diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2015-01-08 18:02:44 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2015-01-22 10:57:44 +0000 |
| commit | ab8707e6875a9fe447ff04fad9053d7d719f89e6 (patch) | |
| tree | 376a47144a8349f7ce3cdf21a1a12694e7f6bba6 /plat/juno/bl2_plat_setup.c | |
| parent | 8c5fe0b5b9f1666b4ddd8f5849de80249cdebe40 (diff) | |
Remove coherent memory from the BL memory maps
This patch extends the build option `USE_COHERENT_MEMORY` to
conditionally remove coherent memory from the memory maps of
all boot loader stages. The patch also adds necessary
documentation for coherent memory removal in firmware-design,
porting and user guides.
Fixes ARM-Software/tf-issues#106
Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
Diffstat (limited to 'plat/juno/bl2_plat_setup.c')
| -rw-r--r-- | plat/juno/bl2_plat_setup.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/plat/juno/bl2_plat_setup.c b/plat/juno/bl2_plat_setup.c index 900a587f..8e7b2a0a 100644 --- a/plat/juno/bl2_plat_setup.c +++ b/plat/juno/bl2_plat_setup.c @@ -47,8 +47,10 @@ extern unsigned long __RO_START__; extern unsigned long __RO_END__; +#if USE_COHERENT_MEM extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; +#endif /* * The next 2 constants identify the extents of the code & RO data region. @@ -59,6 +61,7 @@ extern unsigned long __COHERENT_RAM_END__; #define BL2_RO_BASE (unsigned long)(&__RO_START__) #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) +#if USE_COHERENT_MEM /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be @@ -68,11 +71,11 @@ extern unsigned long __COHERENT_RAM_END__; */ #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif /* Data structure which holds the extents of the trusted RAM for BL2 */ static meminfo_t bl2_tzram_layout -__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), - section("tzfw_coherent_mem"))); +__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE))); /******************************************************************************* * Structure which holds the arguments which need to be passed to BL3-1 @@ -194,9 +197,12 @@ void bl2_plat_arch_setup(void) configure_mmu_el1(bl2_tzram_layout.total_base, bl2_tzram_layout.total_size, BL2_RO_BASE, - BL2_RO_LIMIT, - BL2_COHERENT_RAM_BASE, - BL2_COHERENT_RAM_LIMIT); + BL2_RO_LIMIT +#if USE_COHERENT_MEM + , BL2_COHERENT_RAM_BASE, + BL2_COHERENT_RAM_LIMIT +#endif + ); } /******************************************************************************* |