diff options
author | Soby Mathew <soby.mathew@arm.com> | 2015-01-08 18:02:44 +0000 |
---|---|---|
committer | Dan Handley <dan.handley@arm.com> | 2015-01-22 10:57:44 +0000 |
commit | ab8707e6875a9fe447ff04fad9053d7d719f89e6 (patch) | |
tree | 376a47144a8349f7ce3cdf21a1a12694e7f6bba6 /plat/juno | |
parent | 8c5fe0b5b9f1666b4ddd8f5849de80249cdebe40 (diff) |
Remove coherent memory from the BL memory maps
This patch extends the build option `USE_COHERENT_MEMORY` to
conditionally remove coherent memory from the memory maps of
all boot loader stages. The patch also adds necessary
documentation for coherent memory removal in firmware-design,
porting and user guides.
Fixes ARM-Software/tf-issues#106
Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
Diffstat (limited to 'plat/juno')
-rw-r--r-- | plat/juno/aarch64/juno_common.c | 21 | ||||
-rw-r--r-- | plat/juno/bl1_plat_setup.c | 11 | ||||
-rw-r--r-- | plat/juno/bl2_plat_setup.c | 16 | ||||
-rw-r--r-- | plat/juno/bl31_plat_setup.c | 25 | ||||
-rw-r--r-- | plat/juno/juno_private.h | 18 | ||||
-rw-r--r-- | plat/juno/tsp/tsp_plat_setup.c | 26 |
6 files changed, 87 insertions, 30 deletions
diff --git a/plat/juno/aarch64/juno_common.c b/plat/juno/aarch64/juno_common.c index 8129b051..7ad40d0d 100644 --- a/plat/juno/aarch64/juno_common.c +++ b/plat/juno/aarch64/juno_common.c @@ -140,6 +140,7 @@ const unsigned int num_sec_irqs = sizeof(irq_sec_array) / * Macro generating the code for the function setting up the pagetables as per * the platform memory map & initialize the mmu, for the given exception level ******************************************************************************/ +#if USE_COHERENT_MEM #define DEFINE_CONFIGURE_MMU_EL(_el) \ void configure_mmu_el##_el(unsigned long total_base, \ unsigned long total_size, \ @@ -162,7 +163,25 @@ const unsigned int num_sec_irqs = sizeof(irq_sec_array) / \ enable_mmu_el##_el(0); \ } - +#else +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void configure_mmu_el##_el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add(juno_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el##_el(0); \ + } +#endif /* Define EL1 and EL3 variants of the function initialising the MMU */ DEFINE_CONFIGURE_MMU_EL(1) DEFINE_CONFIGURE_MMU_EL(3) diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c index e27e3948..23e8592b 100644 --- a/plat/juno/bl1_plat_setup.c +++ b/plat/juno/bl1_plat_setup.c @@ -41,6 +41,7 @@ #include "juno_def.h" #include "juno_private.h" +#if USE_COHERENT_MEM /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted RAM @@ -57,6 +58,7 @@ extern unsigned long __COHERENT_RAM_END__; */ #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -189,9 +191,12 @@ void bl1_plat_arch_setup(void) configure_mmu_el3(bl1_tzram_layout.total_base, bl1_tzram_layout.total_size, TZROM_BASE, - TZROM_BASE + TZROM_SIZE, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + TZROM_BASE + TZROM_SIZE +#if USE_COHERENT_MEM + , BL1_COHERENT_RAM_BASE, + BL1_COHERENT_RAM_LIMIT +#endif + ); } /******************************************************************************* diff --git a/plat/juno/bl2_plat_setup.c b/plat/juno/bl2_plat_setup.c index 900a587f..8e7b2a0a 100644 --- a/plat/juno/bl2_plat_setup.c +++ b/plat/juno/bl2_plat_setup.c @@ -47,8 +47,10 @@ extern unsigned long __RO_START__; extern unsigned long __RO_END__; +#if USE_COHERENT_MEM extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; +#endif /* * The next 2 constants identify the extents of the code & RO data region. @@ -59,6 +61,7 @@ extern unsigned long __COHERENT_RAM_END__; #define BL2_RO_BASE (unsigned long)(&__RO_START__) #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) +#if USE_COHERENT_MEM /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be @@ -68,11 +71,11 @@ extern unsigned long __COHERENT_RAM_END__; */ #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif /* Data structure which holds the extents of the trusted RAM for BL2 */ static meminfo_t bl2_tzram_layout -__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), - section("tzfw_coherent_mem"))); +__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE))); /******************************************************************************* * Structure which holds the arguments which need to be passed to BL3-1 @@ -194,9 +197,12 @@ void bl2_plat_arch_setup(void) configure_mmu_el1(bl2_tzram_layout.total_base, bl2_tzram_layout.total_size, BL2_RO_BASE, - BL2_RO_LIMIT, - BL2_COHERENT_RAM_BASE, - BL2_COHERENT_RAM_LIMIT); + BL2_RO_LIMIT +#if USE_COHERENT_MEM + , BL2_COHERENT_RAM_BASE, + BL2_COHERENT_RAM_LIMIT +#endif + ); } /******************************************************************************* diff --git a/plat/juno/bl31_plat_setup.c b/plat/juno/bl31_plat_setup.c index c4504622..ad8ea435 100644 --- a/plat/juno/bl31_plat_setup.c +++ b/plat/juno/bl31_plat_setup.c @@ -48,19 +48,25 @@ ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __RO_END__; +extern unsigned long __BL31_END__; +#if USE_COHERENT_MEM extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; +#endif /* - * The next 2 constants identify the extents of the code & RO data region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL3-1 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. */ #define BL31_RO_BASE (unsigned long)(&__RO_START__) #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) +#if USE_COHERENT_MEM /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be @@ -70,6 +76,7 @@ extern unsigned long __COHERENT_RAM_END__; */ #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif /****************************************************************************** * Placeholder variables for copying the arguments that have been passed to @@ -178,9 +185,13 @@ void bl31_platform_setup(void) void bl31_plat_arch_setup() { configure_mmu_el3(BL31_RO_BASE, - BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE, + (BL31_END - BL31_RO_BASE), BL31_RO_BASE, - BL31_RO_LIMIT, + BL31_RO_LIMIT +#if USE_COHERENT_MEM + , BL31_COHERENT_RAM_BASE, - BL31_COHERENT_RAM_LIMIT); + BL31_COHERENT_RAM_LIMIT +#endif + ); } diff --git a/plat/juno/juno_private.h b/plat/juno/juno_private.h index b7ef4488..70439e8b 100644 --- a/plat/juno/juno_private.h +++ b/plat/juno/juno_private.h @@ -134,15 +134,21 @@ unsigned int platform_get_core_pos(unsigned long mpidr); void configure_mmu_el1(unsigned long total_base, unsigned long total_size, unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); + unsigned long ro_limit +#if USE_COHERENT_MEM + , unsigned long coh_start, + unsigned long coh_limit +#endif + ); void configure_mmu_el3(unsigned long total_base, unsigned long total_size, unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); + unsigned long ro_limit +#if USE_COHERENT_MEM + , unsigned long coh_start, + unsigned long coh_limit +#endif + ); void plat_report_exception(unsigned long type); unsigned long plat_get_ns_image_entrypoint(void); unsigned long platform_get_stack(unsigned long mpidr); diff --git a/plat/juno/tsp/tsp_plat_setup.c b/plat/juno/tsp/tsp_plat_setup.c index 0a9d4cbe..8293a132 100644 --- a/plat/juno/tsp/tsp_plat_setup.c +++ b/plat/juno/tsp/tsp_plat_setup.c @@ -40,19 +40,25 @@ ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __RO_END__; +extern unsigned long __BL32_END__; +#if USE_COHERENT_MEM extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; +#endif /* - * The next 2 constants identify the extents of the code & RO data region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL3-2 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL32_END__ linker symbols + * refer to page-aligned addresses. */ #define BL32_RO_BASE (unsigned long)(&__RO_START__) #define BL32_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL32_END (unsigned long)(&__BL32_END__) +#if USE_COHERENT_MEM /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be @@ -62,6 +68,7 @@ extern unsigned long __COHERENT_RAM_END__; */ #define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif /******************************************************************************* * Initialize the UART @@ -90,9 +97,12 @@ void tsp_platform_setup(void) void tsp_plat_arch_setup(void) { configure_mmu_el1(BL32_RO_BASE, - BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE, + (BL32_END - BL32_RO_BASE), BL32_RO_BASE, - BL32_RO_LIMIT, - BL32_COHERENT_RAM_BASE, - BL32_COHERENT_RAM_LIMIT); + BL32_RO_LIMIT +#if USE_COHERENT_MEM + , BL32_COHERENT_RAM_BASE, + BL32_COHERENT_RAM_LIMIT +#endif + ); } |