diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2017-07-05 17:44:12 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-07-31 11:41:41 -0700 |
| commit | cb95a19a61cb7a9ad30d7c5b4b9a6c8dbd6840a1 (patch) | |
| tree | 00127191b84098a612a69a42c147ac84e33d9971 /plat/nvidia | |
| parent | 1862d6203cb21d1846388e8d7530612a9b98786e (diff) | |
Tegra: implement the early suspend handler
This patch implements the early suspend handler for Tegra SoCs. This
handler is empty for now and the actual support for a particular platform
would be added later.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia')
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_pm.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index 0c25934c..86021ba9 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -36,6 +36,7 @@ uint8_t tegra_fake_system_suspend; * The following platform setup functions are weakly defined. They * provide typical implementations that will be overridden by a SoC. */ +#pragma weak tegra_soc_pwr_domain_suspend_pwrdown_early #pragma weak tegra_soc_pwr_domain_suspend #pragma weak tegra_soc_pwr_domain_on #pragma weak tegra_soc_pwr_domain_off @@ -45,6 +46,11 @@ uint8_t tegra_fake_system_suspend; #pragma weak tegra_soc_prepare_system_off #pragma weak tegra_soc_get_target_pwr_state +int tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) +{ + return PSCI_E_NOT_SUPPORTED; +} + int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) { return PSCI_E_NOT_SUPPORTED; @@ -145,6 +151,17 @@ void tegra_pwr_domain_off(const psci_power_state_t *target_state) /******************************************************************************* * Handler called when a power domain is about to be suspended. The * target_state encodes the power state that each level should transition to. + * This handler is called with SMP and data cache enabled, when + * HW_ASSISTED_COHERENCY = 0 + ******************************************************************************/ +void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) +{ + tegra_soc_pwr_domain_suspend_pwrdown_early(target_state); +} + +/******************************************************************************* + * Handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. ******************************************************************************/ void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) { @@ -315,6 +332,7 @@ static const plat_psci_ops_t tegra_plat_psci_ops = { .cpu_standby = tegra_cpu_standby, .pwr_domain_on = tegra_pwr_domain_on, .pwr_domain_off = tegra_pwr_domain_off, + .pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early, .pwr_domain_suspend = tegra_pwr_domain_suspend, .pwr_domain_on_finish = tegra_pwr_domain_on_finish, .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, |