diff options
| author | Bai Ping <ping.bai@nxp.com> | 2017-08-28 14:22:15 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:08:39 +0300 |
| commit | 5b1cd00a6ea4d4f67d5e4ae9adc87ae690cc62ce (patch) | |
| tree | 2dfed8a7e9c70907200c7855f08b2c17a9b318dd /plat | |
| parent | 7b10c32b2a5dd81c425522dfd7d5c6c7e5e01b82 (diff) | |
fix sw pup/pdn issue on imx8mq
The bits[3:0] of CPU_PGC_PUP/PDN_TRG use core's SW
power up/down. prevous bits assignment is wrong, so
fix it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/imx/imx8mq/gpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/imx/imx8mq/gpc.c b/plat/imx/imx8mq/gpc.c index 51774dd8..d636334b 100644 --- a/plat/imx/imx8mq/gpc.c +++ b/plat/imx/imx8mq/gpc.c @@ -271,7 +271,7 @@ void imx_gpc_set_core_pdn_pup_by_software(unsigned int cpu, bool pdn) /*Set the core PCR bit before sw PUP/PDN trigger */ imx_gpc_set_m_core_pgc(GPC_ARM_PGC + cpu * 0x40, true); - index = cpu < 2 ? cpu : cpu + 1; + index = cpu; val |= (BM_CPU_PGC_SW_PDN_PUP_REQ << index); mmio_write_32(IMX_GPC_BASE + (pdn ? GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ), val); |