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authorBai Ping <ping.bai@nxp.com>2017-10-18 15:23:29 +0800
committerAbel Vesa <abel.vesa@nxp.com>2018-06-11 10:08:40 +0300
commit6fb035381ce6857444af4860a095a1552764abb0 (patch)
tree946f596977debc3dbd9404927d4e12d55e94a4c9 /plat
parent33a7fa4220b8b99430adce131d4b1005a967ac55 (diff)
imx8mq: change the BL31 load address to ocram
Change the BL31 load address to ocram so we can put DDR into low power mode as needed. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'plat')
-rw-r--r--plat/imx/imx8mq/imx8m_bl31_setup.c2
-rw-r--r--plat/imx/imx8mq/include/platform_def.h6
2 files changed, 3 insertions, 5 deletions
diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c
index ac5067b2..96b67b19 100644
--- a/plat/imx/imx8mq/imx8m_bl31_setup.c
+++ b/plat/imx/imx8mq/imx8m_bl31_setup.c
@@ -120,8 +120,6 @@ void bl31_tzc380_setup(void)
/* Enable 1G-5G S/NS RW */
tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
- /* Enable 0x40000000 - 0x40020000 S RW */
- tzc380_configure_region(1, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_128K) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW);
tzc380_dump_state();
}
diff --git a/plat/imx/imx8mq/include/platform_def.h b/plat/imx/imx8mq/include/platform_def.h
index 670f0abf..13a4641f 100644
--- a/plat/imx/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8mq/include/platform_def.h
@@ -19,11 +19,11 @@
#define PLAT_MAX_OFF_STATE 2
#define PLAT_MAX_RET_STATE 1
-#define BL31_BASE 0x40001000
-#define BL31_LIMIT 0x40020000
+#define BL31_BASE 0x910000
+#define BL31_LIMIT 0x920000
/* non-secure uboot base */
-#define PLAT_NS_IMAGE_OFFSET 0x40021000
+#define PLAT_NS_IMAGE_OFFSET 0x40200000
/* GICv3 base address */
#define PLAT_GICD_BASE 0x38800000