imx8mq: add src sip to handle m4

Add src sip to handle M4 boot and status check

Signed-off-by: Peng Fan <peng.fan@nxp.com>

4 files changed, 54 insertions, 0 deletions

diff --git a/plat/imx/common/include/fsl_sip.h b/plat/imx/common/include/fsl_sip.h
index be9af94b..306cdecc 100644
--- a/plat/imx/common/include/fsl_sip.h
+++ b/plat/imx/common/include/fsl_sip.h
@@ -28,4 +28,8 @@
 #define FSL_SIP_BUILDINFO_GET_COMMITHASH	0x00
 
 #define FSL_SIP_DDR_DVFS		0xc2000004
+
+#define FSL_SIP_SRC			0xc2000005
+#define FSL_SIP_SRC_M4_START		0x00
+#define FSL_SIP_SRC_M4_STARTED		0x01
 #endif
diff --git a/plat/imx/common/sip_svc.c b/plat/imx/common/sip_svc.c
index a45a0a35..a5578a8c 100644
--- a/plat/imx/common/sip_svc.c
+++ b/plat/imx/common/sip_svc.c
@@ -44,6 +44,7 @@ extern int imx_cpufreq_handler(uint32_t  smc_fid, u_register_t x1, u_register_t
 extern int imx_srtc_handler(uint32_t smc_fid, u_register_t x1,
 	u_register_t x2, u_register_t x3, u_register_t x4);
 extern int lpddr4_dvfs_handler(uint32_t  smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
+extern int imx_src_handler(uint32_t  smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
 
 /* Setup i.MX platform specific services Services */
 static int32_t plat_svc_setup(void)
@@ -116,6 +117,9 @@ uintptr_t imx_svc_smc_handler(uint32_t smc_fid,
 	case FSL_SIP_DDR_DVFS:
 		SMC_RET1(handle, lpddr4_dvfs_handler(smc_fid, x1, x2, x3));
 		break;
+	case FSL_SIP_SRC:
+		SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3));
+		break;
 #endif
 #if (defined(PLAT_IMX8QM) || defined(PLAT_IMX8QXP))
 	case  FSL_SIP_CPUFREQ:
diff --git a/plat/imx/imx8mq/platform.mk b/plat/imx/imx8mq/platform.mk
index 50196d11..16114123 100644
--- a/plat/imx/imx8mq/platform.mk
+++ b/plat/imx/imx8mq/platform.mk
@@ -11,6 +11,7 @@ BL31_SOURCES		+=	plat/imx/common/imx8_helpers.S		\
 				plat/imx/common/mxcuart_console.S	\
 				plat/imx/common/sip_svc.c		\
 				plat/imx/imx8mq/imx8m_bl31_setup.c	\
+				plat/imx/imx8mq/src.c			\
 				plat/imx/imx8mq/gpc.c			\
 				plat/imx/imx8mq/ddrc.c			\
 				plat/imx/imx8mq/imx8m_psci.c		\
diff --git a/plat/imx/imx8mq/src.c b/plat/imx/imx8mq/src.c
new file mode 100644
index 00000000..4fa0e2c3
--- /dev/null
+++ b/plat/imx/imx8mq/src.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <smcc_helpers.h>
+#include <std_svc.h>
+#include <types.h>
+#include <mmio.h>
+#include <platform_def.h>
+#include <fsl_sip.h>
+#include <soc.h>
+
+#define M4RCR (0xC)
+#define SRC_SCR_M4_ENABLE_OFFSET		3
+#define SRC_SCR_M4_ENABLE_MASK			(1 << 3)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET		0
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK		(1 << 0)
+int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+		    u_register_t x3)
+{
+	uint32_t val;
+
+	switch(x1) {
+	case FSL_SIP_SRC_M4_START:
+		val = mmio_read_32(IMX_SRC_BASE + M4RCR);
+		val &= ~SRC_SCR_M4C_NON_SCLR_RST_MASK;
+		val |= SRC_SCR_M4_ENABLE_MASK;
+		mmio_write_32(IMX_SRC_BASE + M4RCR, val);
+		break;
+	case FSL_SIP_SRC_M4_STARTED:
+		val = mmio_read_32(IMX_SRC_BASE + M4RCR);
+		return !(val & SRC_SCR_M4C_NON_SCLR_RST_MASK);
+	default:
+		return SMC_UNK;
+
+	};
+
+	return 0;
+}