imx: imx8mq: add SOC info SIP support for i.MX8MQ

i.MX8MQ does NOT update revision info in ANATOP_DIGPROG
register, so the revision info needs to read from ROM,
for security reason, this needs to be done in ATF, so
add this SIP support for kernel.

The A0 chip's ROM version is located at 0x800, and B0
chip is located at 0x83c.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

5 files changed, 34 insertions, 0 deletions

diff --git a/plat/imx/common/include/fsl_sip.h b/plat/imx/common/include/fsl_sip.h
index 306cdecc..458e19f6 100644
--- a/plat/imx/common/include/fsl_sip.h
+++ b/plat/imx/common/include/fsl_sip.h
@@ -32,4 +32,7 @@
 #define FSL_SIP_SRC			0xc2000005
 #define FSL_SIP_SRC_M4_START		0x00
 #define FSL_SIP_SRC_M4_STARTED		0x01
+
+#define FSL_SIP_GET_SOC_INFO            0xc2000006
+
 #endif
diff --git a/plat/imx/common/sip_svc.c b/plat/imx/common/sip_svc.c
index a5578a8c..34b15702 100644
--- a/plat/imx/common/sip_svc.c
+++ b/plat/imx/common/sip_svc.c
@@ -45,6 +45,7 @@ extern int imx_srtc_handler(uint32_t smc_fid, u_register_t x1,
 	u_register_t x2, u_register_t x3, u_register_t x4);
 extern int lpddr4_dvfs_handler(uint32_t  smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
 extern int imx_src_handler(uint32_t  smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
+extern int imx_soc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
 
 /* Setup i.MX platform specific services Services */
 static int32_t plat_svc_setup(void)
@@ -120,6 +121,9 @@ uintptr_t imx_svc_smc_handler(uint32_t smc_fid,
 	case FSL_SIP_SRC:
 		SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3));
 		break;
+	case FSL_SIP_GET_SOC_INFO:
+		SMC_RET1(handle, imx_soc_handler(smc_fid, x1, x2, x3));
+		break;
 #endif
 #if (defined(PLAT_IMX8QM) || defined(PLAT_IMX8QXP))
 	case  FSL_SIP_CPUFREQ:
diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c
index e61ab5b7..176283c0 100644
--- a/plat/imx/imx8mq/imx8m_bl31_setup.c
+++ b/plat/imx/imx8mq/imx8m_bl31_setup.c
@@ -206,6 +206,8 @@ void bl31_plat_arch_setup(void)
 			MT_MEMORY | MT_RO);
 	mmap_add_region(IMX_BOOT_UART_BASE, IMX_BOOT_UART_BASE,
 			0x1000,	MT_DEVICE | MT_RW);
+	mmap_add_region(IMX_ROM_BASE, IMX_ROM_BASE,
+			0x1000,	MT_DEVICE | MT_RW);
 	/* map the AIPS1 */
 	mmap_add_region(IMX_AIPS1_BASE, IMX_AIPS1_BASE, 0x200000, MT_DEVICE | MT_RW);
 	mmap_add_region(PLAT_GICD_BASE, PLAT_GICD_BASE, 0x80000,
diff --git a/plat/imx/imx8mq/include/platform_def.h b/plat/imx/imx8mq/include/platform_def.h
index b3ea3f3d..faff2021 100644
--- a/plat/imx/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8mq/include/platform_def.h
@@ -54,6 +54,7 @@
 #define IMX_DDRC_BASE			0x3d400000
 #define IMX_DDRPHY_BASE			0x3c000000
 #define IMX_DDR_IPS_BASE		0x3d000000
+#define IMX_ROM_BASE			0x0
 
 #define COUNTER_FREQUENCY		8000000 /* 8MHz */
 
diff --git a/plat/imx/imx8mq/src.c b/plat/imx/imx8mq/src.c
index 4fa0e2c3..25382dd0 100644
--- a/plat/imx/imx8mq/src.c
+++ b/plat/imx/imx8mq/src.c
@@ -21,6 +21,11 @@
 #define SRC_SCR_M4_ENABLE_MASK			(1 << 3)
 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET		0
 #define SRC_SCR_M4C_NON_SCLR_RST_MASK		(1 << 0)
+
+#define DIGPROG		0x6c
+#define SW_INFO_A0	0x800
+#define SW_INFO_B0	0x83C
+
 int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
 		    u_register_t x3)
 {
@@ -43,3 +48,22 @@ int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
 
 	return 0;
 }
+
+int imx_soc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+		    u_register_t x3)
+{
+	uint32_t val;
+	uint32_t rom_version;
+
+	val = mmio_read_32(IMX_ANAMIX_BASE + DIGPROG);
+	rom_version = mmio_read_32(IMX_ROM_BASE + SW_INFO_A0);
+	if (rom_version != 0x10) {
+		rom_version = mmio_read_32(IMX_ROM_BASE + SW_INFO_B0);
+		if (rom_version >= 0x20) {
+			val &= ~0xff;
+			val |= rom_version;
+		}
+	}
+
+	return val;
+}