diff options
| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2013-11-12 16:41:16 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2013-11-27 15:31:06 +0000 |
| commit | c10bd2ce69e54a8c71fa773810e130fc465c03ac (patch) | |
| tree | 34e34f2b4a21a448c4823f8b591579cfd1ca9f36 /plat | |
| parent | ba3155bb0eb51ca4b5dcf43877c394381cff2fb1 (diff) | |
Move generic architectural setup out of blx_plat_arch_setup().
blx_plat_arch_setup() should only perform platform-specific
architectural setup, e.g. enabling the MMU. This patch moves
generic architectural setup code out of blx_plat_arch_setup().
Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/fvp/bl2_plat_setup.c | 15 | ||||
| -rw-r--r-- | plat/fvp/bl31_plat_setup.c | 8 |
2 files changed, 0 insertions, 23 deletions
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c index e38f00bd..4bb10157 100644 --- a/plat/fvp/bl2_plat_setup.c +++ b/plat/fvp/bl2_plat_setup.c @@ -124,24 +124,9 @@ void bl2_platform_setup() ******************************************************************************/ void bl2_plat_arch_setup() { - unsigned long sctlr; - - /* Enable instruction cache. */ - sctlr = read_sctlr(); - sctlr |= SCTLR_I_BIT; - write_sctlr(sctlr); - - /* - * Very simple exception vectors which assert if any exception other - * than a single SMC call from BL2 to pass control to BL31 in EL3 is - * received. - */ - write_vbar((unsigned long) early_exceptions); - configure_mmu(&bl2_tzram_layout, (unsigned long) &BL2_RO_BASE, (unsigned long) &BL2_STACKS_BASE, (unsigned long) &BL2_COHERENT_RAM_BASE, (unsigned long) &BL2_RW_BASE); - return; } diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c index 6c8635fa..7aa1182d 100644 --- a/plat/fvp/bl31_plat_setup.c +++ b/plat/fvp/bl31_plat_setup.c @@ -166,14 +166,6 @@ void bl31_platform_setup() ******************************************************************************/ void bl31_plat_arch_setup() { - unsigned long sctlr; - - /* Enable instruction cache. */ - sctlr = read_sctlr(); - sctlr |= SCTLR_I_BIT; - write_sctlr(sctlr); - - write_vbar((unsigned long) runtime_exceptions); configure_mmu(&bl31_tzram_layout, (unsigned long) &BL31_RO_BASE, (unsigned long) &BL31_STACKS_BASE, |