diff options
| author | Yatharth Kochar <yatharth.kochar@arm.com> | 2014-11-20 18:09:41 +0000 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2015-01-26 19:04:15 +0000 |
| commit | 79a97b2ef723365663b403223002d29aeb675c85 (patch) | |
| tree | 7845353dd58e3d75b4b66abd414b6f19ca78b41a /services/std_svc | |
| parent | 9d212557979e3c99b48ca18d9bd5583926368391 (diff) | |
Call reset handlers upon BL3-1 entry.
This patch adds support to call the reset_handler() function in BL3-1 in the
cold and warm boot paths when another Boot ROM reset_handler() has already run.
This means the BL1 and BL3-1 versions of the CPU and platform specific reset
handlers may execute different code to each other. This enables a developer to
perform additional actions or undo actions already performed during the first
call of the reset handlers e.g. apply additional errata workarounds.
Typically, the reset handler will be first called from the BL1 Boot ROM. Any
additional functionality can be added to the reset handler when it is called
from BL3-1 resident in RW memory. The constant FIRST_RESET_HANDLER_CALL is used
to identify whether this is the first version of the reset handler code to be
executed or an overridden version of the code.
The Cortex-A57 errata workarounds are applied only if they have not already been
applied.
Fixes ARM-software/tf-issue#275
Change-Id: Id295f106e4fda23d6736debdade2ac7f2a9a9053
Diffstat (limited to 'services/std_svc')
| -rw-r--r-- | services/std_svc/psci/psci_entry.S | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/services/std_svc/psci/psci_entry.S b/services/std_svc/psci/psci_entry.S index 81450128..3e67d344 100644 --- a/services/std_svc/psci/psci_entry.S +++ b/services/std_svc/psci/psci_entry.S @@ -54,9 +54,18 @@ psci_aff_suspend_finish_entry: psci_aff_common_finish_entry: #if !RESET_TO_BL31 /* --------------------------------------------- + * Perform any processor specific actions which + * undo or are in addition to the actions + * performed by the reset handler in the BootROM + * (BL1) e.g. cache, tlb invalidations, errata + * workarounds etc. + * --------------------------------------------- + */ + bl reset_handler + + /* --------------------------------------------- * Enable the instruction cache, stack pointer - * and data access alignment checks. Also, set - * the EL3 exception endianess to little-endian. + * and data access alignment checks. * It can be assumed that BL3-1 entrypoint code * will do this when RESET_TO_BL31 is set. The * same assumption cannot be made when another |