diff options
| author | Achin Gupta <achin.gupta@arm.com> | 2014-07-18 18:38:28 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-07-28 10:10:22 +0100 |
| commit | ec3c10039bdc2c1468a8ba95fbbe9de78628eea5 (patch) | |
| tree | b8781fc14291cb3afd32a49ef8bbe5f60bdf0188 /services/std_svc | |
| parent | 539a7b383d52493a94df4f5da8f74aa102429fa0 (diff) | |
Simplify management of SCTLR_EL3 and SCTLR_EL1
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of
SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset
in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in
S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They
do not have to be saved and restored either. The M, WXN and optionally the C
bit are set in the enable_mmu_elX() function. This is done during both the warm
and cold boot paths.
Fixes ARM-software/tf-issues#226
Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
Diffstat (limited to 'services/std_svc')
| -rw-r--r-- | services/std_svc/psci/psci_entry.S | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/services/std_svc/psci/psci_entry.S b/services/std_svc/psci/psci_entry.S index 192b638c..e9ad1305 100644 --- a/services/std_svc/psci/psci_entry.S +++ b/services/std_svc/psci/psci_entry.S @@ -54,6 +54,25 @@ psci_aff_suspend_finish_entry: adr x23, psci_afflvl_suspend_finishers psci_aff_common_finish_entry: +#if !RESET_TO_BL31 + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks. Also, set + * the EL3 exception endianess to little-endian. + * It can be assumed that BL3-1 entrypoint code + * will do this when RESET_TO_BL31 is set. The + * same assumption cannot be made when another + * boot loader executes before BL3-1 in the warm + * boot path e.g. BL1. + * --------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, x1 + msr sctlr_el3, x0 + isb +#endif + /* --------------------------------------------- * Initialise the pcpu cache pointer for the CPU * --------------------------------------------- |