diff options
| -rw-r--r-- | bl31/aarch64/runtime_exceptions.S | 247 | ||||
| -rw-r--r-- | docs/firmware-design.md | 2 | ||||
| -rw-r--r-- | docs/interrupt-framework-design.md | 38 | ||||
| -rw-r--r-- | docs/porting-guide.md | 12 | ||||
| -rw-r--r-- | include/common/aarch32/el3_common_macros.S | 8 | ||||
| -rw-r--r-- | include/common/aarch64/el3_common_macros.S | 7 | ||||
| -rw-r--r-- | include/lib/aarch32/arch.h | 10 | ||||
| -rw-r--r-- | include/lib/aarch32/arch_helpers.h | 3 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 5 | ||||
| -rw-r--r-- | include/lib/aarch64/arch_helpers.h | 3 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch32/context_mgmt.c | 14 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 10 | ||||
| -rw-r--r-- | readme.md | 4 |
13 files changed, 203 insertions, 160 deletions
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index f333bf16..220d1cc1 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -38,10 +38,10 @@ .globl runtime_exceptions - /* ----------------------------------------------------- - * Handle SMC exceptions separately from other sync. - * exceptions. - * ----------------------------------------------------- + /* --------------------------------------------------------------------- + * This macro handles Synchronous exceptions. + * Only SMC exceptions are supported. + * --------------------------------------------------------------------- */ .macro handle_sync_exception /* Enable the SError interrupt */ @@ -50,11 +50,10 @@ str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] #if ENABLE_RUNTIME_INSTRUMENTATION - /* - * Read the timestamp value and store it in per-cpu data. - * The value will be extracted from per-cpu data by the - * C level SMC handler and saved to the PMF timestamp region. + * Read the timestamp value and store it in per-cpu data. The value + * will be extracted from per-cpu data by the C level SMC handler and + * saved to the PMF timestamp region. */ mrs x30, cntpct_el0 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] @@ -66,26 +65,22 @@ mrs x30, esr_el3 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + /* Handle SMC exceptions separately from other synchronous exceptions */ cmp x30, #EC_AARCH32_SMC b.eq smc_handler32 cmp x30, #EC_AARCH64_SMC b.eq smc_handler64 - /* ----------------------------------------------------- - * The following code handles any synchronous exception - * that is not an SMC. - * ----------------------------------------------------- - */ - + /* Other kinds of synchronous exceptions are not handled */ bl report_unhandled_exception .endm - /* ----------------------------------------------------- - * This macro handles FIQ or IRQ interrupts i.e. EL3, - * S-EL1 and NS interrupts. - * ----------------------------------------------------- + /* --------------------------------------------------------------------- + * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS + * interrupts. + * --------------------------------------------------------------------- */ .macro handle_interrupt_exception label /* Enable the SError interrupt */ @@ -94,10 +89,7 @@ str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] bl save_gp_registers - /* - * Save the EL3 system registers needed to return from - * this exception. - */ + /* Save the EL3 system registers needed to return from this exception */ mrs x0, spsr_el3 mrs x1, elr_el3 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] @@ -109,36 +101,34 @@ mov sp, x2 /* - * Find out whether this is a valid interrupt type. If the - * interrupt controller reports a spurious interrupt then - * return to where we came from. + * Find out whether this is a valid interrupt type. + * If the interrupt controller reports a spurious interrupt then return + * to where we came from. */ bl plat_ic_get_pending_interrupt_type cmp x0, #INTR_TYPE_INVAL b.eq interrupt_exit_\label /* - * Get the registered handler for this interrupt type. A - * NULL return value could be 'cause of the following - * conditions: + * Get the registered handler for this interrupt type. + * A NULL return value could be 'cause of the following conditions: * - * a. An interrupt of a type was routed correctly but a - * handler for its type was not registered. + * a. An interrupt of a type was routed correctly but a handler for its + * type was not registered. * - * b. An interrupt of a type was not routed correctly so - * a handler for its type was not registered. + * b. An interrupt of a type was not routed correctly so a handler for + * its type was not registered. * - * c. An interrupt of a type was routed correctly to EL3, - * but was deasserted before its pending state could - * be read. Another interrupt of a different type pended - * at the same time and its type was reported as pending - * instead. However, a handler for this type was not - * registered. + * c. An interrupt of a type was routed correctly to EL3, but was + * deasserted before its pending state could be read. Another + * interrupt of a different type pended at the same time and its + * type was reported as pending instead. However, a handler for this + * type was not registered. * - * a. and b. can only happen due to a programming error. - * The occurrence of c. could be beyond the control of - * Trusted Firmware. It makes sense to return from this - * exception instead of reporting an error. + * a. and b. can only happen due to a programming error. The + * occurrence of c. could be beyond the control of Trusted Firmware. + * It makes sense to return from this exception instead of reporting an + * error. */ bl get_interrupt_type_handler cbz x0, interrupt_exit_\label @@ -153,7 +143,7 @@ /* Restore the reference to the 'handle' i.e. SP_EL3 */ mov x2, x20 - /* x3 will point to a cookie (not used now) */ + /* x3 will point to a cookie (not used now) */ mov x3, xzr /* Call the interrupt type handler */ @@ -180,24 +170,20 @@ interrupt_exit_\label: vector_base runtime_exceptions - /* ----------------------------------------------------- - * Current EL with _sp_el0 : 0x0 - 0x200 - * ----------------------------------------------------- + /* --------------------------------------------------------------------- + * Current EL with SP_EL0 : 0x0 - 0x200 + * --------------------------------------------------------------------- */ vector_entry sync_exception_sp_el0 - /* ----------------------------------------------------- - * We don't expect any synchronous exceptions from EL3 - * ----------------------------------------------------- - */ + /* We don't expect any synchronous exceptions from EL3 */ bl report_unhandled_exception check_vector_size sync_exception_sp_el0 - /* ----------------------------------------------------- - * EL3 code is non-reentrant. Any asynchronous exception - * is a serious error. Loop infinitely. - * ----------------------------------------------------- - */ vector_entry irq_sp_el0 + /* + * EL3 code is non-reentrant. Any asynchronous exception is a serious + * error. Loop infinitely. + */ bl report_unhandled_interrupt check_vector_size irq_sp_el0 @@ -211,18 +197,16 @@ vector_entry serror_sp_el0 bl report_unhandled_exception check_vector_size serror_sp_el0 - /* ----------------------------------------------------- - * Current EL with SPx: 0x200 - 0x400 - * ----------------------------------------------------- + /* --------------------------------------------------------------------- + * Current EL with SP_ELx: 0x200 - 0x400 + * --------------------------------------------------------------------- */ - vector_entry sync_exception_sp_elx - /* ----------------------------------------------------- - * This exception will trigger if anything went wrong - * during a previous exception entry or exit or while - * handling an earlier unexpected synchronous exception. - * There is a high probability that SP_EL3 is corrupted. - * ----------------------------------------------------- + /* + * This exception will trigger if anything went wrong during a previous + * exception entry or exit or while handling an earlier unexpected + * synchronous exception. There is a high probability that SP_EL3 is + * corrupted. */ bl report_unhandled_exception check_vector_size sync_exception_sp_elx @@ -239,27 +223,20 @@ vector_entry serror_sp_elx bl report_unhandled_exception check_vector_size serror_sp_elx - /* ----------------------------------------------------- + /* --------------------------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x600 - * ----------------------------------------------------- + * --------------------------------------------------------------------- */ vector_entry sync_exception_aarch64 - /* ----------------------------------------------------- - * This exception vector will be the entry point for - * SMCs and traps that are unhandled at lower ELs most - * commonly. SP_EL3 should point to a valid cpu context - * where the general purpose and system register state - * can be saved. - * ----------------------------------------------------- + /* + * This exception vector will be the entry point for SMCs and traps + * that are unhandled at lower ELs most commonly. SP_EL3 should point + * to a valid cpu context where the general purpose and system register + * state can be saved. */ handle_sync_exception check_vector_size sync_exception_aarch64 - /* ----------------------------------------------------- - * Asynchronous exceptions from lower ELs are not - * currently supported. Report their occurrence. - * ----------------------------------------------------- - */ vector_entry irq_aarch64 handle_interrupt_exception irq_aarch64 check_vector_size irq_aarch64 @@ -269,30 +246,27 @@ vector_entry fiq_aarch64 check_vector_size fiq_aarch64 vector_entry serror_aarch64 + /* + * SError exceptions from lower ELs are not currently supported. + * Report their occurrence. + */ bl report_unhandled_exception check_vector_size serror_aarch64 - /* ----------------------------------------------------- + /* --------------------------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x800 - * ----------------------------------------------------- + * --------------------------------------------------------------------- */ vector_entry sync_exception_aarch32 - /* ----------------------------------------------------- - * This exception vector will be the entry point for - * SMCs and traps that are unhandled at lower ELs most - * commonly. SP_EL3 should point to a valid cpu context - * where the general purpose and system register state - * can be saved. - * ----------------------------------------------------- + /* + * This exception vector will be the entry point for SMCs and traps + * that are unhandled at lower ELs most commonly. SP_EL3 should point + * to a valid cpu context where the general purpose and system register + * state can be saved. */ handle_sync_exception check_vector_size sync_exception_aarch32 - /* ----------------------------------------------------- - * Asynchronous exceptions from lower ELs are not - * currently supported. Report their occurrence. - * ----------------------------------------------------- - */ vector_entry irq_aarch32 handle_interrupt_exception irq_aarch32 check_vector_size irq_aarch32 @@ -302,34 +276,34 @@ vector_entry fiq_aarch32 check_vector_size fiq_aarch32 vector_entry serror_aarch32 + /* + * SError exceptions from lower ELs are not currently supported. + * Report their occurrence. + */ bl report_unhandled_exception check_vector_size serror_aarch32 - /* ----------------------------------------------------- + /* --------------------------------------------------------------------- * The following code handles secure monitor calls. - * Depending upon the execution state from where the SMC - * has been invoked, it frees some general purpose - * registers to perform the remaining tasks. They - * involve finding the runtime service handler that is - * the target of the SMC & switching to runtime stacks - * (SP_EL0) before calling the handler. + * Depending upon the execution state from where the SMC has been + * invoked, it frees some general purpose registers to perform the + * remaining tasks. They involve finding the runtime service handler + * that is the target of the SMC & switching to runtime stacks (SP_EL0) + * before calling the handler. * - * Note that x30 has been explicitly saved and can be - * used here - * ----------------------------------------------------- + * Note that x30 has been explicitly saved and can be used here + * --------------------------------------------------------------------- */ func smc_handler smc_handler32: /* Check whether aarch32 issued an SMC64 */ tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited - /* ----------------------------------------------------- - * Since we're are coming from aarch32, x8-x18 need to - * be saved as per SMC32 calling convention. If a lower - * EL in aarch64 is making an SMC32 call then it must - * have saved x8-x17 already therein. - * ----------------------------------------------------- + /* + * Since we're are coming from aarch32, x8-x18 need to be saved as per + * SMC32 calling convention. If a lower EL in aarch64 is making an + * SMC32 call then it must have saved x8-x17 already therein. */ stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] @@ -340,15 +314,14 @@ smc_handler32: /* x4-x7, x18, sp_el0 are saved below */ smc_handler64: - /* ----------------------------------------------------- - * Populate the parameters for the SMC handler. We - * already have x0-x4 in place. x5 will point to a - * cookie (not used now). x6 will point to the context - * structure (SP_EL3) and x7 will contain flags we need - * to pass to the handler Hence save x5-x7. Note that x4 - * only needs to be preserved for AArch32 callers but we - * do it for AArch64 callers as well for convenience - * ----------------------------------------------------- + /* + * Populate the parameters for the SMC handler. + * We already have x0-x4 in place. x5 will point to a cookie (not used + * now). x6 will point to the context structure (SP_EL3) and x7 will + * contain flags we need to pass to the handler Hence save x5-x7. + * + * Note: x4 only needs to be preserved for AArch32 callers but we do it + * for AArch64 callers as well for convenience */ stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] @@ -370,12 +343,10 @@ smc_handler64: adr x14, rt_svc_descs_indices ldrb w15, [x14, x16] - /* ----------------------------------------------------- - * Restore the saved C runtime stack value which will - * become the new SP_EL0 i.e. EL3 runtime stack. It was - * saved in the 'cpu_context' structure prior to the last - * ERET from EL3. - * ----------------------------------------------------- + /* + * Restore the saved C runtime stack value which will become the new + * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' + * structure prior to the last ERET from EL3. */ ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] @@ -388,22 +359,19 @@ smc_handler64: /* Switch to SP_EL0 */ msr spsel, #0 - /* ----------------------------------------------------- + /* * Get the descriptor using the index * x11 = (base + off), x15 = index * * handler = (base + off) + (index << log2(size)) - * ----------------------------------------------------- */ lsl w10, w15, #RT_SVC_SIZE_LOG2 ldr x15, [x11, w10, uxtw] - /* ----------------------------------------------------- - * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there - * is a world switch during SMC handling. - * TODO: Revisit if all system registers can be saved - * later. - * ----------------------------------------------------- + /* + * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world + * switch during SMC handling. + * TODO: Revisit if all system registers can be saved later. */ mrs x16, spsr_el3 mrs x17, elr_el3 @@ -416,12 +384,10 @@ smc_handler64: mov sp, x12 - /* ----------------------------------------------------- - * Call the Secure Monitor Call handler and then drop - * directly into el3_exit() which will program any - * remaining architectural state prior to issuing the - * ERET to the desired lower EL. - * ----------------------------------------------------- + /* + * Call the Secure Monitor Call handler and then drop directly into + * el3_exit() which will program any remaining architectural state + * prior to issuing the ERET to the desired lower EL. */ #if DEBUG cbz x15, rt_svc_fw_critical_error @@ -436,7 +402,7 @@ smc_unknown: * callers will find the registers contents unchanged, but AArch64 * callers will find the registers modified (with stale earlier NS * content). Either way, we aren't leaking any secure information - * through them + * through them. */ mov w0, #SMC_UNK b restore_gp_registers_callee_eret @@ -447,6 +413,7 @@ smc_prohibited: eret rt_svc_fw_critical_error: - msr spsel, #1 /* Switch to SP_ELx */ + /* Switch to SP_ELx */ + msr spsel, #1 bl report_unhandled_exception endfunc smc_handler diff --git a/docs/firmware-design.md b/docs/firmware-design.md index abe7dc5a..c37f9c5f 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -1077,7 +1077,7 @@ reset handling functions. Details for implementing a CPU specific reset handler can be found in Section 8. Details for implementing a platform specific reset handler can be -found in the [Porting Guide](see the `plat_reset_handler()` function). +found in the [Porting Guide] (see the `plat_reset_handler()` function). When adding functionality to a reset handler, keep in mind that if a different reset handling behavior is required between the first and the subsequent diff --git a/docs/interrupt-framework-design.md b/docs/interrupt-framework-design.md index e50d1758..b4689496 100644 --- a/docs/interrupt-framework-design.md +++ b/docs/interrupt-framework-design.md @@ -335,9 +335,9 @@ during the registration of a handler for an interrupt type. This component declares the following prototype for a handler of an interrupt type. typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, - uint32_t flags, - void *handle, - void *cookie); + uint32_t flags, + void *handle, + void *cookie); The `id` is parameter is reserved and could be used in the future for passing the interrupt id of the highest pending interrupt only if there is a foolproof @@ -358,10 +358,16 @@ The `handle` parameter points to the `cpu_context` structure of the current CPU for the security state specified in the `flags` parameter. Once the handler routine completes, execution will return to either the secure -or non-secure state. The handler routine should return a pointer to -`cpu_context` structure of the current CPU for the target security state. It -should treat all error conditions as critical errors and take appropriate action -within its implementation e.g. use assertion failures. +or non-secure state. The handler routine must return a pointer to +`cpu_context` structure of the current CPU for the target security state. On +AArch64, this return value is currently ignored by the caller as the +appropriate `cpu_context` to be used is expected to be set by the handler +via the context management library APIs. +A portable interrupt handler implementation must set the target context both in +the structure pointed to by the returned pointer and via the context management +library APIs. The handler should treat all error conditions as critical errors +and take appropriate action within its implementation e.g. use assertion +failures. The runtime firmware provides the following API for registering a handler for a particular type of interrupt. A Secure Payload Dispatcher service should use @@ -370,8 +376,8 @@ interrupts. This API also requires the caller to specify the routing model for the type of interrupt. int32_t register_interrupt_type_handler(uint32_t type, - interrupt_type_handler handler, - uint64_t flags); + interrupt_type_handler handler, + uint64_t flags); The `type` parameter can be one of the three interrupt types listed above i.e. @@ -962,13 +968,13 @@ as the resume SMC FID. It is important to note that `TSP_FID_RESUME` is a secure software sequence for issuing a `standard` SMC would look like this, assuming `P.STATE.I=0` in the non secure state : - int rc; - rc = smc(TSP_STD_SMC_FID, ...); /* Issue a Standard SMC call */ - /* The pending non-secure interrupt is handled by the interrupt handler - and returns back here. */ - while (rc == SMC_PREEMPTED) { /* Check if the SMC call is preempted */ - rc = smc(TSP_FID_RESUME); /* Issue resume SMC call */ - } + int rc; + rc = smc(TSP_STD_SMC_FID, ...); /* Issue a Standard SMC call */ + /* The pending non-secure interrupt is handled by the interrupt handler + and returns back here. */ + while (rc == SMC_PREEMPTED) { /* Check if the SMC call is preempted */ + rc = smc(TSP_FID_RESUME); /* Issue resume SMC call */ + } The `TSP_STD_SMC_FID` is any `standard` SMC function identifier and the smc() function invokes a SMC call with the required arguments. The pending non-secure diff --git a/docs/porting-guide.md b/docs/porting-guide.md index 7534e395..74a0a85f 100644 --- a/docs/porting-guide.md +++ b/docs/porting-guide.md @@ -1834,6 +1834,18 @@ The `target_state` (first argument) has a similar meaning as described in the `pwr_domain_on_finish()` operation. The generic code expects the platform to succeed. +#### plat_psci_ops.system_off() + +This function is called by PSCI implementation in response to a `SYSTEM_OFF` +call. It performs the platform-specific system poweroff sequence after +notifying the Secure Payload Dispatcher. + +#### plat_psci_ops.system_reset() + +This function is called by PSCI implementation in response to a `SYSTEM_RESET` +call. It performs the platform-specific system reset sequence after +notifying the Secure Payload Dispatcher. + #### plat_psci_ops.validate_power_state() This function is called by the PSCI implementation during the `CPU_SUSPEND` diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S index 50ce952f..0018ea4b 100644 --- a/include/common/aarch32/el3_common_macros.S +++ b/include/common/aarch32/el3_common_macros.S @@ -67,6 +67,14 @@ orr r0, r0, #SCR_SIF_BIT stcopr r0, SCR + /* ----------------------------------------------------------------- + * Reset those registers that may have architecturally unknown reset + * values + * ----------------------------------------------------------------- + */ + mov r0, #0 + stcopr r0, SDCR + /* ----------------------------------------------------- * Enable the Asynchronous data abort now that the * exception vectors have been setup. diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S index 9b22a734..a4189116 100644 --- a/include/common/aarch64/el3_common_macros.S +++ b/include/common/aarch64/el3_common_macros.S @@ -77,6 +77,13 @@ */ mov x0, #(SCR_RES1_BITS | SCR_EA_BIT | SCR_SIF_BIT) msr scr_el3, x0 + + /* --------------------------------------------------------------------- + * Reset registers that may have architecturally unknown reset values + * --------------------------------------------------------------------- + */ + msr mdcr_el3, xzr + /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception * vectors have been setup. diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 4968e245..3c5ab26e 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -318,6 +318,11 @@ #define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ +/* PMCR definitions */ +#define PMCR_N_SHIFT 11 +#define PMCR_N_MASK 0x1f +#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) + /******************************************************************************* * Definitions of register offsets and fields in the CNTCTLBase Frame of the * system level implementation of the Generic Timer. @@ -375,6 +380,11 @@ #define CSSELR p15, 2, c0, c0, 0 #define CCSIDR p15, 1, c0, c0, 0 +/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ +#define HDCR p15, 4, c1, c1, 1 +#define SDCR p15, 0, c1, c3, 1 +#define PMCR p15, 0, c9, c12, 0 + /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ #define ICC_IAR1 p15, 0, c12, c12, 0 #define ICC_IAR0 p15, 0, c12, c8, 0 diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index 3b4349c3..0633bca2 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -249,6 +249,9 @@ DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1) DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0) DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1) +DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR) +DEFINE_COPROCR_READ_FUNC(pmcr, PMCR) + /* * TLBI operation prototypes */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index bef60323..a034ae20 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -411,4 +411,9 @@ #define CNTACR_RWVT_SHIFT 0x4 #define CNTACR_RWPT_SHIFT 0x5 +/* PMCR_EL0 definitions */ +#define PMCR_EL0_N_SHIFT 11 +#define PMCR_EL0_N_MASK 0x1f +#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) + #endif /* __ARCH_H__ */ diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index 4d936ad5..37db0313 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -279,6 +279,9 @@ DEFINE_SYSREG_READ_FUNC(isr_el1) DEFINE_SYSREG_READ_FUNC(ctr_el0) +DEFINE_SYSREG_RW_FUNCS(mdcr_el2) +DEFINE_SYSREG_READ_FUNC(pmcr_el0) + DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index 02ae2a7e..29532e8c 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -200,7 +200,10 @@ void cm_prepare_el3_exit(uint32_t security_state) isb(); } else if (read_id_pfr1() & (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) { - /* Set the NS bit to access HCR, HCPTR, CNTHCTL, VPIDR, VMPIDR */ + /* + * Set the NS bit to access NS copies of certain banked + * registers + */ write_scr(read_scr() | SCR_NS_BIT); isb(); @@ -231,6 +234,15 @@ void cm_prepare_el3_exit(uint32_t security_state) * translation are disabled. */ write64_vttbr(0); + + /* + * Avoid unexpected debug traps in case where HDCR + * is not completely reset by the hardware - set + * HDCR.HPMN to PMCR.N and zero the remaining bits. + * The HDCR.HPMN and PMCR.N fields are the same size + * (5 bits) and HPMN is at offset zero within HDCR. + */ + write_hdcr((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT); isb(); write_scr(read_scr() & ~SCR_NS_BIT); diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 4b5d0ee5..fadc1dbf 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -259,6 +259,16 @@ void cm_prepare_el3_exit(uint32_t security_state) * translation are disabled. */ write_vttbr_el2(0); + /* + * Avoid unexpected debug traps in case where MDCR_EL2 + * is not completely reset by the hardware - set + * MDCR_EL2.HPMN to PMCR_EL0.N and zero the remaining + * bits. + * MDCR_EL2.HPMN and PMCR_EL0.N fields are the same size + * (5 bits) and HPMN is at offset zero within MDCR_EL2. + */ + write_mdcr_el2((read_pmcr_el0() & PMCR_EL0_N_BITS) + >> PMCR_EL0_N_SHIFT); } } @@ -105,7 +105,7 @@ The AArch64 build of this release has been tested on variants r0, r1 and r2 of the [Juno ARM Development Platform] [Juno] with [Linaro Release 16.06]. The AArch64 build of this release has been tested on the following ARM -[FVP]s (64-bit host machine only): +[FVP]s (64-bit host machine only, with [Linaro Release 16.06]): * `Foundation_Platform` (Version 10.1, Build 10.1.32) * `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) @@ -114,7 +114,7 @@ The AArch64 build of this release has been tested on the following ARM * `FVP_Base_Cortex-A57x2-A53x4` (Version 7.7, Build 0.8.7701) The AArch32 build of this release has been tested on the following ARM -[FVP]s (64-bit host machine only): +[FVP]s (64-bit host machine only, with [Linaro Release 16.06]): * `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) * `FVP_Base_Cortex-A32x4` (Version 10.1, Build 10.1.32) |