diff options
208 files changed, 984 insertions, 1199 deletions
@@ -273,8 +273,7 @@ endif CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \ -Wmissing-include-dirs $(ERRORS) $(WARNINGS) ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \ - -D__ASSEMBLY__ -ffreestanding \ - -Wa,--fatal-warnings + -ffreestanding -Wa,--fatal-warnings TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ -ffreestanding -fno-builtin -Wall -std=gnu99 \ -Os -ffunction-sections -fdata-sections @@ -735,12 +734,6 @@ else $(eval $(call add_define,PRELOADED_BL33_BASE)) endif endif -# Define the AARCH32/AARCH64 flag based on the ARCH flag -ifeq (${ARCH},aarch32) - $(eval $(call add_define,AARCH32)) -else - $(eval $(call add_define,AARCH64)) -endif # Define the DYN_DISABLE_AUTH flag only if set. ifeq (${DYN_DISABLE_AUTH},1) @@ -763,14 +756,22 @@ all: msg_start msg_start: @echo "Building ${PLAT}" -# Check if deprecated declarations and cpp warnings should be treated as error or not. ifeq (${ERROR_DEPRECATED},0) +# Check if deprecated declarations and cpp warnings should be treated as error or not. ifneq ($(findstring clang,$(notdir $(CC))),) CPPFLAGS += -Wno-error=deprecated-declarations else CPPFLAGS += -Wno-error=deprecated-declarations -Wno-error=cpp endif +# __ASSEMBLY__ is deprecated in favor of the compiler-builtin __ASSEMBLER__. +ASFLAGS += -D__ASSEMBLY__ +# AARCH32/AARCH64 macros are deprecated in favor of the compiler-builtin __aarch64__. +ifeq (${ARCH},aarch32) + $(eval $(call add_define,AARCH32)) +else + $(eval $(call add_define,AARCH64)) endif +endif # !ERROR_DEPRECATED $(eval $(call MAKE_LIB_DIRS)) $(eval $(call MAKE_LIB,c)) diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index 76a43753..d222b9c5 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -520,7 +520,7 @@ static int bl1_fwu_image_execute(unsigned int image_id, INFO("BL1-FWU: Executing Secure image\n"); -#ifdef AARCH64 +#ifdef __aarch64__ /* Save NS-EL1 system registers. */ cm_el1_sysregs_context_save(NON_SECURE); #endif @@ -531,7 +531,7 @@ static int bl1_fwu_image_execute(unsigned int image_id, /* Update the secure image id. */ sec_exec_image_id = image_id; -#ifdef AARCH64 +#ifdef __aarch64__ *handle = cm_get_context(SECURE); #else *handle = smc_get_ctx(SECURE); @@ -584,7 +584,7 @@ static register_t bl1_fwu_image_resume(register_t image_param, INFO("BL1-FWU: Resuming %s world context\n", (resume_sec_state == SECURE) ? "secure" : "normal"); -#ifdef AARCH64 +#ifdef __aarch64__ /* Save the EL1 system registers of calling world. */ cm_el1_sysregs_context_save(caller_sec_state); @@ -641,7 +641,7 @@ static int bl1_fwu_sec_image_done(void **handle, unsigned int flags) sec_exec_image_id = INVALID_IMAGE_ID; INFO("BL1-FWU: Resuming Normal world context\n"); -#ifdef AARCH64 +#ifdef __aarch64__ /* * Secure world is done so no need to save the context. * Just restore the Non-Secure context. diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index fce14f55..d44b46dc 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -59,7 +59,7 @@ void bl1_setup(void) /* Perform early platform-specific setup */ bl1_early_platform_setup(); -#ifdef AARCH64 +#ifdef __aarch64__ /* * Update pointer authentication key before the MMU is enabled. It is * saved in the rodata section, that can be writen before enabling the @@ -67,7 +67,7 @@ void bl1_setup(void) * in the early platform setup. */ bl_handle_pauth(); -#endif /* AARCH64 */ +#endif /* __aarch64__ */ /* Perform late platform-specific setup */ bl1_plat_arch_setup(); @@ -97,10 +97,10 @@ void bl1_main(void) /* * Ensure that MMU/Caches and coherency are turned on */ -#ifdef AARCH32 - val = read_sctlr(); -#else +#ifdef __aarch64__ val = read_sctlr_el3(); +#else + val = read_sctlr(); #endif assert(val & SCTLR_M_BIT); assert(val & SCTLR_C_BIT); @@ -198,11 +198,11 @@ static void bl1_load_bl2(void) ******************************************************************************/ void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) { -#ifdef AARCH32 - NOTICE("BL1: Booting BL32\n"); -#else +#ifdef __aarch64__ NOTICE("BL1: Booting BL31\n"); -#endif /* AARCH32 */ +#else + NOTICE("BL1: Booting BL32\n"); +#endif /* __aarch64__ */ print_entry_point_info(bl_ep_info); } diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c index 7d8d60c1..79b0e717 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c @@ -15,10 +15,10 @@ #include "bl2_private.h" -#ifdef AARCH32 -#define NEXT_IMAGE "BL32" -#else +#ifdef __aarch64__ #define NEXT_IMAGE "BL31" +#else +#define NEXT_IMAGE "BL32" #endif #if !BL2_AT_EL3 @@ -31,7 +31,7 @@ void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, /* Perform early platform-specific setup */ bl2_early_platform_setup2(arg0, arg1, arg2, arg3); -#ifdef AARCH64 +#ifdef __aarch64__ /* * Update pointer authentication key before the MMU is enabled. It is * saved in the rodata section, that can be writen before enabling the @@ -39,7 +39,7 @@ void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, * in the early platform setup. */ bl_handle_pauth(); -#endif /* AARCH64 */ +#endif /* __aarch64__ */ /* Perform late platform-specific setup */ bl2_plat_arch_setup(); @@ -55,7 +55,7 @@ void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, /* Perform early platform-specific setup */ bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3); -#ifdef AARCH64 +#ifdef __aarch64__ /* * Update pointer authentication key before the MMU is enabled. It is * saved in the rodata section, that can be writen before enabling the @@ -63,7 +63,7 @@ void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, * in the early platform setup. */ bl_handle_pauth(); -#endif /* AARCH64 */ +#endif /* __aarch64__ */ /* Perform late platform-specific setup */ bl2_el3_plat_arch_setup(); @@ -97,14 +97,14 @@ void bl2_main(void) next_bl_ep_info = bl2_load_images(); #if !BL2_AT_EL3 -#ifdef AARCH32 +#ifndef __aarch64__ /* * For AArch32 state BL1 and BL2 share the MMU setup. * Given that BL2 does not map BL1 regions, MMU needs * to be disabled in order to go back to BL1. */ disable_mmu_icache_secure(); -#endif /* AARCH32 */ +#endif /* !__aarch64__ */ console_flush(); diff --git a/bl2u/bl2u_main.c b/bl2u/bl2u_main.c index d3c83ccc..d49c9ce9 100644 --- a/bl2u/bl2u_main.c +++ b/bl2u/bl2u_main.c @@ -45,14 +45,14 @@ void bl2u_main(void) console_flush(); -#ifdef AARCH32 +#ifndef __aarch64__ /* * For AArch32 state BL1 and BL2U share the MMU setup. * Given that BL2U does not map BL1 regions, MMU needs * to be disabled in order to go back to BL1. */ disable_mmu_icache_secure(); -#endif /* AARCH32 */ +#endif /* !__aarch64__ */ /* * Indicate that BL2U is done and resume back to diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S index 40506785..2c410298 100644 --- a/bl31/aarch64/crash_reporting.S +++ b/bl31/aarch64/crash_reporting.S @@ -28,7 +28,7 @@ */ .section .rodata.crash_prints, "aS" print_spacer: - .asciz " =\t\t0x" + .asciz " = 0x" gp_regs: .asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\ @@ -55,11 +55,11 @@ aarch32_regs: #endif /* CTX_INCLUDE_AARCH32_REGS */ panic_msg: - .asciz "PANIC in EL3 at x30 = 0x" + .asciz "PANIC in EL3.\nx30" excpt_msg: - .asciz "Unhandled Exception in EL3.\nx30 =\t\t0x" + .asciz "Unhandled Exception in EL3.\nx30" intr_excpt_msg: - .asciz "Unhandled Interrupt Exception in EL3.\nx30 =\t\t0x" + .asciz "Unhandled Interrupt Exception in EL3.\nx30" /* * Helper function to print newline to console. @@ -94,10 +94,11 @@ test_size_list: mov x4, x6 /* asm_print_str updates x4 to point to next entry in list */ bl asm_print_str + /* x0 = number of symbols printed + 1 */ + sub x0, x4, x6 /* update x6 with the updated list pointer */ mov x6, x4 - adr x4, print_spacer - bl asm_print_str + bl print_alignment ldr x4, [x7], #REGSZ bl asm_print_hex bl print_newline @@ -107,6 +108,20 @@ exit_size_print: ret endfunc size_controlled_print + /* ----------------------------------------------------- + * This function calculates and prints required number + * of space characters followed by "= 0x", based on the + * length of ascii register name. + * x0: length of ascii register name + 1 + * ------------------------------------------------------ + */ +func print_alignment + /* The minimum ascii length is 3, e.g. for "x0" */ + adr x4, print_spacer - 3 + add x4, x4, x0 + b asm_print_str +endfunc print_alignment + /* * Helper function to store x8 - x15 registers to * the crash buf. The system registers values are @@ -189,7 +204,7 @@ endfunc report_unhandled_interrupt * ----------------------------------------------------- */ func el3_panic - msr spsel, #1 + msr spsel, #MODE_SP_ELX prepare_crash_buf_save_x0_x1 adr x0, panic_msg mov sp, x0 @@ -230,6 +245,9 @@ func do_crash_reporting /* Print the crash message. sp points to the crash message */ mov x4, sp bl asm_print_str + /* Print spaces to align "x30" string */ + mov x0, #4 + bl print_alignment /* load the crash buf address */ mrs x0, tpidr_el3 /* report x30 first from the crash buf */ diff --git a/bl32/tsp/tsp_private.h b/bl32/tsp/tsp_private.h index e39f2916..cbd527f3 100644 --- a/bl32/tsp/tsp_private.h +++ b/bl32/tsp/tsp_private.h @@ -20,7 +20,7 @@ #define TSP_ARGS_END 0x40 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -148,6 +148,6 @@ tsp_args_t *tsp_system_off_main(uint64_t arg0, uint64_t arg7); uint64_t tsp_main(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* TSP_PRIVATE_H */ diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S index da740ef2..ac47cbe9 100644 --- a/common/aarch64/debug.S +++ b/common/aarch64/debug.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ .globl asm_print_str .globl asm_print_hex + .globl asm_print_hex_bits .globl asm_assert .globl do_panic @@ -107,8 +108,11 @@ endfunc asm_print_str * Clobber: x30, x0 - x3, x5 */ func asm_print_hex - mov x3, x30 mov x5, #64 /* No of bits to convert to ascii */ + + /* Convert to ascii number of bits in x5 */ +asm_print_hex_bits: + mov x3, x30 1: sub x5, x5, #4 lsrv x0, x4, x5 diff --git a/common/backtrace/backtrace.c b/common/backtrace/backtrace.c index 53f8b071..506d4a48 100644 --- a/common/backtrace/backtrace.c +++ b/common/backtrace/backtrace.c @@ -93,7 +93,7 @@ static const char *get_el_str(unsigned int el) * Returns true if the address points to a virtual address that can be read at * the current EL, false otherwise. */ -#ifdef AARCH64 +#ifdef __aarch64__ static bool is_address_readable(uintptr_t addr) { unsigned int el = get_current_el(); @@ -123,7 +123,7 @@ static bool is_address_readable(uintptr_t addr) return true; } -#else /* if AARCH32 */ +#else /* !__aarch64__ */ static bool is_address_readable(uintptr_t addr) { unsigned int el = get_current_el(); @@ -144,7 +144,7 @@ static bool is_address_readable(uintptr_t addr) return true; } -#endif +#endif /* __aarch64__ */ /* * Returns true if all the bytes in a given object are in mapped memory and an @@ -207,7 +207,7 @@ static bool is_valid_frame_record(struct frame_record *fr) */ static struct frame_record *adjust_frame_record(struct frame_record *fr) { -#ifdef AARCH64 +#ifdef __aarch64__ return fr; #else return (struct frame_record *)((uintptr_t)fr - 4U); diff --git a/common/bl_common.c b/common/bl_common.c index 61f031bf..a09cd717 100644 --- a/common/bl_common.c +++ b/common/bl_common.c @@ -236,7 +236,7 @@ void print_entry_point_info(const entry_point_info_t *ep_info) PRINT_IMAGE_ARG(1); PRINT_IMAGE_ARG(2); PRINT_IMAGE_ARG(3); -#ifndef AARCH32 +#ifdef __aarch64__ PRINT_IMAGE_ARG(4); PRINT_IMAGE_ARG(5); PRINT_IMAGE_ARG(6); @@ -245,7 +245,7 @@ void print_entry_point_info(const entry_point_info_t *ep_info) #undef PRINT_IMAGE_ARG } -#ifdef AARCH64 +#ifdef __aarch64__ /******************************************************************************* * Handle all possible cases regarding ARMv8.3-PAuth. ******************************************************************************/ @@ -293,4 +293,4 @@ void bl_handle_pauth(void) #endif /* ENABLE_PAUTH */ } -#endif /* AARCH64 */ +#endif /* __aarch64__ */ diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 858996c8..b447f149 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -50,12 +50,13 @@ Install the required packages to build TF-A with the following command: TF-A has been tested with Linaro Release 18.04. -Download and install the AArch32 or AArch64 little-endian GCC cross compiler. If -you would like to use the latest features available, download GCC 8.2-2019.01 -compiler from `arm Developer page`_. Otherwise, the `Linaro Release Notes`_ -documents which version of the compiler to use for a given Linaro Release. Also, -these `Linaro instructions`_ provide further guidance and a script, which can be -used to download Linaro deliverables automatically. +Download and install the AArch32 (arm-eabi) or AArch64 little-endian +(aarch64-linux-gnu) GCC cross compiler. If you would like to use the latest +features available, download GCC 8.3-2019.03 compiler from +`arm Developer page`_. Otherwise, the `Linaro Release Notes`_ documents which +version of the compiler to use for a given Linaro Release. Also, these +`Linaro instructions`_ provide further guidance and a script, which can be used +to download Linaro deliverables automatically. Optionally, TF-A can be built using clang version 4.0 or newer or Arm Compiler 6. See instructions below on how to switch the default compiler. @@ -138,7 +139,7 @@ Building TF-A .. code:: shell - export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf- + export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi- It is possible to build TF-A using Clang or Arm Compiler 6. To do so ``CC`` needs to point to the clang or armclang binary, which will diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c index d184054e..d0c5abc7 100644 --- a/drivers/arm/ccn/ccn.c +++ b/drivers/arm/ccn/ccn.c @@ -17,7 +17,7 @@ #include "ccn_private.h" static const ccn_desc_t *ccn_plat_desc; -#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) +#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) DEFINE_BAKERY_LOCK(ccn_lock); #endif @@ -264,7 +264,7 @@ static void ccn_snoop_dvm_do_op(unsigned long long rn_id_map, assert(ccn_plat_desc); assert(ccn_plat_desc->periphbase); -#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) +#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) bakery_lock_get(&ccn_lock); #endif start_region_id = region_id; @@ -284,7 +284,7 @@ static void ccn_snoop_dvm_do_op(unsigned long long rn_id_map, rn_id_map); } -#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) +#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) bakery_lock_release(&ccn_lock); #endif } diff --git a/drivers/arm/css/sds/sds_private.h b/drivers/arm/css/sds/sds_private.h index 2101dd04..d801a04d 100644 --- a/drivers/arm/css/sds/sds_private.h +++ b/drivers/arm/css/sds/sds_private.h @@ -58,7 +58,7 @@ #define SDS_REGION_REGIONSIZE_OFFSET 0x4 #define SDS_REGION_DESC_SIZE 0x8 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> @@ -95,6 +95,6 @@ typedef struct region_descriptor { & SDS_REGION_SCH_VERSION_MASK) #define GET_SDS_REGION_SIZE(region) ((((region_desc_t *)(region))->reg[1])) -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* SDS_PRIVATE_H */ diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index a94dbf67..94a20ba0 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -73,12 +73,12 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) plat_driver_data->interrupt_props != NULL : 1); /* Check for system register support */ -#ifdef AARCH32 - assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); -#else +#ifdef __aarch64__ assert((read_id_aa64pfr0_el1() & (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); -#endif /* AARCH32 */ +#else + assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); +#endif /* __aarch64__ */ /* The GIC version should be 3.0 */ gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h index 92066e1f..327a9a14 100644 --- a/drivers/arm/gic/v3/gicv3_private.h +++ b/drivers/arm/gic/v3/gicv3_private.h @@ -40,16 +40,16 @@ static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr, * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] * are zeroes. */ -#ifdef AARCH32 +#ifdef __aarch64__ static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) { - return (((typer_val) >> 32) & U(0xffffff)); + return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | + ((typer_val >> 32) & U(0xffffff)); } #else static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) { - return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | - ((typer_val >> 32) & U(0xffffff)); + return (((typer_val) >> 32) & U(0xffffff)); } #endif diff --git a/drivers/imx/uart/imx_uart.h b/drivers/imx/uart/imx_uart.h index b71504c7..4f6d3de2 100644 --- a/drivers/imx/uart/imx_uart.h +++ b/drivers/imx/uart/imx_uart.h @@ -152,7 +152,7 @@ #define IMX_UART_TS_RXFULL BIT(3) #define IMX_UART_TS_SOFTRST BIT(0) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ typedef struct { console_t console; @@ -163,6 +163,6 @@ int console_imx_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_imx_uart_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* IMX_UART_H */ diff --git a/drivers/renesas/rcar/delay/micro_delay.h b/drivers/renesas/rcar/delay/micro_delay.h index 193daba6..37b71f80 100644 --- a/drivers/renesas/rcar/delay/micro_delay.h +++ b/drivers/renesas/rcar/delay/micro_delay.h @@ -7,7 +7,7 @@ #ifndef MICRO_DELAY_H #define MICRO_DELAY_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> void rcar_micro_delay(uint64_t micro_sec); #endif diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c index f4c9d3ab..32e04a73 100644 --- a/drivers/renesas/rcar/pwrc/pwrc.c +++ b/drivers/renesas/rcar/pwrc/pwrc.c @@ -148,7 +148,7 @@ RCAR_INSTANTIATE_LOCK #define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57) #define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START); IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END); IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START); diff --git a/drivers/renesas/rcar/pwrc/pwrc.h b/drivers/renesas/rcar/pwrc/pwrc.h index e67c6ef2..2b817839 100644 --- a/drivers/renesas/rcar/pwrc/pwrc.h +++ b/drivers/renesas/rcar/pwrc/pwrc.h @@ -38,7 +38,7 @@ #define RCAR_CLUSTER_CA53 (1U) #define RCAR_CLUSTER_CA57 (2U) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr); void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr); void rcar_pwrc_clusteroff(uint64_t mpidr); diff --git a/include/arch/aarch32/smccc_helpers.h b/include/arch/aarch32/smccc_helpers.h index d3e5e59c..b2ee3cfe 100644 --- a/include/arch/aarch32/smccc_helpers.h +++ b/include/arch/aarch32/smccc_helpers.h @@ -24,7 +24,7 @@ #define SMC_CTX_PMCR U(0x88) #define SMC_CTX_SIZE U(0x90) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -156,6 +156,6 @@ void smc_set_next_ctx(unsigned int security_state); /* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */ void *smc_get_next_ctx(void); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* SMCCC_HELPERS_H */ diff --git a/include/arch/aarch64/smccc_helpers.h b/include/arch/aarch64/smccc_helpers.h index e28697d7..fac6fd9c 100644 --- a/include/arch/aarch64/smccc_helpers.h +++ b/include/arch/aarch64/smccc_helpers.h @@ -9,7 +9,7 @@ #include <lib/smccc.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdbool.h> @@ -82,6 +82,6 @@ _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \ } while (false) -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* SMCCC_HELPERS_H */ diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h index 937b8c7e..d81f4340 100644 --- a/include/bl1/bl1.h +++ b/include/bl1/bl1.h @@ -61,7 +61,7 @@ #define is_fwu_fid(_fid) \ ((_fid >= FWU_SMC_FID_START) && (_fid <= FWU_SMC_FID_END)) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <lib/cassert.h> @@ -98,5 +98,5 @@ CASSERT(FWU_NUM_SMC_CALLS == \ void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, meminfo_t *bl2_mem_layout); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* BL1_H */ diff --git a/include/bl31/ehf.h b/include/bl31/ehf.h index ee00d093..c13d28c3 100644 --- a/include/bl31/ehf.h +++ b/include/bl31/ehf.h @@ -7,7 +7,7 @@ #ifndef EHF_H #define EHF_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <cdefs.h> #include <stdint.h> @@ -87,6 +87,6 @@ void ehf_register_priority_handler(unsigned int pri, ehf_handler_t handler); void ehf_allow_ns_preemption(uint64_t preempt_ret_code); unsigned int ehf_is_ns_preemption_allowed(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* EHF_H */ diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index b1683cc1..8bb1bab2 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -79,7 +79,7 @@ #define get_interrupt_src_ss(flag) (((flag) >> INTR_SRC_SS_FLAG_SHIFT) & \ INTR_SRC_SS_FLAG_MASK) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <errno.h> #include <stdint.h> @@ -143,5 +143,5 @@ interrupt_type_handler_t get_interrupt_type_handler(uint32_t type); int disable_intr_rm_local(uint32_t type, uint32_t security_state); int enable_intr_rm_local(uint32_t type, uint32_t security_state); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* INTERRUPT_MGMT_H */ diff --git a/include/bl32/tsp/tsp.h b/include/bl32/tsp/tsp.h index 18d3079e..637e14ab 100644 --- a/include/bl32/tsp/tsp.h +++ b/include/bl32/tsp/tsp.h @@ -84,7 +84,7 @@ #define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -106,6 +106,6 @@ typedef struct tsp_vectors { void tsp_setup(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* TSP_H */ diff --git a/include/common/bl_common.h b/include/common/bl_common.h index eb96df0b..896a03f0 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -11,11 +11,11 @@ #include <common/param_header.h> #include <lib/utils_def.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> #include <lib/cassert.h> -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #include <export/common/bl_common_exp.h> @@ -91,7 +91,7 @@ #define __TEXT_END__ Load$$__TEXT_EPILOGUE__$$Base #endif /* USE_ARM_LINK */ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* * Declarations of linker defined symbols to help determine memory layout of @@ -178,6 +178,6 @@ void setup_page_tables(const struct mmap_region *bl_regions, void bl_handle_pauth(void); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* BL_COMMON_H */ diff --git a/include/common/debug.h b/include/common/debug.h index f8faf683..245e6986 100644 --- a/include/common/debug.h +++ b/include/common/debug.h @@ -27,7 +27,7 @@ #define LOG_LEVEL_INFO U(40) #define LOG_LEVEL_VERBOSE U(50) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <cdefs.h> #include <stdarg.h> @@ -110,5 +110,5 @@ void __dead2 __stack_chk_fail(void); void tf_log(const char *fmt, ...) __printflike(1, 2); void tf_log_set_max_level(unsigned int log_level); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* DEBUG_H */ diff --git a/include/common/ep_info.h b/include/common/ep_info.h index 6cb903ef..4bfa1fa6 100644 --- a/include/common/ep_info.h +++ b/include/common/ep_info.h @@ -9,10 +9,10 @@ #include <common/param_header.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> #include <lib/cassert.h> -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #include <export/common/ep_info_exp.h> @@ -30,7 +30,7 @@ #define SET_SECURITY_STATE(x, security) \ ((x) = ((x) & ~EP_SECURITY_MASK) | (security)) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* * Compile time assertions related to the 'entry_point_info' structure to @@ -41,7 +41,7 @@ CASSERT(ENTRY_POINT_INFO_PC_OFFSET == __builtin_offsetof(entry_point_info_t, pc), \ assert_BL31_pc_offset_mismatch); -#ifdef AARCH32 +#ifndef __aarch64__ CASSERT(ENTRY_POINT_INFO_LR_SVC_OFFSET == __builtin_offsetof(entry_point_info_t, lr_svc), assert_entrypoint_lr_offset_error); @@ -56,6 +56,6 @@ CASSERT(sizeof(uintptr_t) == __builtin_offsetof(entry_point_info_t, pc), \ assert_entrypoint_and_spsr_should_be_adjacent); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* EP_INFO_H */ diff --git a/include/common/interrupt_props.h b/include/common/interrupt_props.h index 6c6a8536..07bafaae 100644 --- a/include/common/interrupt_props.h +++ b/include/common/interrupt_props.h @@ -7,7 +7,7 @@ #ifndef INTERRUPT_PROPS_H #define INTERRUPT_PROPS_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* Create an interrupt property descriptor from various interrupt properties */ #define INTR_PROP_DESC(num, pri, grp, cfg) \ @@ -25,5 +25,5 @@ typedef struct interrupt_prop { unsigned int intr_cfg:2; } interrupt_prop_t; -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* INTERRUPT_PROPS_H */ diff --git a/include/common/param_header.h b/include/common/param_header.h index b8852869..4dab4e3c 100644 --- a/include/common/param_header.h +++ b/include/common/param_header.h @@ -9,9 +9,9 @@ #include <stdbool.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #include <export/common/param_header_exp.h> diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h index e5e36c71..472a32a1 100644 --- a/include/common/runtime_svc.h +++ b/include/common/runtime_svc.h @@ -20,15 +20,15 @@ * Constants to allow the assembler access a runtime service * descriptor */ -#ifdef AARCH32 -#define RT_SVC_SIZE_LOG2 U(4) -#define RT_SVC_DESC_INIT U(8) -#define RT_SVC_DESC_HANDLE U(12) -#else +#ifdef __aarch64__ #define RT_SVC_SIZE_LOG2 U(5) #define RT_SVC_DESC_INIT U(16) #define RT_SVC_DESC_HANDLE U(24) -#endif /* AARCH32 */ +#else +#define RT_SVC_SIZE_LOG2 U(4) +#define RT_SVC_DESC_INIT U(8) +#define RT_SVC_DESC_HANDLE U(12) +#endif /* __aarch64__ */ #define SIZEOF_RT_SVC_DESC (U(1) << RT_SVC_SIZE_LOG2) @@ -39,7 +39,7 @@ */ #define MAX_RT_SVCS U(128) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* Prototype for runtime service initializing function */ typedef int32_t (*rt_svc_init_t)(void); @@ -134,5 +134,5 @@ void init_crash_reporting(void); extern uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* RUNTIME_SVC_H */ diff --git a/include/drivers/arm/cci.h b/include/drivers/arm/cci.h index c5ddcfd4..5aea95a0 100644 --- a/include/drivers/arm/cci.h +++ b/include/drivers/arm/cci.h @@ -100,7 +100,7 @@ #define SLAVE_IF_UNUSED -1 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -121,5 +121,5 @@ void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters); void cci_enable_snoop_dvm_reqs(unsigned int master_id); void cci_disable_snoop_dvm_reqs(unsigned int master_id); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CCI_H */ diff --git a/include/drivers/arm/ccn.h b/include/drivers/arm/ccn.h index 9c3abac6..7f737681 100644 --- a/include/drivers/arm/ccn.h +++ b/include/drivers/arm/ccn.h @@ -46,7 +46,7 @@ */ #define CCN_GET_RUN_STATE(pstate) (pstate & 0xf) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> /* @@ -109,5 +109,5 @@ unsigned long long ccn_read_node_reg(node_types_t node_type, unsigned int node_id, unsigned int reg_offset); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CCN_H */ diff --git a/include/drivers/arm/css/sds.h b/include/drivers/arm/css/sds.h index 114ae925..db4cbaaf 100644 --- a/include/drivers/arm/css/sds.h +++ b/include/drivers/arm/css/sds.h @@ -70,7 +70,7 @@ #define SDS_ERR_STRUCT_NOT_FOUND -3 #define SDS_ERR_STRUCT_NOT_FINALIZED -4 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> @@ -85,6 +85,6 @@ int sds_struct_read(uint32_t structure_id, unsigned int fld_off, void *data, size_t size, sds_access_mode_t mode); int sds_struct_write(uint32_t structure_id, unsigned int fld_off, void *data, size_t size, sds_access_mode_t mode); -#endif /*__ASSEMBLY__ */ +#endif /*__ASSEMBLER__ */ #endif /* SDS_H */ diff --git a/include/drivers/arm/fvp/fvp_pwrc.h b/include/drivers/arm/fvp/fvp_pwrc.h index ca173f36..39e25162 100644 --- a/include/drivers/arm/fvp/fvp_pwrc.h +++ b/include/drivers/arm/fvp/fvp_pwrc.h @@ -35,7 +35,7 @@ #define PSYSR_INVALID U(0xffffffff) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -50,6 +50,6 @@ void fvp_pwrc_clr_wen(u_register_t mpidr); unsigned int fvp_pwrc_read_psysr(u_register_t mpidr); unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* FVP_PWRC_H */ diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h index 6bc5101d..ebcb216d 100644 --- a/include/drivers/arm/gicv2.h +++ b/include/drivers/arm/gicv2.h @@ -116,7 +116,7 @@ /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ #define INT_ID_MASK U(0x3ff) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <cdefs.h> #include <stdint.h> @@ -184,5 +184,5 @@ void gicv2_clear_interrupt_pending(unsigned int id); unsigned int gicv2_set_pmr(unsigned int mask); void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* GICV2_H */ diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 72221acb..9c72d4df 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -208,7 +208,7 @@ #define GITS_CTLR_QUIESCENT_SHIFT 31 #define GITS_CTLR_QUIESCENT_BIT BIT_32(GITS_CTLR_QUIESCENT_SHIFT) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdbool.h> #include <stdint.h> @@ -406,5 +406,5 @@ void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num); void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num); unsigned int gicv3_set_pmr(unsigned int mask); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* GICV3_H */ diff --git a/include/drivers/arm/pl011.h b/include/drivers/arm/pl011.h index f201f004..8733d196 100644 --- a/include/drivers/arm/pl011.h +++ b/include/drivers/arm/pl011.h @@ -83,7 +83,7 @@ #define CONSOLE_T_PL011_BASE CONSOLE_T_DRVDATA -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -101,6 +101,6 @@ typedef struct { int console_pl011_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_pl011_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* PL011_H */ diff --git a/include/drivers/arm/sp805.h b/include/drivers/arm/sp805.h index 551bfe4b..b00ede1d 100644 --- a/include/drivers/arm/sp805.h +++ b/include/drivers/arm/sp805.h @@ -21,7 +21,7 @@ #define SP805_CTR_RESEN (U(1) << 1) #define SP805_CTR_INTEN (U(1) << 0) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -31,6 +31,6 @@ void sp805_start(uintptr_t base, unsigned int ticks); void sp805_stop(uintptr_t base); void sp805_refresh(uintptr_t base, unsigned int ticks); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* SP805_H */ diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h index 98ef0ec1..32aeb035 100644 --- a/include/drivers/arm/tzc400.h +++ b/include/drivers/arm/tzc400.h @@ -93,7 +93,7 @@ #define TZC_400_REGION_SIZE U(0x20) #define TZC_400_ACTION_OFF U(0x4) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <cdefs.h> #include <stdint.h> @@ -154,6 +154,6 @@ static inline void tzc_disable_filters(void) tzc400_disable_filters(); } -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* TZC400_H */ diff --git a/include/drivers/arm/tzc_dmc500.h b/include/drivers/arm/tzc_dmc500.h index 24bfaeb1..cce074cb 100644 --- a/include/drivers/arm/tzc_dmc500.h +++ b/include/drivers/arm/tzc_dmc500.h @@ -121,7 +121,7 @@ /* Length of registers for configuring each region */ #define TZC_DMC500_REGION_SIZE U(0x018) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -147,5 +147,5 @@ void tzc_dmc500_config_complete(void); int tzc_dmc500_verify_complete(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* TZC_DMC500_H */ diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h index d143d735..acfde268 100644 --- a/include/drivers/auth/mbedtls/mbedtls_config.h +++ b/include/drivers/auth/mbedtls/mbedtls_config.h @@ -86,7 +86,7 @@ /* Memory buffer allocator options */ #define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* System headers required to build mbed TLS with the current configuration */ #include <stdlib.h> #include "mbedtls/check_config.h" diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h index 0a1cf778..64a062ca 100644 --- a/include/drivers/cadence/cdns_uart.h +++ b/include/drivers/cadence/cdns_uart.h @@ -27,7 +27,7 @@ #define CONSOLE_T_CDNS_BASE CONSOLE_T_DRVDATA -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -45,6 +45,6 @@ typedef struct { int console_cdns_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_cdns_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* CDNS_UART_H */ diff --git a/include/drivers/console.h b/include/drivers/console.h index f31de954..cada771b 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h @@ -28,7 +28,7 @@ /* Returned by console_xxx() if no registered console implements xxx. */ #define ERROR_NO_VALID_CONSOLE (-128) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -75,6 +75,6 @@ int console_getc(void); /* Flush all consoles registered for the current state. */ int console_flush(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CONSOLE_H */ diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h index 1aa4c889..85babb8d 100644 --- a/include/drivers/marvell/cache_llc.h +++ b/include/drivers/marvell/cache_llc.h @@ -27,7 +27,7 @@ #define LLC_EXCLUSIVE_EN 0x100 #define LLC_WAY_MASK 0xFFFFFFFF -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ void llc_cache_sync(int ap_index); void llc_flush_all(int ap_index); void llc_clean_all(int ap_index); diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h index 546d9f13..b0d1ec98 100644 --- a/include/drivers/marvell/ccu.h +++ b/include/drivers/marvell/ccu.h @@ -10,7 +10,7 @@ #ifndef CCU_H #define CCU_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <drivers/marvell/addr_map.h> #endif @@ -36,7 +36,7 @@ #define CCU_SRAM_WIN_CR CCU_WIN_CR_OFFSET(MVEBU_AP0, 1) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ int init_ccu(int); void ccu_win_check(struct addr_map_win *win); void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id); diff --git a/include/drivers/marvell/uart/a3700_console.h b/include/drivers/marvell/uart/a3700_console.h index 5511d96c..517f01a8 100644 --- a/include/drivers/marvell/uart/a3700_console.h +++ b/include/drivers/marvell/uart/a3700_console.h @@ -56,7 +56,7 @@ #define CONSOLE_T_A3700_BASE CONSOLE_T_DRVDATA -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -74,6 +74,6 @@ typedef struct { int console_a3700_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_a3700_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* A3700_CONSOLE_H */ diff --git a/include/drivers/meson/meson_console.h b/include/drivers/meson/meson_console.h index 5da1e3fd..70e3b0bd 100644 --- a/include/drivers/meson/meson_console.h +++ b/include/drivers/meson/meson_console.h @@ -11,7 +11,7 @@ #define CONSOLE_T_MESON_BASE CONSOLE_T_DRVDATA -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -32,6 +32,6 @@ typedef struct { int console_meson_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_meson_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* MESON_CONSOLE_H */ diff --git a/include/drivers/renesas/rcar/console/console.h b/include/drivers/renesas/rcar/console/console.h index 5bc10b7b..0e4ed8f3 100644 --- a/include/drivers/renesas/rcar/console/console.h +++ b/include/drivers/renesas/rcar/console/console.h @@ -9,7 +9,7 @@ #define CONSOLE_T_RCAR_BASE CONSOLE_T_DRVDATA -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -27,6 +27,6 @@ typedef struct { int console_rcar_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_rcar_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* RCAR_PRINTF_H */ diff --git a/include/drivers/st/stm32_console.h b/include/drivers/st/stm32_console.h index b3037682..a2ad87cb 100644 --- a/include/drivers/st/stm32_console.h +++ b/include/drivers/st/stm32_console.h @@ -11,7 +11,7 @@ #define CONSOLE_T_STM32_BASE CONSOLE_T_DRVDATA -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -29,6 +29,6 @@ struct console_stm32 { int console_stm32_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, struct console_stm32 *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* STM32_CONSOLE_H */ diff --git a/include/drivers/st/stm32_gpio.h b/include/drivers/st/stm32_gpio.h index 4320eafc..e241f584 100644 --- a/include/drivers/st/stm32_gpio.h +++ b/include/drivers/st/stm32_gpio.h @@ -45,13 +45,13 @@ #define GPIO_PULL_DOWN 0x02 #define GPIO_PULL_MASK U(0x03) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> int dt_set_pinctrl_config(int node); void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, uint32_t pull, uint32_t alternate, uint8_t status); void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* STM32_GPIO_H */ diff --git a/include/drivers/ti/uart/uart_16550.h b/include/drivers/ti/uart/uart_16550.h index 92b1ea8c..32e38f0a 100644 --- a/include/drivers/ti/uart/uart_16550.h +++ b/include/drivers/ti/uart/uart_16550.h @@ -73,7 +73,7 @@ #define CONSOLE_T_16550_BASE CONSOLE_T_DRVDATA -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -91,6 +91,6 @@ typedef struct { int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_16550_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* UART_16550_H */ diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h index a2f540c6..1fece01a 100644 --- a/include/lib/bakery_lock.h +++ b/include/lib/bakery_lock.h @@ -11,7 +11,7 @@ #define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <cdefs.h> #include <stdbool.h> #include <stdint.h> @@ -101,5 +101,5 @@ void bakery_lock_release(bakery_lock_t *bakery); #define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* BAKERY_LOCK_H */ diff --git a/include/lib/cpus/aarch32/cortex_a9.h b/include/lib/cpus/aarch32/cortex_a9.h index 1fb0a923..a8c978a8 100644 --- a/include/lib/cpus/aarch32/cortex_a9.h +++ b/include/lib/cpus/aarch32/cortex_a9.h @@ -25,7 +25,7 @@ ******************************************************************************/ #define PCR p15, 0, c15, c0, 0 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <arch_helpers.h> DEFINE_COPROCR_RW_FUNCS(pcr, PCR) #endif diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h index 204bfdd4..e5ca1ba3 100644 --- a/include/lib/cpus/aarch64/cortex_a75.h +++ b/include/lib/cpus/aarch64/cortex_a75.h @@ -41,7 +41,7 @@ #define CORTEX_A75_AMU_GROUP0_MASK U(0x7) #define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> uint64_t cortex_a75_amu_cnt_read(int idx); @@ -50,6 +50,6 @@ unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CORTEX_A75_H */ diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_hercules.h index 86e8af03..b943e7a4 100644 --- a/include/lib/cpus/aarch64/cortex_hercules.h +++ b/include/lib/cpus/aarch64/cortex_hercules.h @@ -22,4 +22,20 @@ #define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30) + +/******************************************************************************* + * CPU Activity Monitor Unit register specific definitions. + ******************************************************************************/ +#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 +#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 +#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 +#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 + +#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF) +#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7) + #endif /* CORTEX_HERCULES_H */ diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h index 921abdbd..463f890f 100644 --- a/include/lib/cpus/aarch64/cpuamu.h +++ b/include/lib/cpus/aarch64/cpuamu.h @@ -29,7 +29,7 @@ #define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3 #define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> uint64_t cpuamu_cnt_read(unsigned int idx); @@ -43,6 +43,6 @@ int midr_match(unsigned int cpu_midr); void cpuamu_context_save(unsigned int nr_counters); void cpuamu_context_restore(unsigned int nr_counters); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CPUAMU_H */ diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index 81c076a1..02657a0f 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h @@ -34,11 +34,11 @@ #define DENVER_CPU_PMSTATE_C7 U(0x7) #define DENVER_CPU_PMSTATE_MASK U(0xF) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* Disable Dynamic Code Optimisation */ void denver_disable_dco(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* DENVER_H */ diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h index 17b2c30f..7cac77eb 100644 --- a/include/lib/cpus/errata_report.h +++ b/include/lib/cpus/errata_report.h @@ -7,7 +7,7 @@ #ifndef ERRATA_REPORT_H #define ERRATA_REPORT_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <arch.h> #include <arch_helpers.h> @@ -23,7 +23,7 @@ static inline void print_errata_status(void) {} void errata_print_msg(unsigned int status, const char *cpu, const char *id); int errata_needs_reporting(spinlock_t *lock, uint32_t *reported); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ /* Errata status */ #define ERRATA_NOT_APPLIES 0 diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h index 86ff53a6..c5567c97 100644 --- a/include/lib/el3_runtime/aarch32/context.h +++ b/include/lib/el3_runtime/aarch32/context.h @@ -24,7 +24,7 @@ #define CTX_NS_SCTLR U(0x1C) #define CTX_REGS_END U(0x20) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -65,6 +65,6 @@ typedef struct cpu_context { CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx), \ assert_core_context_regs_offset_mismatch); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CONTEXT_H */ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index 5bd0de42..a76a59b7 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -207,7 +207,7 @@ #define CTX_PAUTH_REGS_END U(0) #endif /* CTX_INCLUDE_PAUTH_REGS */ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -384,6 +384,6 @@ void fpregs_context_save(fp_regs_t *regs); void fpregs_context_restore(fp_regs_t *regs); #endif -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CONTEXT_H */ diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index f23f9cd4..7c996d12 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h @@ -35,7 +35,7 @@ void cm_init_context_by_index(unsigned int cpu_idx, void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep); void cm_prepare_el3_exit(uint32_t security_state); -#ifndef AARCH32 +#ifdef __aarch64__ void cm_el1_sysregs_context_save(uint32_t security_state); void cm_el1_sysregs_context_restore(uint32_t security_state); void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint); @@ -78,6 +78,6 @@ static inline void cm_set_next_context(void *context) #else void *cm_get_next_context(void); void cm_set_next_context(void *context); -#endif /* AARCH32 */ +#endif /* __aarch64__ */ #endif /* CONTEXT_MGMT_H */ diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h index 9e1d7f16..55db4cff 100644 --- a/include/lib/el3_runtime/cpu_data.h +++ b/include/lib/el3_runtime/cpu_data.h @@ -11,15 +11,7 @@ #include <bl31/ehf.h> -#ifdef AARCH32 - -#if CRASH_REPORTING -#error "Crash reporting is not supported in AArch32" -#endif -#define CPU_DATA_CPU_OPS_PTR 0x0 -#define CPU_DATA_CRASH_BUF_OFFSET 0x4 - -#else /* AARCH32 */ +#ifdef __aarch64__ /* Offsets for the cpu_data structure */ #define CPU_DATA_CRASH_BUF_OFFSET 0x18 @@ -27,7 +19,15 @@ #define CPU_DATA_CRASH_BUF_SIZE 64 #define CPU_DATA_CPU_OPS_PTR 0x10 -#endif /* AARCH32 */ +#else /* __aarch64__ */ + +#if CRASH_REPORTING +#error "Crash reporting is not supported in AArch32" +#endif +#define CPU_DATA_CPU_OPS_PTR 0x0 +#define CPU_DATA_CRASH_BUF_OFFSET 0x4 + +#endif /* __aarch64__ */ #if CRASH_REPORTING #define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \ @@ -49,7 +49,7 @@ #define CPU_DATA_PMF_TS0_IDX 0 #endif -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <arch_helpers.h> #include <lib/cassert.h> @@ -84,7 +84,7 @@ * used for this. ******************************************************************************/ typedef struct cpu_data { -#ifndef AARCH32 +#ifdef __aarch64__ void *cpu_context[2]; #endif uintptr_t cpu_ops_ptr; @@ -127,7 +127,7 @@ CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof struct cpu_data *_cpu_data_by_index(uint32_t cpu_index); -#ifndef AARCH32 +#ifdef __aarch64__ /* Return the cpu_data structure for the current CPU. */ static inline struct cpu_data *_cpu_data(void) { @@ -161,5 +161,5 @@ void init_cpu_ops(void); sizeof(((cpu_data_t *)0)->_m)) -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CPU_DATA_H */ diff --git a/include/lib/el3_runtime/pubsub_events.h b/include/lib/el3_runtime/pubsub_events.h index 8e4a87af..50120826 100644 --- a/include/lib/el3_runtime/pubsub_events.h +++ b/include/lib/el3_runtime/pubsub_events.h @@ -24,7 +24,7 @@ REGISTER_PUBSUB_EVENT(psci_cpu_on_finish); REGISTER_PUBSUB_EVENT(psci_suspend_pwrdown_start); REGISTER_PUBSUB_EVENT(psci_suspend_pwrdown_finish); -#ifdef AARCH64 +#ifdef __aarch64__ /* * These events are published by the AArch64 context management framework * after the secure context is restored/saved via @@ -40,4 +40,4 @@ REGISTER_PUBSUB_EVENT(cm_exited_secure_world); */ REGISTER_PUBSUB_EVENT(cm_entering_normal_world); REGISTER_PUBSUB_EVENT(cm_exited_normal_world); -#endif /* AARCH64 */ +#endif /* __aarch64__ */ diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h index 98daab60..4fc8f04b 100644 --- a/include/lib/extensions/ras.h +++ b/include/lib/extensions/ras.h @@ -68,7 +68,7 @@ .num_intrs = ARRAY_SIZE(_array), \ } -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <assert.h> @@ -196,6 +196,6 @@ int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, void *handle, uint64_t flags); void ras_init(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* RAS_H */ diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h index e9375a35..0c98c4a0 100644 --- a/include/lib/extensions/ras_arch.h +++ b/include/lib/extensions/ras_arch.h @@ -178,7 +178,7 @@ /* I/DFSC code for synchronous external abort */ #define SYNC_EA_FSC 0x10 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <arch.h> #include <arch_helpers.h> @@ -256,6 +256,6 @@ static inline void ser_sys_select_record(unsigned int idx) /* Library functions to probe Standard Error Record */ int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data); int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* RAS_ARCH_H */ diff --git a/include/lib/libc/aarch64/setjmp_.h b/include/lib/libc/aarch64/setjmp_.h index 174b3eb1..f880a17b 100644 --- a/include/lib/libc/aarch64/setjmp_.h +++ b/include/lib/libc/aarch64/setjmp_.h @@ -18,13 +18,13 @@ #define JMP_SIZE (JMP_CTX_END >> 3) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <cdefs.h> /* Jump buffer hosting x18 - x30 and sp_el0 registers */ typedef uint64_t jmp_buf[JMP_SIZE] __aligned(16); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* SETJMP__H */ diff --git a/include/lib/libc/setjmp.h b/include/lib/libc/setjmp.h index 5661201a..be8e2c01 100644 --- a/include/lib/libc/setjmp.h +++ b/include/lib/libc/setjmp.h @@ -9,12 +9,12 @@ #include <setjmp_.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <cdefs.h> int setjmp(jmp_buf env); __dead2 void longjmp(jmp_buf env, int val); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* SETJMP_H */ diff --git a/include/lib/libfdt/fdt.h b/include/lib/libfdt/fdt.h index 74961f90..ef7c86b6 100644 --- a/include/lib/libfdt/fdt.h +++ b/include/lib/libfdt/fdt.h @@ -52,7 +52,7 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ struct fdt_header { fdt32_t magic; /* magic word FDT_MAGIC */ @@ -90,7 +90,7 @@ struct fdt_property { char data[0]; }; -#endif /* !__ASSEMBLY */ +#endif /* !__ASSEMBLER__ */ #define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ #define FDT_TAGSIZE sizeof(fdt32_t) diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index fe279d4f..04e5e3d7 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h @@ -166,7 +166,7 @@ #define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT) #define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0)) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -348,6 +348,6 @@ int psci_features(unsigned int psci_fid); void __dead2 psci_power_down_wfi(void); void psci_arch_setup(void); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* PSCI_H */ diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h index 53d7711b..76c1a8dc 100644 --- a/include/lib/psci/psci_lib.h +++ b/include/lib/psci/psci_lib.h @@ -9,7 +9,7 @@ #include <common/ep_info.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <cdefs.h> #include <stdint.h> @@ -89,6 +89,6 @@ void psci_warmboot_entrypoint(void); void psci_register_spd_pm_hook(const spd_pm_ops_t *pm); void psci_prepare_next_non_secure_ctx( entry_point_info_t *next_image_info); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* PSCI_LIB_H */ diff --git a/include/lib/runtime_instr.h b/include/lib/runtime_instr.h index f5a3f138..303f27e5 100644 --- a/include/lib/runtime_instr.h +++ b/include/lib/runtime_instr.h @@ -17,9 +17,9 @@ #define RT_INSTR_EXIT_CFLUSH U(5) #define RT_INSTR_TOTAL_IDS U(6) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ PMF_DECLARE_CAPTURE_TIMESTAMP(rt_instr_svc) PMF_DECLARE_GET_TIMESTAMP(rt_instr_svc) -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* RUNTIME_INSTR_H */ diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 94c39d2a..76e60231 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -87,7 +87,7 @@ #define SMC_FROM_SECURE (U(0) << 0) #define SMC_FROM_NON_SECURE (U(1) << 0) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -155,5 +155,5 @@ static inline uint32_t smc_uuid_word(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t smc_uuid_word((_uuid).node[2], (_uuid).node[3], \ (_uuid).node[4], (_uuid).node[5])) -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* SMCCC_H */ diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h index fcd36e85..0bf3ee06 100644 --- a/include/lib/spinlock.h +++ b/include/lib/spinlock.h @@ -7,7 +7,7 @@ #ifndef SPINLOCK_H #define SPINLOCK_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> diff --git a/include/lib/utils.h b/include/lib/utils.h index 67484540..cdb125cf 100644 --- a/include/lib/utils.h +++ b/include/lib/utils.h @@ -11,7 +11,7 @@ * C code should be put in this part of the header to avoid breaking ASM files * or linker scripts including it. */ -#if !(defined(__LINKER__) || defined(__ASSEMBLY__)) +#if !(defined(__LINKER__) || defined(__ASSEMBLER__)) #include <stddef.h> #include <stdint.h> @@ -91,6 +91,6 @@ static inline u_register_t load_addr_## _name(void) \ /* Helper to invoke the function defined by DEFINE_LOAD_SYM_ADDR() */ #define LOAD_ADDR_OF(_name) (typeof(_name) *) load_addr_## _name() -#endif /* !(defined(__LINKER__) || defined(__ASSEMBLY__)) */ +#endif /* !(defined(__LINKER__) || defined(__ASSEMBLER__)) */ #endif /* UTILS_H */ diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 41f71e84..35ae33a6 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -21,10 +21,10 @@ #define BIT_32(nr) (U(1) << (nr)) #define BIT_64(nr) (ULL(1) << (nr)) -#ifdef AARCH32 -#define BIT BIT_32 -#else +#ifdef __aarch64__ #define BIT BIT_64 +#else +#define BIT BIT_32 #endif /* @@ -32,7 +32,7 @@ * position @h. For example * GENMASK_64(39, 21) gives us the 64bit vector 0x000000ffffe00000. */ -#if defined(__LINKER__) || defined(__ASSEMBLY__) +#if defined(__LINKER__) || defined(__ASSEMBLER__) #define GENMASK_32(h, l) \ (((0xFFFFFFFF) << (l)) & (0xFFFFFFFF >> (32 - 1 - (h)))) @@ -46,10 +46,10 @@ (((~UINT64_C(0)) << (l)) & (~UINT64_C(0) >> (64 - 1 - (h)))) #endif -#ifdef AARCH32 -#define GENMASK GENMASK_32 -#else +#ifdef __aarch64__ #define GENMASK GENMASK_64 +#else +#define GENMASK GENMASK_32 #endif /* @@ -109,10 +109,10 @@ ((_u32) > (UINT32_MAX - (_inc))) /* Register size of the current architecture. */ -#ifdef AARCH32 -#define REGSZ U(4) -#else +#ifdef __aarch64__ #define REGSZ U(8) +#else +#define REGSZ U(4) #endif /* diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h index 85effcaa..abdf1b6d 100644 --- a/include/lib/xlat_tables/xlat_mmu_helpers.h +++ b/include/lib/xlat_tables/xlat_mmu_helpers.h @@ -50,7 +50,7 @@ #define MMU_CFG_TTBR0 2 #define MMU_CFG_PARAM_MAX 3 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdbool.h> #include <stdint.h> @@ -65,14 +65,7 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags, const uint64_t *base_table, unsigned long long max_pa, uintptr_t max_va, int xlat_regime); -#ifdef AARCH32 -/* AArch32 specific translation table API */ -void enable_mmu_svc_mon(unsigned int flags); -void enable_mmu_hyp(unsigned int flags); - -void enable_mmu_direct_svc_mon(unsigned int flags); -void enable_mmu_direct_hyp(unsigned int flags); -#else +#ifdef __aarch64__ /* AArch64 specific translation table APIs */ void enable_mmu_el1(unsigned int flags); void enable_mmu_el2(unsigned int flags); @@ -81,11 +74,18 @@ void enable_mmu_el3(unsigned int flags); void enable_mmu_direct_el1(unsigned int flags); void enable_mmu_direct_el2(unsigned int flags); void enable_mmu_direct_el3(unsigned int flags); -#endif /* AARCH32 */ +#else +/* AArch32 specific translation table API */ +void enable_mmu_svc_mon(unsigned int flags); +void enable_mmu_hyp(unsigned int flags); + +void enable_mmu_direct_svc_mon(unsigned int flags); +void enable_mmu_direct_hyp(unsigned int flags); +#endif /* __aarch64__ */ bool xlat_arch_is_granule_size_supported(size_t size); size_t xlat_arch_get_max_supported_granule_size(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* XLAT_MMU_HELPERS_H */ diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h index 9e2543fb..082bb5e4 100644 --- a/include/lib/xlat_tables/xlat_tables.h +++ b/include/lib/xlat_tables/xlat_tables.h @@ -9,7 +9,7 @@ #include <lib/xlat_tables/xlat_tables_defs.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> @@ -88,5 +88,5 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, size_t size, unsigned int attr); void mmap_add(const mmap_region_t *mm); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* XLAT_TABLES_H */ diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h index 72375340..0ce0cacb 100644 --- a/include/lib/xlat_tables/xlat_tables_arch.h +++ b/include/lib/xlat_tables/xlat_tables_arch.h @@ -7,10 +7,10 @@ #ifndef XLAT_TABLES_ARCH_H #define XLAT_TABLES_ARCH_H -#ifdef AARCH32 -#include "aarch32/xlat_tables_aarch32.h" -#else +#ifdef __aarch64__ #include "aarch64/xlat_tables_aarch64.h" +#else +#include "aarch32/xlat_tables_aarch32.h" #endif /* diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index 000811f3..76cfc0b3 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -62,7 +62,7 @@ #define OSH (U(0x2) << 6) #define ISH (U(0x3) << 6) -#ifdef AARCH64 +#ifdef __aarch64__ /* Guarded Page bit */ #define GP (ULL(1) << 50) #endif diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index 55514268..0e099987 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -10,7 +10,7 @@ #include <lib/xlat_tables/xlat_tables_defs.h> #include <lib/xlat_tables/xlat_tables_v2_helpers.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> @@ -364,5 +364,5 @@ int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, uint32_t *attr); int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* XLAT_TABLES_V2_H */ diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h index 6a1be325..b17b71a8 100644 --- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h +++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h @@ -16,7 +16,7 @@ #error "Do not include this header file directly. Include xlat_tables_v2.h instead." #endif -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdbool.h> #include <stddef.h> @@ -160,6 +160,6 @@ struct xlat_ctx { .initialized = false, \ } -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* XLAT_TABLES_V2_HELPERS_H */ diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h index f982b57b..4637b678 100644 --- a/include/plat/arm/board/common/board_css_def.h +++ b/include/plat/arm/board/common/board_css_def.h @@ -29,7 +29,7 @@ #define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 #define BOARD_CSS_PLAT_TYPE_FVP 0x03 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <lib/mmio.h> @@ -37,7 +37,7 @@ ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #define MAX_IO_DEVICES 3 diff --git a/include/plat/arm/common/aarch64/arm_macros.S b/include/plat/arm/common/aarch64/arm_macros.S index 0bd0daf5..d47e4e09 100644 --- a/include/plat/arm/common/aarch64/arm_macros.S +++ b/include/plat/arm/common/aarch64/arm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,11 +22,13 @@ icc_regs: /* Registers common to both GICv2 and GICv3 */ gicd_pend_reg: - .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" + .asciz "gicd_ispendr regs (Offsets 0x200-0x278)\nOffset\t\t\tValue\n" newline: .asciz "\n" spacer: - .asciz ":\t\t0x" + .asciz ":\t\t 0x" +prefix: + .asciz "0x" /* --------------------------------------------- * The below utility macro prints out relevant GIC @@ -77,7 +79,15 @@ gicd_ispendr_loop: sub x4, x7, x16 cmp x4, #0x280 b.eq exit_print_gic_regs - bl asm_print_hex + + /* Print "0x" */ + adr x4, prefix + bl asm_print_str + + /* Print offset */ + sub x4, x7, x16 + mov x5, #12 + bl asm_print_hex_bits adr x4, spacer bl asm_print_str diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index ead1a8b3..53bd13fc 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -434,7 +434,7 @@ #endif #endif -#if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME +#if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME /******************************************************************************* * BL32 specific defines for EL3 runtime in AArch32 mode ******************************************************************************/ @@ -498,17 +498,17 @@ # else # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" # endif -#endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */ +#endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ /* * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no * SPD and no SPM, as they are the only ones that can be used as BL32. */ -#if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) +#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME # if defined(SPD_none) && !ENABLE_SPM # undef BL32_BASE # endif /* defined(SPD_none) && !ENABLE_SPM */ -#endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */ +#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ /******************************************************************************* * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index c8260e88..07a46c51 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -69,7 +69,7 @@ typedef struct arm_tzc_regions_info { void arm_setup_romlib(void); -#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) +#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) /* * Use this macro to instantiate lock before it is used in below * arm_lock_xxx() macros @@ -102,7 +102,7 @@ void arm_setup_romlib(void); #define arm_lock_get() #define arm_lock_release() -#endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */ +#endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ #if ARM_RECOM_STATE_ID_ENC /* diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index ec28db07..2adf11d6 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -136,7 +136,7 @@ #define SPIDEN_INT_CLR_SHIFT 6 #define SPIDEN_SEL_SET_SHIFT 7 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* SSC_VERSION related accessors */ @@ -150,7 +150,7 @@ (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ SSC_VERSION_CONFIG_MASK) -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ /************************************************************************* * Required platform porting definitions common to all diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h index 66c88ba8..14ae603b 100644 --- a/include/plat/common/common_def.h +++ b/include/plat/common/common_def.h @@ -20,13 +20,13 @@ /* * Platform binary types for linking */ -#ifdef AARCH32 -#define PLATFORM_LINKER_FORMAT "elf32-littlearm" -#define PLATFORM_LINKER_ARCH arm -#else +#ifdef __aarch64__ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 -#endif /* AARCH32 */ +#else +#define PLATFORM_LINKER_FORMAT "elf32-littlearm" +#define PLATFORM_LINKER_ARCH arm +#endif /* __aarch64__ */ /* * Generic platform constants diff --git a/include/services/spm_svc.h b/include/services/spm_svc.h index 57912e88..a3723a0f 100644 --- a/include/services/spm_svc.h +++ b/include/services/spm_svc.h @@ -63,7 +63,7 @@ #endif /* SPM_MM */ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -85,6 +85,6 @@ uint64_t spm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3); #endif /* SPM_MM */ -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* SPM_SVC_H */ diff --git a/lib/aarch32/arm32_aeabi_divmod.c b/lib/aarch32/arm32_aeabi_divmod.c index 0b36cb6c..ea8e2bbc 100644 --- a/lib/aarch32/arm32_aeabi_divmod.c +++ b/lib/aarch32/arm32_aeabi_divmod.c @@ -33,13 +33,11 @@ static void uint_div_qr(unsigned int numerator, unsigned int denominator, unsigned int __aeabi_uidivmod(unsigned int numerator, unsigned int denominator); unsigned int __aeabi_uidiv(unsigned int numerator, unsigned int denominator); -unsigned int __aeabi_uimod(unsigned int numerator, unsigned int denominator); /* returns in R0 and R1 by tail calling an asm function */ signed int __aeabi_idivmod(signed int numerator, signed int denominator); signed int __aeabi_idiv(signed int numerator, signed int denominator); -signed int __aeabi_imod(signed int numerator, signed int denominator); /* * __ste_idivmod_ret_t __aeabi_idivmod(signed numerator, signed denominator) @@ -106,15 +104,6 @@ unsigned int __aeabi_uidiv(unsigned int numerator, unsigned int denominator) return qr.q; } -unsigned int __aeabi_uimod(unsigned int numerator, unsigned int denominator) -{ - struct qr qr = { .q_n = 0, .r_n = 0 }; - - uint_div_qr(numerator, denominator, &qr); - - return qr.r; -} - unsigned int __aeabi_uidivmod(unsigned int numerator, unsigned int denominator) { struct qr qr = { .q_n = 0, .r_n = 0 }; @@ -145,42 +134,6 @@ signed int __aeabi_idiv(signed int numerator, signed int denominator) return qr.q; } -signed int __aeabi_imod(signed int numerator, signed int denominator) -{ - signed int s; - signed int i; - signed int j; - signed int h; - struct qr qr = { .q_n = 0, .r_n = 0 }; - - /* in case modulo of a power of 2 */ - for (i = 0, j = 0, h = 0, s = denominator; (s != 0) || (h > 1); i++) { - if (s & 1) { - j = i; - h++; - } - s = s >> 1; - } - if (h == 1) - return numerator >> j; - - if (((numerator < 0) && (denominator > 0)) || - ((numerator > 0) && (denominator < 0))) - qr.q_n = 1; /* quotient shall be negate */ - - if (numerator < 0) { - numerator = -numerator; - qr.r_n = 1; /* remainder shall be negate */ - } - - if (denominator < 0) - denominator = -denominator; - - uint_div_qr(numerator, denominator, &qr); - - return qr.r; -} - signed int __aeabi_idivmod(signed int numerator, signed int denominator) { struct qr qr = { .q_n = 0, .r_n = 0 }; diff --git a/lib/cpus/aarch64/cortex_hercules.S b/lib/cpus/aarch64/cortex_hercules.S index 25287de8..4e048145 100644 --- a/lib/cpus/aarch64/cortex_hercules.S +++ b/lib/cpus/aarch64/cortex_hercules.S @@ -16,6 +16,35 @@ #error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled" #endif + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-Hercules + * ------------------------------------------------- + */ +#if ENABLE_AMU +func cortex_hercules_reset_func + /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ + mrs x0, actlr_el3 + bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT + msr actlr_el3, x0 + + /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ + mrs x0, actlr_el2 + bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT + msr actlr_el2, x0 + + /* Enable group0 counters */ + mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK + msr CPUAMCNTENSET0_EL0, x0 + + /* Enable group1 counters */ + mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK + msr CPUAMCNTENSET1_EL0, x0 + isb + + ret +endfunc cortex_hercules_reset_func +#endif + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -60,6 +89,12 @@ func cortex_hercules_cpu_reg_dump ret endfunc cortex_hercules_cpu_reg_dump +#if ENABLE_AMU +#define HERCULES_RESET_FUNC cortex_hercules_reset_func +#else +#define HERCULES_RESET_FUNC CPU_NO_RESET_FUNC +#endif + declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \ - CPU_NO_RESET_FUNC, \ + HERCULES_RESET_FUNC, \ cortex_hercules_core_pwr_dwn diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c index aeb35600..f43b2176 100644 --- a/lib/cpus/errata_report.c +++ b/lib/cpus/errata_report.c @@ -18,9 +18,9 @@ #ifdef IMAGE_BL1 # define BL_STRING "BL1" -#elif defined(AARCH64) && defined(IMAGE_BL31) +#elif defined(__aarch64__) && defined(IMAGE_BL31) # define BL_STRING "BL31" -#elif defined(AARCH32) && defined(IMAGE_BL32) +#elif !defined(__arch64__) && defined(IMAGE_BL32) # define BL_STRING "BL32" #elif defined(IMAGE_BL2) && BL2_AT_EL3 # define BL_STRING "BL2" diff --git a/lib/extensions/ras/ras_common.c b/lib/extensions/ras/ras_common.c index be8becee..64a48524 100644 --- a/lib/extensions/ras/ras_common.c +++ b/lib/extensions/ras/ras_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -83,7 +83,8 @@ static int ras_interrupt_handler(uint32_t intr_raw, uint32_t flags, { struct ras_interrupt *ras_inrs = ras_interrupt_mappings.intrs; struct ras_interrupt *selected = NULL; - int start, end, mid, probe_data, ret __unused; + int probe_data = 0; + int start, end, mid, ret __unused; const struct err_handler_data err_data = { .version = ERR_HANDLER_VERSION, diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c index cc13fc1b..f906f51e 100644 --- a/lib/locks/bakery/bakery_lock_normal.c +++ b/lib/locks/bakery/bakery_lock_normal.c @@ -167,10 +167,10 @@ void bakery_lock_get(bakery_lock_t *lock) unsigned int their_bakery_data; me = plat_my_core_pos(); -#ifdef AARCH32 - is_cached = read_sctlr() & SCTLR_C_BIT; -#else +#ifdef __aarch64__ is_cached = read_sctlr_el3() & SCTLR_C_BIT; +#else + is_cached = read_sctlr() & SCTLR_C_BIT; #endif /* Get a ticket */ @@ -228,10 +228,10 @@ void bakery_lock_get(bakery_lock_t *lock) void bakery_lock_release(bakery_lock_t *lock) { bakery_info_t *my_bakery_info; -#ifdef AARCH32 - unsigned int is_cached = read_sctlr() & SCTLR_C_BIT; -#else +#ifdef __aarch64__ unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT; +#else + unsigned int is_cached = read_sctlr() & SCTLR_C_BIT; #endif my_bakery_info = get_bakery_info(plat_my_core_pos(), lock); diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c index f7392fda..2a407939 100644 --- a/lib/optee/optee_utils.c +++ b/lib/optee/optee_utils.c @@ -176,7 +176,7 @@ int parse_optee_header(entry_point_info_t *header_ep, */ if (!tee_validate_header(header)) { INFO("Invalid OPTEE header, set legacy mode.\n"); -#ifdef AARCH64 +#ifdef __aarch64__ header_ep->args.arg0 = MODE_RW_64; #else header_ep->args.arg0 = MODE_RW_32; @@ -222,7 +222,7 @@ int parse_optee_header(entry_point_info_t *header_ep, if (header->arch == 0) { header_ep->args.arg0 = MODE_RW_32; } else { -#ifdef AARCH64 +#ifdef __aarch64__ header_ep->args.arg0 = MODE_RW_64; #else ERROR("Cannot boot an AArch64 OP-TEE\n"); diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 3f5e9893..5d24356c 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -619,53 +619,7 @@ int psci_validate_mpidr(u_register_t mpidr) * This function determines the full entrypoint information for the requested * PSCI entrypoint on power on/resume and returns it. ******************************************************************************/ -#ifdef AARCH32 -static int psci_get_ns_ep_info(entry_point_info_t *ep, - uintptr_t entrypoint, - u_register_t context_id) -{ - u_register_t ep_attr; - unsigned int aif, ee, mode; - u_register_t scr = read_scr(); - u_register_t ns_sctlr, sctlr; - - /* Switch to non secure state */ - write_scr(scr | SCR_NS_BIT); - isb(); - ns_sctlr = read_sctlr(); - - sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr; - - /* Return to original state */ - write_scr(scr); - isb(); - ee = 0; - - ep_attr = NON_SECURE | EP_ST_DISABLE; - if (sctlr & SCTLR_EE_BIT) { - ep_attr |= EP_EE_BIG; - ee = 1; - } - SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); - - ep->pc = entrypoint; - zeromem(&ep->args, sizeof(ep->args)); - ep->args.arg0 = context_id; - - mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; - - /* - * TODO: Choose async. exception bits if HYP mode is not - * implemented according to the values of SCR.{AW, FW} bits - */ - aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT; - - ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif); - - return PSCI_E_SUCCESS; -} - -#else +#ifdef __aarch64__ static int psci_get_ns_ep_info(entry_point_info_t *ep, uintptr_t entrypoint, u_register_t context_id) @@ -722,7 +676,53 @@ static int psci_get_ns_ep_info(entry_point_info_t *ep, return PSCI_E_SUCCESS; } -#endif +#else /* !__aarch64__ */ +static int psci_get_ns_ep_info(entry_point_info_t *ep, + uintptr_t entrypoint, + u_register_t context_id) +{ + u_register_t ep_attr; + unsigned int aif, ee, mode; + u_register_t scr = read_scr(); + u_register_t ns_sctlr, sctlr; + + /* Switch to non secure state */ + write_scr(scr | SCR_NS_BIT); + isb(); + ns_sctlr = read_sctlr(); + + sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr; + + /* Return to original state */ + write_scr(scr); + isb(); + ee = 0; + + ep_attr = NON_SECURE | EP_ST_DISABLE; + if (sctlr & SCTLR_EE_BIT) { + ep_attr |= EP_EE_BIG; + ee = 1; + } + SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); + + ep->pc = entrypoint; + zeromem(&ep->args, sizeof(ep->args)); + ep->args.arg0 = context_id; + + mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; + + /* + * TODO: Choose async. exception bits if HYP mode is not + * implemented according to the values of SCR.{AW, FW} bits + */ + aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT; + + ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif); + + return PSCI_E_SUCCESS; +} + +#endif /* __aarch64__ */ /******************************************************************************* * This function validates the entrypoint with the platform layer if the diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile index 60c14580..cec94043 100644 --- a/lib/romlib/Makefile +++ b/lib/romlib/Makefile @@ -15,7 +15,7 @@ LIB_DIR = ../../$(BUILD_PLAT)/lib WRAPPER_DIR = ../../$(BUILD_PLAT)/libwrapper LIBS = -lmbedtls -lfdt -lc INC = $(INCLUDES:-I%=-I../../%) -PPFLAGS = $(INC) $(DEFINES) -P -D__ASSEMBLY__ -D__LINKER__ -MD -MP -MT $(BUILD_DIR)/romlib.ld +PPFLAGS = $(INC) $(DEFINES) -P -x assembler-with-cpp -D__LINKER__ -MD -MP -MT $(BUILD_DIR)/romlib.ld OBJS = $(BUILD_DIR)/jmptbl.o $(BUILD_DIR)/init.o MAPFILE = ../../$(BUILD_PLAT)/romlib/romlib.map diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c index e31f9d84..bd6b152e 100644 --- a/lib/xlat_tables/aarch32/nonlpae_tables.c +++ b/lib/xlat_tables/aarch32/nonlpae_tables.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2017, Linaro Limited. All rights reserved. - * Copyright (c) 2014-2017, Arm Limited. All rights reserved. + * Copyright (c) 2014-2019, Arm Limited. All rights reserved. * Copyright (c) 2014, STMicroelectronics International N.V. * All rights reserved. * @@ -445,7 +445,8 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, } else { xlat_table = (unsigned long)mmu_l2_base + next_xlat * MMU32B_L2_TABLE_SIZE; - assert(++next_xlat <= MAX_XLAT_TABLES); + next_xlat++; + assert(next_xlat <= MAX_XLAT_TABLES); memset((char *)xlat_table, 0, MMU32B_L2_TABLE_SIZE); diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c index bf3ae1e7..f4b64b33 100644 --- a/lib/xlat_tables_v2/xlat_tables_context.c +++ b/lib/xlat_tables_v2/xlat_tables_context.c @@ -136,48 +136,48 @@ int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr) #define MAX_PHYS_ADDR tf_xlat_ctx.max_pa #endif -#ifdef AARCH32 +#ifdef __aarch64__ -void enable_mmu_svc_mon(unsigned int flags) +void enable_mmu_el1(unsigned int flags) { setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); - enable_mmu_direct_svc_mon(flags); + enable_mmu_direct_el1(flags); } -void enable_mmu_hyp(unsigned int flags) +void enable_mmu_el2(unsigned int flags) { setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, tf_xlat_ctx.va_max_address, EL2_REGIME); - enable_mmu_direct_hyp(flags); + enable_mmu_direct_el2(flags); } -#else - -void enable_mmu_el1(unsigned int flags) +void enable_mmu_el3(unsigned int flags) { setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, - tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); - enable_mmu_direct_el1(flags); + tf_xlat_ctx.va_max_address, EL3_REGIME); + enable_mmu_direct_el3(flags); } -void enable_mmu_el2(unsigned int flags) +#else /* !__aarch64__ */ + +void enable_mmu_svc_mon(unsigned int flags) { setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, - tf_xlat_ctx.va_max_address, EL2_REGIME); - enable_mmu_direct_el2(flags); + tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); + enable_mmu_direct_svc_mon(flags); } -void enable_mmu_el3(unsigned int flags) +void enable_mmu_hyp(unsigned int flags) { setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, - tf_xlat_ctx.va_max_address, EL3_REGIME); - enable_mmu_direct_el3(flags); + tf_xlat_ctx.va_max_address, EL2_REGIME); + enable_mmu_direct_hyp(flags); } -#endif /* AARCH32 */ +#endif /* __aarch64__ */ diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c index 761d00c3..232142e8 100644 --- a/lib/xlat_tables_v2/xlat_tables_utils.c +++ b/lib/xlat_tables_v2/xlat_tables_utils.c @@ -97,7 +97,7 @@ static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc) printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S"); -#ifdef AARCH64 +#ifdef __aarch64__ /* Check Guarded Page bit */ if ((desc & GP) != 0ULL) { printf("-GP"); diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 2d41b2db..b89d87ea 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -273,7 +273,7 @@ $(eval IMAGE := IMAGE_BL$(call uppercase,$(3))) $(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs $$(ECHO) " PP $$<" - $$(Q)$$(CPP) $$(CPPFLAGS) -P -D__ASSEMBLY__ -D__LINKER__ $(MAKE_DEP) -D$(IMAGE) -o $$@ $$< + $$(Q)$$(CPP) $$(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) -P -x assembler-with-cpp -D__LINKER__ $(MAKE_DEP) -D$(IMAGE) -o $$@ $$< -include $(DEP) diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index b885b47a..36cd5009 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -81,7 +81,7 @@ const mmap_region_t plat_arm_mmap[] = { MAP_DEVICE0, MAP_DEVICE1, ARM_MAP_NS_DRAM1, -#ifdef AARCH64 +#ifdef __aarch64__ ARM_MAP_DRAM2, #endif #ifdef SPD_tspd @@ -150,7 +150,7 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = { #endif #ifdef IMAGE_BL32 const mmap_region_t plat_arm_mmap[] = { -#ifdef AARCH32 +#ifndef __aarch64__ ARM_MAP_SHARED_RAM, ARM_V2M_MAP_MEM_PROTECT, #endif diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 207cd31d..4f262770 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -120,7 +120,7 @@ #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) #endif -#ifdef AARCH32 +#ifndef __aarch64__ /* * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is * calculated using the current SP_MIN PROGBITS debug size plus the sizes of @@ -259,7 +259,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifdef AARCH64 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h index b3b36726..4e575e1a 100644 --- a/plat/arm/board/fvp_ve/include/platform_def.h +++ b/plat/arm/board/fvp_ve/include/platform_def.h @@ -331,7 +331,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifdef AARCH64 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index d693c26a..83aeeb4b 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -291,7 +291,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifdef AARCH64 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c index 118c19ab..98c5d3c9 100644 --- a/plat/arm/board/juno/juno_common.c +++ b/plat/arm/board/juno/juno_common.c @@ -37,7 +37,7 @@ const mmap_region_t plat_arm_mmap[] = { CSS_MAP_DEVICE, SOC_CSS_MAP_DEVICE, ARM_MAP_NS_DRAM1, -#ifdef AARCH64 +#ifdef __aarch64__ ARM_MAP_DRAM2, #endif #ifdef SPD_tspd @@ -74,7 +74,7 @@ const mmap_region_t plat_arm_mmap[] = { #endif #ifdef IMAGE_BL32 const mmap_region_t plat_arm_mmap[] = { -#ifdef AARCH32 +#ifndef __aarch64__ ARM_MAP_SHARED_RAM, #ifdef PLAT_ARM_MEM_PROT_ADDR ARM_V2M_MAP_MEM_PROTECT, diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index ff583a90..7348bf5e 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -34,7 +34,7 @@ * space the physical & virtual address space limits are extended to * 40-bits. */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) #else diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h index c62cda85..50b04f04 100644 --- a/plat/arm/board/rde1edge/include/platform_def.h +++ b/plat/arm/board/rde1edge/include/platform_def.h @@ -29,7 +29,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index 2c7b8bda..580ab8e6 100644 --- a/plat/arm/board/rdn1edge/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -30,7 +30,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h index 883403bb..f00146f9 100644 --- a/plat/arm/board/sgi575/include/platform_def.h +++ b/plat/arm/board/sgi575/include/platform_def.h @@ -30,7 +30,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/sgm775/include/platform_def.h b/plat/arm/board/sgm775/include/platform_def.h index 3e1fdd12..27d1b330 100644 --- a/plat/arm/board/sgm775/include/platform_def.h +++ b/plat/arm/board/sgm775/include/platform_def.h @@ -15,7 +15,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index 8905bb05..b19a7c39 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -121,11 +121,11 @@ void arm_bl1_plat_arch_setup(void) }; setup_page_tables(bl_regions, plat_arm_get_mmap()); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el3(0); -#endif /* AARCH32 */ +#else + enable_mmu_svc_mon(0); +#endif /* __aarch64__ */ arm_setup_romlib(); } diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c index 0c01c872..97b5a888 100644 --- a/plat/arm/common/arm_bl2_el3_setup.c +++ b/plat/arm/common/arm_bl2_el3_setup.c @@ -83,10 +83,10 @@ void arm_bl2_el3_plat_arch_setup(void) setup_page_tables(bl_regions, plat_arm_get_mmap()); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el3(0); +#else + enable_mmu_svc_mon(0); #endif } diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 32617f68..cdf87ca5 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -128,10 +128,10 @@ void arm_bl2_plat_arch_setup(void) setup_page_tables(bl_regions, plat_arm_get_mmap()); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el1(0); +#else + enable_mmu_svc_mon(0); #endif arm_setup_romlib(); @@ -153,7 +153,7 @@ int arm_bl2_handle_post_image_load(unsigned int image_id) assert(bl_mem_params); switch (image_id) { -#ifdef AARCH64 +#ifdef __aarch64__ case BL32_IMAGE_ID: #ifdef SPD_opteed pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c index 9f44b9e6..3614c7d2 100644 --- a/plat/arm/common/arm_bl2u_setup.c +++ b/plat/arm/common/arm_bl2u_setup.c @@ -83,10 +83,10 @@ void arm_bl2u_plat_arch_setup(void) setup_page_tables(bl_regions, plat_arm_get_mmap()); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el1(0); +#else + enable_mmu_svc_mon(0); #endif arm_setup_romlib(); } diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index f5ce4d24..bc0cf9a8 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -59,7 +59,7 @@ uint32_t arm_get_spsr_for_bl32_entry(void) /******************************************************************************* * Gets SPSR for BL33 entry ******************************************************************************/ -#ifndef AARCH32 +#ifdef __aarch64__ uint32_t arm_get_spsr_for_bl33_entry(void) { unsigned int mode; @@ -97,7 +97,7 @@ uint32_t arm_get_spsr_for_bl33_entry(void) SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); return spsr; } -#endif /* AARCH32 */ +#endif /* __aarch64__ */ /******************************************************************************* * Configures access to the system counter timer module. diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index 93bebf34..7f4957fa 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -83,8 +83,8 @@ void __init plat_arm_gic_driver_init(void) * can use GIC system registers to manage interrupts and does * not need GIC interface base addresses to be configured. */ -#if (defined(AARCH32) && defined(IMAGE_BL32)) || \ - (defined(IMAGE_BL31) && !defined(AARCH32)) +#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ + (defined(__aarch64__) && defined(IMAGE_BL31)) gicv3_driver_init(&arm_gic_data); #endif } diff --git a/plat/arm/common/arm_nor_psci_mem_protect.c b/plat/arm/common/arm_nor_psci_mem_protect.c index 3a700598..b9181eb4 100644 --- a/plat/arm/common/arm_nor_psci_mem_protect.c +++ b/plat/arm/common/arm_nor_psci_mem_protect.c @@ -26,7 +26,7 @@ static mem_region_t arm_ram_ranges[] = { {DRAM1_NS_IMAGE_LIMIT, DRAM1_PROTECTED_SIZE}, -#ifdef AARCH64 +#ifdef __aarch64__ {ARM_DRAM2_BASE, 1u << ONE_GB_SHIFT}, #endif }; diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index cb87bafd..c95f4523 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -116,7 +116,7 @@ int arm_validate_ns_entrypoint(uintptr_t entrypoint) (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { return 0; } -#ifndef AARCH32 +#ifdef __aarch64__ if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { return 0; diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/execution_state_switch.c index d4711302..00ac16ef 100644 --- a/plat/arm/common/execution_state_switch.c +++ b/plat/arm/common/execution_state_switch.c @@ -40,7 +40,7 @@ int arm_execution_state_switch(unsigned int smc_fid, void *handle) { /* Execution state can be switched only if EL3 is AArch64 */ -#ifdef AARCH64 +#ifdef __aarch64__ bool caller_64, thumb = false, from_el2; unsigned int el, endianness; u_register_t spsr, pc, scr, sctlr; @@ -173,7 +173,7 @@ invalid_param: SMC_RET1(handle, STATE_SW_E_PARAM); exec_denied: -#endif +#endif /* __aarch64__ */ /* State switch denied */ SMC_RET1(handle, STATE_SW_E_DENIED); } diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index 032a1f47..a9cc8527 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -187,7 +187,7 @@ /* Platform ID address */ #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* SSC_VERSION related accessors */ /* Returns the part number of the platform */ #define GET_SGI_PART_NUM \ @@ -195,7 +195,7 @@ /* Returns the configuration number of the platform */ #define GET_SGI_CONFIG_NUM \ GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ /******************************************************************************* * Memprotect definitions diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h index 4ecfc969..f349c196 100644 --- a/plat/arm/css/sgm/include/sgm_base_platform_def.h +++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h @@ -51,7 +51,7 @@ /* Platform ID address */ #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* SSC_VERSION related accessors */ /* Returns the part number of the platform */ #define GET_PLAT_PART_NUM \ @@ -59,7 +59,7 @@ /* Returns the configuration number of the platform */ #define GET_PLAT_CONFIG_NUM \ GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ /************************************************************************* diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c index f5ed6fc9..4a8a7eef 100644 --- a/plat/common/plat_gicv3.c +++ b/plat/common/plat_gicv3.c @@ -300,7 +300,7 @@ unsigned int plat_ic_get_interrupt_id(unsigned int raw) #pragma weak plat_ic_end_of_interrupt /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ -#ifdef AARCH32 +#ifndef __aarch64__ #define IS_IN_EL1() IS_IN_SECURE() #endif diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c index 1a29d9ca..16bec797 100644 --- a/plat/common/plat_psci_common.c +++ b/plat/common/plat_psci_common.c @@ -20,10 +20,10 @@ #define MHZ_TICKS_PER_SEC 1000000U /* Maximum time-stamp value read from architectural counters */ -#ifdef AARCH32 -#define MAX_TS UINT32_MAX -#else +#ifdef __aarch64__ #define MAX_TS UINT64_MAX +#else +#define MAX_TS UINT32_MAX #endif /* Following are used as ID's to capture time-stamp */ diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index c57fea90..2f96efcd 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -77,7 +77,7 @@ uint32_t hikey_get_spsr_for_bl32_entry(void) /******************************************************************************* * Gets SPSR for BL33 entry ******************************************************************************/ -#ifndef AARCH32 +#ifdef __aarch64__ uint32_t hikey_get_spsr_for_bl33_entry(void) { unsigned int mode; @@ -112,7 +112,7 @@ uint32_t hikey_get_spsr_for_bl33_entry(void) SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); return spsr; } -#endif /* AARCH32 */ +#endif /* __aarch64__ */ int hikey_bl2_handle_post_image_load(unsigned int image_id) { @@ -125,7 +125,7 @@ int hikey_bl2_handle_post_image_load(unsigned int image_id) assert(bl_mem_params); switch (image_id) { -#ifdef AARCH64 +#ifdef __aarch64__ case BL32_IMAGE_ID: #ifdef SPD_opteed pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); diff --git a/plat/hisilicon/hikey/include/hikey_layout.h b/plat/hisilicon/hikey/include/hikey_layout.h index a87648ed..4b8dc535 100644 --- a/plat/hisilicon/hikey/include/hikey_layout.h +++ b/plat/hisilicon/hikey/include/hikey_layout.h @@ -113,7 +113,7 @@ #endif /* BL32 is mandatory in AArch32 */ -#ifndef AARCH32 +#ifdef __aarch64__ #ifdef SPD_none #undef BL32_BASE #endif /* SPD_none */ diff --git a/plat/hisilicon/hikey/include/hisi_pwrc.h b/plat/hisilicon/hikey/include/hisi_pwrc.h index f1cc297d..cbb46513 100644 --- a/plat/hisilicon/hikey/include/hisi_pwrc.h +++ b/plat/hisilicon/hikey/include/hisi_pwrc.h @@ -7,7 +7,7 @@ #ifndef HISI_PWRC_H #define HISI_PWRC_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ void hisi_pwrc_set_cluster_wfi(unsigned int id); void hisi_pwrc_set_core_bx_addr(unsigned int core, @@ -17,6 +17,6 @@ void hisi_pwrc_enable_debug(unsigned int core, unsigned int cluster); int hisi_pwrc_setup(void); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* HISI_PWRC_H */ diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c index 7102de85..fc9ddab0 100644 --- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c @@ -168,7 +168,7 @@ uint32_t hikey960_get_spsr_for_bl32_entry(void) /******************************************************************************* * Gets SPSR for BL33 entry ******************************************************************************/ -#ifndef AARCH32 +#ifdef __aarch64__ uint32_t hikey960_get_spsr_for_bl33_entry(void) { unsigned int mode; @@ -203,7 +203,7 @@ uint32_t hikey960_get_spsr_for_bl33_entry(void) SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); return spsr; } -#endif /* AARCH32 */ +#endif /* __aarch64__ */ int hikey960_bl2_handle_post_image_load(unsigned int image_id) { @@ -216,7 +216,7 @@ int hikey960_bl2_handle_post_image_load(unsigned int image_id) assert(bl_mem_params); switch (image_id) { -#ifdef AARCH64 +#ifdef __aarch64__ case BL32_IMAGE_ID: #ifdef SPD_opteed pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h index 7c3c1023..f6edad66 100644 --- a/plat/hisilicon/hikey960/include/platform_def.h +++ b/plat/hisilicon/hikey960/include/platform_def.h @@ -95,7 +95,7 @@ #endif /* BL32 is mandatory in AArch32 */ -#ifndef AARCH32 +#ifdef __aarch64__ #ifdef SPD_none #undef BL32_BASE #endif /* SPD_none */ diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c index 11403b07..cc9d9754 100644 --- a/plat/hisilicon/poplar/bl2_plat_setup.c +++ b/plat/hisilicon/poplar/bl2_plat_setup.c @@ -54,7 +54,7 @@ uint32_t poplar_get_spsr_for_bl32_entry(void) /******************************************************************************* * Gets SPSR for BL33 entry ******************************************************************************/ -#ifndef AARCH32 +#ifdef __aarch64__ uint32_t poplar_get_spsr_for_bl33_entry(void) { unsigned long el_status; @@ -93,7 +93,7 @@ uint32_t poplar_get_spsr_for_bl33_entry(void) SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); return spsr; } -#endif /* AARCH32 */ +#endif /* __aarch64__ */ int poplar_bl2_handle_post_image_load(unsigned int image_id) { @@ -107,7 +107,7 @@ int poplar_bl2_handle_post_image_load(unsigned int image_id) assert(bl_mem_params); switch (image_id) { -#ifdef AARCH64 +#ifdef __aarch64__ case BL32_IMAGE_ID: #ifdef SPD_opteed pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h index 8f7a1559..9783f8d2 100644 --- a/plat/hisilicon/poplar/include/platform_def.h +++ b/plat/hisilicon/poplar/include/platform_def.h @@ -107,7 +107,7 @@ #endif /* BL32 is mandatory in AArch32 */ -#ifndef AARCH32 +#ifdef __aarch64__ #ifdef SPD_none #undef BL32_BASE #endif /* SPD_none */ diff --git a/plat/imx/common/include/imx8_lpuart.h b/plat/imx/common/include/imx8_lpuart.h index 63449e7d..0ea284fd 100644 --- a/plat/imx/common/include/imx8_lpuart.h +++ b/plat/imx/common/include/imx8_lpuart.h @@ -50,7 +50,7 @@ #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_M10_MASK (0x20000000U) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -61,6 +61,6 @@ typedef struct { int console_lpuart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_lpuart_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* IMX8_LPUART_H */ diff --git a/plat/imx/common/include/imx_uart.h b/plat/imx/common/include/imx_uart.h index 1b52e2f0..cc1b5318 100644 --- a/plat/imx/common/include/imx_uart.h +++ b/plat/imx/common/include/imx_uart.h @@ -9,7 +9,7 @@ #include <drivers/console.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ typedef struct { console_t console; @@ -18,6 +18,6 @@ typedef struct { int console_imx_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_uart_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* IMX_UART_H */ diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index 385065f9..e9ab9285 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -69,9 +69,9 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, deassert_peripheral_reset(); config_hps_hs_before_warm_reset(); - watchdog_init(get_wdt_clk(&reverse_handoff_ptr)); + watchdog_init(get_wdt_clk()); - console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, + console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, &console); socfpga_delay_timer_init(); @@ -105,7 +105,7 @@ void bl2_el3_plat_arch_setup(void) enable_mmu_el3(0); - dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000); + dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); info.mmc_dev_type = MMC_IS_SD; info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index 03fba8aa..c8765e85 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -97,7 +97,7 @@ void bl31_platform_setup(void) const mmap_region_t plat_agilex_mmap[] = { MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, MT_NON_CACHEABLE | MT_RW | MT_SECURE), MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h index c1a7546c..73e6c4e1 100644 --- a/plat/intel/soc/agilex/include/agilex_clock_manager.h +++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h @@ -80,41 +80,38 @@ #define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16) #define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004 #define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008 +#define CLKMGR_INTOSC_HZ 460000000 /* Main PLL Macros */ #define CLKMGR_MAINPLL_EN_RESET 0x000000ff -#define CLKMGR_MAINPLL_PLLM_MDIV(x) ((x) & 0x000003ff) -#define CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK 0x00000001 -#define CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK 0x00000002 - -#define CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) -#define CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) -#define CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) - -#define CLKMGR_MAINPLL_PLLGLOB_PSRC(x) (((x) & 0x00030000) >> 16) -#define CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1 0x0 -#define CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC 0x1 -#define CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S 0x2 -#define CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) -#define CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) /* Peripheral PLL Macros */ #define CLKMGR_PERPLL_EN_RESET 0x00000fff -#define CLKMGR_PERPLL_PLLM_MDIV(x) ((x) & 0x000003ff) #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) -#define CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001 - -#define CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) -#define CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) -#define CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) - -#define CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002 -#define CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) -#define CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) /* Altera Macros */ #define CLKMGR_ALTERA_EXTCNTRST_RESET 0xff +/* Shared Macros */ +#define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) +#define CLKMGR_PSRC_MAIN 0 +#define CLKMGR_PSRC_PER 1 + +#define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0 +#define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1 +#define CLKMGR_PLLGLOB_PSRC_F2S 0x2 + +#define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff) +#define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001 +#define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002 + +#define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) +#define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) +#define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) + +#define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) +#define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) + typedef struct { uint32_t clk_freq_of_eosc1; @@ -123,6 +120,8 @@ typedef struct { } CLOCK_SOURCE_CONFIG; void config_clkmgr_handoff(handoff *hoff_ptr); -int get_wdt_clk(handoff *hoff_ptr); +uint32_t get_wdt_clk(void); +uint32_t get_uart_clk(void); +uint32_t get_mmc_clk(void); #endif diff --git a/plat/intel/soc/agilex/include/agilex_private.h b/plat/intel/soc/agilex/include/agilex_private.h index 5ccbc8c3..fc0e9fdd 100644 --- a/plat/intel/soc/agilex/include/agilex_private.h +++ b/plat/intel/soc/agilex/include/agilex_private.h @@ -11,14 +11,13 @@ #define AGX_MMC_REG_BASE 0xff808000 #define EMMC_DESC_SIZE (1<<20) -#define EMMC_INIT_PARAMS(base) \ +#define EMMC_INIT_PARAMS(base, clk) \ { .bus_width = MMC_BUS_WIDTH_4, \ - .clk_rate = 50000000, \ + .clk_rate = (clk), \ .desc_base = (base), \ .desc_size = EMMC_DESC_SIZE, \ .flags = 0, \ - .reg_base = AGX_MMC_REG_BASE, \ - \ + .reg_base = AGX_MMC_REG_BASE \ } typedef enum { @@ -26,7 +25,7 @@ typedef enum { BOOT_SOURCE_SDMMC, BOOT_SOURCE_NAND, BOOT_SOURCE_RSVD, - BOOT_SOURCE_QSPI, + BOOT_SOURCE_QSPI } boot_source_type; void enable_nonsecure_access(void); diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h index 6ec20842..381c2d35 100644 --- a/plat/intel/soc/agilex/include/agilex_system_manager.h +++ b/plat/intel/soc/agilex/include/agilex_system_manager.h @@ -65,6 +65,11 @@ #define AGX_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 #define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 +#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x)) +#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 +#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 +#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 + #define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) diff --git a/plat/intel/soc/agilex/include/platform_def.h b/plat/intel/soc/agilex/include/platform_def.h index 10f73386..277862a3 100644 --- a/plat/intel/soc/agilex/include/platform_def.h +++ b/plat/intel/soc/agilex/include/platform_def.h @@ -15,7 +15,7 @@ #define PLAT_CPUID_RELEASE 0xffe1b000 -#define PLAT_AGX_SEC_ENTRY 0xffe1b008 +#define PLAT_SEC_ENTRY 0xffe1b008 /* Define next boot image name and offset */ #define PLAT_NS_IMAGE_OFFSET 0x50000 diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 22ff1603..5d20462b 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -7,7 +7,8 @@ # PLAT_INCLUDES := \ -Iplat/intel/soc/agilex/include/ \ - -Iplat/intel/soc/common/drivers/ + -Iplat/intel/soc/common/drivers/ \ + -Iplat/intel/soc/common/include/ PLAT_BL_COMMON_SOURCES := \ drivers/arm/gic/common/gic_common.c \ @@ -19,8 +20,8 @@ PLAT_BL_COMMON_SOURCES := \ lib/xlat_tables/aarch64/xlat_tables.c \ lib/xlat_tables/xlat_tables_common.c \ plat/common/plat_gicv2.c \ - plat/intel/soc/agilex/aarch64/platform_common.c \ - plat/intel/soc/agilex/aarch64/plat_helpers.S \ + plat/intel/soc/common/aarch64/platform_common.c \ + plat/intel/soc/common/aarch64/plat_helpers.S BL2_SOURCES += \ common/desc_image_load.c \ @@ -37,14 +38,14 @@ BL2_SOURCES += \ lib/cpus/aarch64/cortex_a53.S \ plat/intel/soc/agilex/bl2_plat_setup.c \ plat/intel/soc/agilex/socfpga_storage.c \ - plat/intel/soc/agilex/bl2_plat_mem_params_desc.c \ + plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_handoff.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_memory_controller.c \ - plat/intel/soc/agilex/socfpga_delay_timer.c \ - plat/intel/soc/agilex/socfpga_image_load.c \ + plat/intel/soc/common/socfpga_delay_timer.c \ + plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/agilex/soc/agilex_system_manager.c \ plat/intel/soc/agilex/soc/agilex_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ @@ -59,8 +60,8 @@ BL31_SOURCES += \ plat/intel/soc/agilex/socfpga_sip_svc.c \ plat/intel/soc/agilex/bl31_plat_setup.c \ plat/intel/soc/agilex/socfpga_psci.c \ - plat/intel/soc/agilex/socfpga_topology.c \ - plat/intel/soc/agilex/socfpga_delay_timer.c \ + plat/intel/soc/common/socfpga_topology.c \ + plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c index 6e7b43e0..218676a9 100644 --- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c @@ -12,15 +12,8 @@ #include "agilex_clock_manager.h" #include "agilex_handoff.h" +#include "agilex_system_manager.h" -static const CLOCK_SOURCE_CONFIG clk_source = { - /* clk_freq_of_eosc1 */ - (uint32_t) 25000000, - /* clk_freq_of_f2h_free */ - (uint32_t) 400000000, - /* clk_freq_of_cb_intosc_ls */ - (uint32_t) 50000000, -}; uint32_t wait_pll_lock(void) { @@ -114,18 +107,18 @@ void config_clkmgr_handoff(handoff *hoff_ptr) /* Put both PLL in reset and power down */ mmio_clrbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB, - CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK | - CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK); + CLKMGR_PLLGLOB_PD_SET_MSK | + CLKMGR_PLLGLOB_RST_SET_MSK); mmio_clrbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB, - CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK | - CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK); + CLKMGR_PLLGLOB_PD_SET_MSK | + CLKMGR_PLLGLOB_RST_SET_MSK); /* Setup main PLL dividers */ - mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm); + mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->main_pll_pllm); - arefclk_div = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV( + arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV( hoff_ptr->main_pll_pllglob); - drefclk_div = CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV( + drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV( hoff_ptr->main_pll_pllglob); mscnt = 100 / (mdiv / BIT(drefclk_div)); @@ -134,8 +127,8 @@ void config_clkmgr_handoff(handoff *hoff_ptr) hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4; mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_VCOCALIB, - CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(hscnt) | - CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(mscnt)); + CLKMGR_VCOCALIB_HSCNT_SET(hscnt) | + CLKMGR_VCOCALIB_MSCNT_SET(mscnt)); mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV, hoff_ptr->main_pll_nocdiv); @@ -159,11 +152,11 @@ void config_clkmgr_handoff(handoff *hoff_ptr) hoff_ptr->main_pll_nocclk); /* Setup peripheral PLL dividers */ - mdiv = CLKMGR_PERPLL_PLLM_MDIV(hoff_ptr->per_pll_pllm); + mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->per_pll_pllm); - arefclk_div = CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV( + arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV( hoff_ptr->per_pll_pllglob); - drefclk_div = CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV( + drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV( hoff_ptr->per_pll_pllglob); mscnt = 100 / (mdiv / BIT(drefclk_div)); @@ -172,8 +165,8 @@ void config_clkmgr_handoff(handoff *hoff_ptr) hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4; mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_VCOCALIB, - CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(hscnt) | - CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(mscnt)); + CLKMGR_VCOCALIB_HSCNT_SET(hscnt) | + CLKMGR_VCOCALIB_MSCNT_SET(mscnt)); mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EMACCTL, hoff_ptr->per_pll_emacctl); @@ -197,11 +190,11 @@ void config_clkmgr_handoff(handoff *hoff_ptr) /* Take both PLL out of reset and power up */ mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB, - CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK | - CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK); + CLKMGR_PLLGLOB_PD_SET_MSK | + CLKMGR_PLLGLOB_RST_SET_MSK); mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB, - CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK | - CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK); + CLKMGR_PLLGLOB_PD_SET_MSK | + CLKMGR_PLLGLOB_RST_SET_MSK); wait_pll_lock(); @@ -256,24 +249,31 @@ void config_clkmgr_handoff(handoff *hoff_ptr) CLKMGR_MAINPLL_EN_RESET); mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN, CLKMGR_PERPLL_EN_RESET); + + /* Pass clock source frequency into scratch register */ + mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1), + hoff_ptr->hps_osc_clk_h); + mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2), + hoff_ptr->fpga_clk_hz); } -int get_wdt_clk(handoff *hoff_ptr) +/* Extract reference clock from platform clock source */ +uint32_t get_ref_clk(uint32_t pllglob) { - int main_noc_base_clk, l3_main_free_clk, l4_sys_free_clk; - int data32, mdiv, arefclkdiv, ref_clk; - - data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB); + uint32_t arefclkdiv, ref_clk; + uint32_t scr_reg; - switch (CLKMGR_MAINPLL_PLLGLOB_PSRC(data32)) { - case CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1: - ref_clk = clk_source.clk_freq_of_eosc1; + switch (CLKMGR_PSRC(pllglob)) { + case CLKMGR_PLLGLOB_PSRC_EOSC1: + scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1); + ref_clk = mmio_read_32(scr_reg); break; - case CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC: - ref_clk = clk_source.clk_freq_of_cb_intosc_ls; + case CLKMGR_PLLGLOB_PSRC_INTOSC: + ref_clk = CLKMGR_INTOSC_HZ; break; - case CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S: - ref_clk = clk_source.clk_freq_of_f2h_free; + case CLKMGR_PLLGLOB_PSRC_F2S: + scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2); + ref_clk = mmio_read_32(scr_reg); break; default: ref_clk = 0; @@ -281,13 +281,91 @@ int get_wdt_clk(handoff *hoff_ptr) break; } - arefclkdiv = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(data32); - mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm); + arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob); + ref_clk /= arefclkdiv; + + return ref_clk; +} + +/* Calculate clock frequency based on parameter */ +uint32_t get_clk_freq(uint32_t psrc_reg, uint32_t main_pllc, uint32_t per_pllc) +{ + uint32_t clk_psrc, mdiv, ref_clk; + uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg; + + clk_psrc = mmio_read_32(CLKMGR_MAINPLL + psrc_reg); + + switch (CLKMGR_PSRC(clk_psrc)) { + case CLKMGR_PSRC_MAIN: + pllm_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM; + pllc_reg = CLKMGR_MAINPLL + main_pllc; + pllglob_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB; + break; + case CLKMGR_PSRC_PER: + pllm_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM; + pllc_reg = CLKMGR_PERPLL + per_pllc; + pllglob_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB; + break; + default: + return 0; + } + + ref_clk = get_ref_clk(mmio_read_32(pllglob_reg)); + mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg)); + ref_clk *= mdiv; + + pllc_div = mmio_read_32(pllc_reg) & 0x7ff; + + return ref_clk / pllc_div; +} + +/* Return L3 interconnect clock */ +uint32_t get_l3_clk(void) +{ + uint32_t l3_clk; + + l3_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1, + CLKMGR_PERPLL_PLLC1); + return l3_clk; +} + +/* Calculate clock frequency to be used for watchdog timer */ +uint32_t get_wdt_clk(void) +{ + uint32_t l3_clk, l4_sys_clk; + + l3_clk = get_l3_clk(); + l4_sys_clk = l3_clk / 4; + + return l4_sys_clk; +} + +/* Calculate clock frequency to be used for UART driver */ +uint32_t get_uart_clk(void) +{ + uint32_t data32, l3_clk, l4_sp_clk; + + l3_clk = get_l3_clk(); + + data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV); + data32 = (data32 >> 16) & 0x3; + + l4_sp_clk = l3_clk >> data32; + + return l4_sp_clk; +} + +/* Calculate clock frequency to be used for SDMMC driver */ +uint32_t get_mmc_clk(void) +{ + uint32_t data32, mmc_clk; + + mmc_clk = get_clk_freq(CLKMGR_ALTERA_SDMMCCTR, + CLKMGR_MAINPLL_PLLC3, CLKMGR_PERPLL_PLLC3); - ref_clk = (ref_clk / arefclkdiv) * mdiv; - main_noc_base_clk = ref_clk / (hoff_ptr->main_pll_pllc1 & 0x7ff); - l3_main_free_clk = main_noc_base_clk / (hoff_ptr->main_pll_nocclk + 1); - l4_sys_free_clk = l3_main_free_clk / 4; + data32 = mmio_read_32(CLKMGR_ALTERA + CLKMGR_ALTERA_SDMMCCTR); + data32 = (data32 & 0x7ff) + 1; + mmc_clk = (mmc_clk / data32) / 4; - return l4_sys_free_clk; + return mmc_clk; } diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/agilex/socfpga_psci.c index 411e89bd..04d8a0e9 100644 --- a/plat/intel/soc/agilex/socfpga_psci.c +++ b/plat/intel/soc/agilex/socfpga_psci.c @@ -17,7 +17,7 @@ #define AGX_RSTMGR_OFST 0xffd11000 #define AGX_RSTMGR_MPUMODRST_OFST 0x20 -uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_AGX_SEC_ENTRY; +uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; /******************************************************************************* diff --git a/plat/intel/soc/agilex/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S index b3f5a5ea..00fe2d99 100644 --- a/plat/intel/soc/agilex/aarch64/plat_helpers.S +++ b/plat/intel/soc/common/aarch64/plat_helpers.S @@ -34,7 +34,7 @@ func plat_secondary_cold_boot_setup poll_mailbox: wfi - mov_imm x0, PLAT_AGX_SEC_ENTRY + mov_imm x0, PLAT_SEC_ENTRY ldr x1, [x0] mov_imm x2, PLAT_CPUID_RELEASE ldr x3, [x2] @@ -66,7 +66,7 @@ func plat_my_core_pos endfunc plat_my_core_pos func plat_get_my_entrypoint - mov_imm x1, PLAT_AGX_SEC_ENTRY + mov_imm x1, PLAT_SEC_ENTRY ldr x0, [x1] ret endfunc plat_get_my_entrypoint diff --git a/plat/intel/soc/agilex/aarch64/platform_common.c b/plat/intel/soc/common/aarch64/platform_common.c index 6d3d817d..6d3d817d 100644 --- a/plat/intel/soc/agilex/aarch64/platform_common.c +++ b/plat/intel/soc/common/aarch64/platform_common.c diff --git a/plat/intel/soc/agilex/bl2_plat_mem_params_desc.c b/plat/intel/soc/common/bl2_plat_mem_params_desc.c index 4f756656..4f756656 100644 --- a/plat/intel/soc/agilex/bl2_plat_mem_params_desc.c +++ b/plat/intel/soc/common/bl2_plat_mem_params_desc.c diff --git a/plat/intel/soc/agilex/include/plat_macros.S b/plat/intel/soc/common/include/plat_macros.S index 43db9a22..43db9a22 100644 --- a/plat/intel/soc/agilex/include/plat_macros.S +++ b/plat/intel/soc/common/include/plat_macros.S diff --git a/plat/intel/soc/agilex/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h index 6ab14090..6ab14090 100644 --- a/plat/intel/soc/agilex/include/socfpga_private.h +++ b/plat/intel/soc/common/include/socfpga_private.h diff --git a/plat/intel/soc/agilex/socfpga_delay_timer.c b/plat/intel/soc/common/socfpga_delay_timer.c index e74b8bd2..ff8a556c 100644 --- a/plat/intel/soc/agilex/socfpga_delay_timer.c +++ b/plat/intel/soc/common/socfpga_delay_timer.c @@ -9,8 +9,8 @@ #include <drivers/delay_timer.h> #include <lib/mmio.h> -#define AGX_GLOBAL_TIMER 0xffd01000 -#define AGX_GLOBAL_TIMER_EN 0x3 +#define SOCFPGA_GLOBAL_TIMER 0xffd01000 +#define SOCFPGA_GLOBAL_TIMER_EN 0x3 /******************************************************************** * The timer delay function @@ -35,5 +35,5 @@ static const timer_ops_t plat_timer_ops = { void socfpga_delay_timer_init(void) { timer_init(&plat_timer_ops); - mmio_write_32(AGX_GLOBAL_TIMER, AGX_GLOBAL_TIMER_EN); + mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN); } diff --git a/plat/intel/soc/agilex/socfpga_image_load.c b/plat/intel/soc/common/socfpga_image_load.c index 67c02bc7..67c02bc7 100644 --- a/plat/intel/soc/agilex/socfpga_image_load.c +++ b/plat/intel/soc/common/socfpga_image_load.c diff --git a/plat/intel/soc/agilex/socfpga_topology.c b/plat/intel/soc/common/socfpga_topology.c index ca1a91e3..ca1a91e3 100644 --- a/plat/intel/soc/agilex/socfpga_topology.c +++ b/plat/intel/soc/common/socfpga_topology.c diff --git a/plat/intel/soc/stratix10/aarch64/plat_helpers.S b/plat/intel/soc/stratix10/aarch64/plat_helpers.S deleted file mode 100644 index f077cf32..00000000 --- a/plat/intel/soc/stratix10/aarch64/plat_helpers.S +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <asm_macros.S> -#include <cpu_macros.S> -#include <platform_def.h> - - .globl plat_secondary_cold_boot_setup - .globl platform_is_primary_cpu - .globl plat_is_my_cpu_primary - .globl plat_my_core_pos - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl plat_crash_console_flush - .globl platform_mem_init - - .globl plat_get_my_entrypoint - - /* ----------------------------------------------------- - * void plat_secondary_cold_boot_setup (void); - * - * This function performs any platform specific actions - * needed for a secondary cpu after a cold reset e.g - * mark the cpu's presence, mechanism to place it in a - * holding pen etc. - * ----------------------------------------------------- - */ -func plat_secondary_cold_boot_setup - /* Wait until the it gets reset signal from rstmgr gets populated */ -poll_mailbox: - wfi - - mov_imm x0, PLAT_S10_SEC_ENTRY - ldr x1, [x0] - mov_imm x2, PLAT_CPUID_RELEASE - ldr x3, [x2] - mrs x4, mpidr_el1 - and x4, x4, #0xff - cmp x3, x4 - b.ne poll_mailbox - br x1 -endfunc plat_secondary_cold_boot_setup - -func platform_is_primary_cpu - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #PLAT_PRIMARY_CPU - cset x0, eq - ret -endfunc platform_is_primary_cpu - -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - b platform_is_primary_cpu -endfunc plat_is_my_cpu_primary - -func plat_my_core_pos - mrs x0, mpidr_el1 - and x1, x0, #MPIDR_CPU_MASK - and x0, x0, #MPIDR_CLUSTER_MASK - add x0, x1, x0, LSR #6 - ret -endfunc plat_my_core_pos - -func plat_get_my_entrypoint - mov_imm x1, PLAT_S10_SEC_ENTRY - ldr x0, [x1] - ret -endfunc plat_get_my_entrypoint - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0, x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, PLAT_UART0_BASE - mov_imm x1, PLAT_UART_CLOCK - mov_imm x2, PLAT_BAUDRATE - b console_16550_core_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(void) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, PLAT_UART0_BASE - b console_16550_core_putc -endfunc plat_crash_console_putc - -func plat_crash_console_flush - mov_imm x0, CRASH_CONSOLE_BASE - b console_16550_core_flush -endfunc plat_crash_console_flush - - - /* -------------------------------------------------------- - * void platform_mem_init (void); - * - * Any memory init, relocation to be done before the - * platform boots. Called very early in the boot process. - * -------------------------------------------------------- - */ -func platform_mem_init - mov x0, #0 - ret -endfunc platform_mem_init - - - .data - .align 3 - diff --git a/plat/intel/soc/stratix10/aarch64/platform_common.c b/plat/intel/soc/stratix10/aarch64/platform_common.c deleted file mode 100644 index 094a3621..00000000 --- a/plat/intel/soc/stratix10/aarch64/platform_common.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch_helpers.h> -#include <lib/xlat_tables/xlat_tables.h> -#include <lib/mmio.h> -#include <platform_def.h> - -unsigned int plat_get_syscnt_freq2(void) -{ - return PLAT_SYS_COUNTER_FREQ_IN_TICKS; -} - -unsigned long plat_get_ns_image_entrypoint(void) -{ - return PLAT_NS_IMAGE_OFFSET; -} - -/****************************************************************************** - * Gets SPSR for BL32 entry - *****************************************************************************/ -uint32_t plat_get_spsr_for_bl32_entry(void) -{ - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL32 image. - */ - return 0; -} - -/****************************************************************************** - * Gets SPSR for BL33 entry - *****************************************************************************/ -uint32_t plat_get_spsr_for_bl33_entry(void) -{ - unsigned long el_status; - unsigned int mode; - uint32_t spsr; - - /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - mode = (el_status) ? MODE_EL2 : MODE_EL1; - - /* - * TODO: Consider the possibility of specifying the SPSR in - * the FIP ToC and allowing the platform to have a say as - * well. - */ - spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); - return spsr; -} - diff --git a/plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c b/plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c deleted file mode 100644 index 4f756656..00000000 --- a/plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <common/bl_common.h> -#include <common/desc_image_load.h> -#include <platform_def.h> -#include <plat/common/platform.h> - - -/******************************************************************************* - * Following descriptor provides BL image/ep information that gets used - * by BL2 to load the images and also subset of this information is - * passed to next BL image. The image loading sequence is managed by - * populating the images in required loading order. The image execution - * sequence is managed by populating the `next_handoff_image_id` with - * the next executable image id. - ******************************************************************************/ -static bl_mem_params_node_t bl2_mem_params_descs[] = { -#ifdef SCP_BL2_BASE - /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = SCP_BL2_SIZE, - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -#endif /* SCP_BL2_BASE */ - -#ifdef EL3_PAYLOAD_BASE - /* Fill EL3 payload related information (BL31 is EL3 payload)*/ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, - -#else /* EL3_PAYLOAD_BASE */ - - /* Fill BL31 related information */ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, - - .next_handoff_image_id = BL33_IMAGE_ID, - }, -#endif /* EL3_PAYLOAD_BASE */ - - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), - .ep_info.pc = PLAT_NS_IMAGE_OFFSET, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_NS_IMAGE_OFFSET, - .image_info.image_max_size = - 0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET, - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -}; - -REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 78301628..8e8b582f 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -19,7 +19,7 @@ #include <common/image_decompress.h> #include <plat/common/platform.h> #include <platform_def.h> -#include <platform_private.h> +#include <socfpga_private.h> #include <drivers/synopsys/dw_mmc.h> #include <lib/mmio.h> #include <lib/xlat_tables/xlat_tables.h> @@ -29,7 +29,7 @@ #include "s10_clock_manager.h" #include "s10_handoff.h" #include "s10_pinmux.h" -#include "aarch64/stratix10_private.h" +#include "stratix10_private.h" #include "include/s10_mailbox.h" #include "qspi/cadence_qspi.h" #include "wdt/watchdog.h" @@ -78,7 +78,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, &console); - plat_delay_timer_init(); + socfpga_delay_timer_init(); init_hard_memory_controller(); } diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 21a37087..7c9833b3 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -21,9 +21,8 @@ #include <lib/mmio.h> #include <plat/common/platform.h> #include <platform_def.h> -#include <platform_private.h> -#include "aarch64/stratix10_private.h" +#include "stratix10_private.h" #include "s10_handoff.h" #include "s10_reset_manager.h" #include "s10_memory_controller.h" @@ -111,16 +110,21 @@ void bl31_platform_setup(void) } const mmap_region_t plat_stratix10_mmap[] = { - MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), - MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, + MT_MEMORY | MT_RW | MT_NS), + MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, + MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, MT_NON_CACHEABLE | MT_RW | MT_SECURE), MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), - {0}, + MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, + MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, + MT_DEVICE | MT_RW | MT_NS), + {0} }; /******************************************************************************* @@ -142,7 +146,7 @@ void bl31_plat_arch_setup(void) BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE), #endif - {0}, + {0} }; setup_page_tables(bl_regions, plat_stratix10_mmap); diff --git a/plat/intel/soc/stratix10/include/plat_macros.S b/plat/intel/soc/stratix10/include/plat_macros.S deleted file mode 100644 index 495aa9dd..00000000 --- a/plat/intel/soc/stratix10/include/plat_macros.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PLAT_MACROS_S__ -#define __PLAT_MACROS_S__ - -#include <platform_def.h> - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant platform registers - * whenever an unhandled exception is taken in - * BL31. - * --------------------------------------------- - */ - .macro plat_crash_print_regs - .endm - -#endif /* __PLAT_MACROS_S__ */ diff --git a/plat/intel/soc/stratix10/platform_def.h b/plat/intel/soc/stratix10/include/platform_def.h index 3ed9023a..a753acd2 100644 --- a/plat/intel/soc/stratix10/platform_def.h +++ b/plat/intel/soc/stratix10/include/platform_def.h @@ -16,7 +16,7 @@ #define PLAT_CPUID_RELEASE 0xffe1b000 -#define PLAT_S10_SEC_ENTRY 0xffe1b008 +#define PLAT_SEC_ENTRY 0xffe1b008 /* Define next boot image name and offset */ #define PLAT_NS_IMAGE_OFFSET 0x50000 diff --git a/plat/intel/soc/stratix10/include/platform_private.h b/plat/intel/soc/stratix10/include/platform_private.h deleted file mode 100644 index db0c1034..00000000 --- a/plat/intel/soc/stratix10/include/platform_private.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PLATFORM_PRIVATE_H__ -#define __PLATFORM_PRIVATE_H__ -#include <common/bl_common.h> - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ -void plat_configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); - - -void plat_configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); - -void plat_gic_driver_init(void); - -void plat_arm_gic_init(void); - -void plat_delay_timer_init(void); - -unsigned long plat_get_ns_image_entrypoint(void); - -uint32_t plat_get_spsr_for_bl32_entry(void); - -uint32_t plat_get_spsr_for_bl33_entry(void); - -#endif /* __PLATFORM_PRIVATE_H__ */ diff --git a/plat/intel/soc/stratix10/aarch64/stratix10_private.h b/plat/intel/soc/stratix10/include/stratix10_private.h index f437202f..f437202f 100644 --- a/plat/intel/soc/stratix10/aarch64/stratix10_private.h +++ b/plat/intel/soc/stratix10/include/stratix10_private.h diff --git a/plat/intel/soc/stratix10/plat_delay_timer.c b/plat/intel/soc/stratix10/plat_delay_timer.c deleted file mode 100644 index bf68cbc1..00000000 --- a/plat/intel/soc/stratix10/plat_delay_timer.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <arch_helpers.h> -#include <drivers/delay_timer.h> -#include <lib/mmio.h> - -#define S10_GLOBAL_TIMER 0xffd01000 -#define S10_GLOBAL_TIMER_EN 0x3 - -/******************************************************************** - * The timer delay function - ********************************************************************/ -static uint32_t plat_get_timer_value(void) -{ - /* - * Generic delay timer implementation expects the timer to be a down - * counter. We apply bitwise NOT operator to the tick values returned - * by read_cntpct_el0() to simulate the down counter. The value is - * clipped from 64 to 32 bits. - */ - return (uint32_t)(~read_cntpct_el0()); -} - -static const timer_ops_t plat_timer_ops = { - .get_timer_value = plat_get_timer_value, - .clk_mult = 1, - .clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ, -}; - -void plat_delay_timer_init(void) -{ - timer_init(&plat_timer_ops); - mmio_write_32(S10_GLOBAL_TIMER, S10_GLOBAL_TIMER_EN); -} diff --git a/plat/intel/soc/stratix10/plat_psci.c b/plat/intel/soc/stratix10/plat_psci.c index 75785288..f4a970e7 100644 --- a/plat/intel/soc/stratix10/plat_psci.c +++ b/plat/intel/soc/stratix10/plat_psci.c @@ -15,14 +15,13 @@ #include <lib/psci/psci.h> #include "platform_def.h" -#include "platform_private.h" #include "s10_reset_manager.h" #include "s10_mailbox.h" #define S10_RSTMGR_OFST 0xffd11000 #define S10_RSTMGR_MPUMODRST_OFST 0x20 -uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_S10_SEC_ENTRY; +uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; /******************************************************************************* diff --git a/plat/intel/soc/stratix10/plat_storage.c b/plat/intel/soc/stratix10/plat_storage.c index f5fd8715..0b8b9cd2 100644 --- a/plat/intel/soc/stratix10/plat_storage.c +++ b/plat/intel/soc/stratix10/plat_storage.c @@ -21,7 +21,7 @@ #include <lib/utils.h> #include <common/tbbr/tbbr_img_def.h> #include "platform_def.h" -#include "aarch64/stratix10_private.h" +#include "stratix10_private.h" #define STRATIX10_FIP_BASE (0) #define STRATIX10_FIP_MAX_SIZE (0x1000000) diff --git a/plat/intel/soc/stratix10/plat_topology.c b/plat/intel/soc/stratix10/plat_topology.c deleted file mode 100644 index 4951f742..00000000 --- a/plat/intel/soc/stratix10/plat_topology.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <platform_def.h> -#include <lib/psci/psci.h> -static const unsigned char plat_power_domain_tree_desc[] = {1, 4}; - -/******************************************************************************* - * This function returns the default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return plat_power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) - return -1; - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) - return -1; - - /* - * Validate cpu_id by checking whether it represents a CPU in - * one of the two clusters present on the platform. - */ - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) - return -1; - - return (cpu_id + (cluster_id * 4)); -} - diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index a21280fe..34674b0c 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -5,9 +5,9 @@ # PLAT_INCLUDES := \ - -Iplat/intel/soc/stratix10/ \ -Iplat/intel/soc/stratix10/include/ \ - -Iplat/intel/soc/common/drivers/ + -Iplat/intel/soc/common/drivers/ \ + -Iplat/intel/soc/common/include/ PLAT_BL_COMMON_SOURCES := \ lib/xlat_tables/xlat_tables_common.c \ @@ -15,12 +15,12 @@ PLAT_BL_COMMON_SOURCES := \ drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ - plat/common/plat_gicv2.c \ + plat/common/plat_gicv2.c \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/ti/uart/aarch64/16550_console.S \ - plat/intel/soc/stratix10/aarch64/platform_common.c \ - plat/intel/soc/stratix10/aarch64/plat_helpers.S \ + plat/intel/soc/common/aarch64/platform_common.c \ + plat/intel/soc/common/aarch64/plat_helpers.S BL2_SOURCES += \ drivers/partition/partition.c \ @@ -35,15 +35,15 @@ BL2_SOURCES += \ drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ plat/intel/soc/stratix10/bl2_plat_setup.c \ plat/intel/soc/stratix10/plat_storage.c \ - plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c \ + plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c \ plat/intel/soc/stratix10/soc/s10_handoff.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c \ plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_memory_controller.c \ - plat/intel/soc/stratix10/plat_delay_timer.c \ + plat/intel/soc/common/socfpga_delay_timer.c \ lib/cpus/aarch64/cortex_a53.S \ - plat/intel/soc/stratix10/stratix10_image_load.c \ + plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/stratix10/soc/s10_system_manager.c \ common/desc_image_load.c \ plat/intel/soc/stratix10/soc/s10_mailbox.c \ @@ -58,13 +58,13 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/intel/soc/stratix10/plat_sip_svc.c \ plat/intel/soc/stratix10/bl31_plat_setup.c \ plat/intel/soc/stratix10/plat_psci.c \ - plat/intel/soc/stratix10/plat_topology.c \ - plat/intel/soc/stratix10/plat_delay_timer.c \ + plat/intel/soc/common/socfpga_topology.c \ + plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c\ plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c\ plat/intel/soc/stratix10/soc/s10_handoff.c \ - plat/intel/soc/stratix10/soc/s10_mailbox.c \ + plat/intel/soc/stratix10/soc/s10_mailbox.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c index dc90076c..b4d05735 100644 --- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c @@ -10,7 +10,6 @@ #include <drivers/delay_timer.h> #include <lib/mmio.h> #include <platform_def.h> -#include <platform_private.h> #include "s10_clock_manager.h" #include "s10_handoff.h" diff --git a/plat/intel/soc/stratix10/soc/s10_handoff.c b/plat/intel/soc/stratix10/soc/s10_handoff.c index 55516c08..1a4d5c32 100644 --- a/plat/intel/soc/stratix10/soc/s10_handoff.c +++ b/plat/intel/soc/stratix10/soc/s10_handoff.c @@ -13,7 +13,6 @@ #include <string.h> #include <plat/common/platform.h> #include <platform_def.h> -#include <platform_private.h> #include "s10_handoff.h" diff --git a/plat/intel/soc/stratix10/soc/s10_reset_manager.c b/plat/intel/soc/stratix10/soc/s10_reset_manager.c index 8b58db65..8b7420bf 100644 --- a/plat/intel/soc/stratix10/soc/s10_reset_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_reset_manager.c @@ -14,7 +14,6 @@ #include <lib/mmio.h> #include <plat/common/platform.h> #include <platform_def.h> -#include <platform_private.h> #include "s10_reset_manager.h" void deassert_peripheral_reset(void) diff --git a/plat/intel/soc/stratix10/stratix10_image_load.c b/plat/intel/soc/stratix10/stratix10_image_load.c deleted file mode 100644 index 67c02bc7..00000000 --- a/plat/intel/soc/stratix10/stratix10_image_load.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <common/desc_image_load.h> - -/******************************************************************************* - * This function flushes the data structures so that they are visible - * in memory for the next BL image. - ******************************************************************************/ -void plat_flush_next_bl_params(void) -{ - flush_bl_params_desc(); -} - -/******************************************************************************* - * This function returns the list of loadable images. - ******************************************************************************/ -bl_load_info_t *plat_get_bl_image_load_info(void) -{ - return get_bl_load_info_from_mem_params_desc(); -} - -/******************************************************************************* - * This function returns the list of executable images. - ******************************************************************************/ -bl_params_t *plat_get_next_bl_params(void) -{ - return get_next_bl_params_from_mem_params_desc(); -} diff --git a/plat/layerscape/common/include/ls_16550.h b/plat/layerscape/common/include/ls_16550.h index b0b1856f..cb4514f3 100644 --- a/plat/layerscape/common/include/ls_16550.h +++ b/plat/layerscape/common/include/ls_16550.h @@ -63,7 +63,7 @@ #define CONSOLE_T_16550_BASE CONSOLE_T_DRVDATA -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -81,6 +81,6 @@ typedef struct { int console_ls_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, console_ls_16550_t *console); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* LS_16550_H */ diff --git a/plat/layerscape/common/ls_bl1_setup.c b/plat/layerscape/common/ls_bl1_setup.c index 163b35c4..fff065ef 100644 --- a/plat/layerscape/common/ls_bl1_setup.c +++ b/plat/layerscape/common/ls_bl1_setup.c @@ -59,11 +59,11 @@ void ls_bl1_plat_arch_setup(void) #endif ); VERBOSE("After setup the page tables\n"); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el3(0); -#endif /* AARCH32 */ +#else + enable_mmu_svc_mon(0); +#endif /* __aarch64__ */ VERBOSE("After MMU enabled\n"); } diff --git a/plat/layerscape/common/ls_bl2_setup.c b/plat/layerscape/common/ls_bl2_setup.c index 192eaec4..35f42e1f 100644 --- a/plat/layerscape/common/ls_bl2_setup.c +++ b/plat/layerscape/common/ls_bl2_setup.c @@ -54,10 +54,10 @@ void ls_bl2_plat_arch_setup(void) #endif ); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el1(0); +#else + enable_mmu_svc_mon(0); #endif } @@ -74,7 +74,7 @@ int ls_bl2_handle_post_image_load(unsigned int image_id) assert(bl_mem_params); switch (image_id) { -#ifdef AARCH64 +#ifdef __aarch64__ case BL32_IMAGE_ID: bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry(); break; diff --git a/plat/layerscape/common/ls_common.c b/plat/layerscape/common/ls_common.c index 3b42909c..23c0d00a 100644 --- a/plat/layerscape/common/ls_common.c +++ b/plat/layerscape/common/ls_common.c @@ -143,7 +143,7 @@ uint32_t ls_get_spsr_for_bl32_entry(void) /******************************************************************************* * Gets SPSR for BL33 entry ******************************************************************************/ -#ifndef AARCH32 +#ifdef __aarch64__ uint32_t ls_get_spsr_for_bl33_entry(void) { unsigned int mode; @@ -181,7 +181,7 @@ uint32_t ls_get_spsr_for_bl33_entry(void) SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); return spsr; } -#endif /* AARCH32 */ +#endif /* __aarch64__ */ /******************************************************************************* * Returns Layerscape platform specific memory map regions. diff --git a/plat/marvell/a3700/common/include/platform_def.h b/plat/marvell/a3700/common/include/platform_def.h index 16865c4d..591f0458 100644 --- a/plat/marvell/a3700/common/include/platform_def.h +++ b/plat/marvell/a3700/common/include/platform_def.h @@ -8,9 +8,9 @@ #ifndef PLATFORM_DEF_H #define PLATFORM_DEF_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdio.h> -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #include <board_marvell_def.h> #include <mvebu_def.h> diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h index 3f6154e7..b9c2e0ed 100644 --- a/plat/marvell/a8k/common/include/platform_def.h +++ b/plat/marvell/a8k/common/include/platform_def.h @@ -8,9 +8,9 @@ #ifndef PLATFORM_DEF_H #define PLATFORM_DEF_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdio.h> -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #include <common/interrupt_props.h> #include <drivers/arm/gic_common.h> diff --git a/plat/mediatek/mt8183/drivers/mcsi/mcsi.h b/plat/mediatek/mt8183/drivers/mcsi/mcsi.h index 8a588bfb..863e7dab 100644 --- a/plat/mediatek/mt8183/drivers/mcsi/mcsi.h +++ b/plat/mediatek/mt8183/drivers/mcsi/mcsi.h @@ -85,7 +85,7 @@ #define CCI_CLK_CTRL (MCUCFG_BASE + 0x660) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <plat/common/common_def.h> #include <stdint.h> @@ -112,5 +112,5 @@ void cci_secure_switch(unsigned int ns); void cci_init_sf(void); unsigned long cci_reg_access(unsigned int op, unsigned long offset, unsigned long val); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* MCSI_H */ diff --git a/plat/meson/gxl/gxl_bl31_setup.c b/plat/meson/gxl/gxl_bl31_setup.c index f8ce6605..b1da7942 100644 --- a/plat/meson/gxl/gxl_bl31_setup.c +++ b/plat/meson/gxl/gxl_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <common/interrupt_props.h> #include <plat/common/platform.h> #include <platform_def.h> +#include <lib/mmio.h> #include <lib/xlat_tables/xlat_mmu_helpers.h> #include "gxl_private.h" @@ -100,12 +101,19 @@ void bl31_plat_arch_setup(void) enable_mmu_el3(0); } +static inline bool gxl_scp_ready(void) +{ + return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT)); +} + static inline void gxl_scp_boot(void) { scpi_upload_scp_fw(bl30_image_info.image_base, bl30_image_info.image_size, 0); scpi_upload_scp_fw(bl301_image_info.image_base, bl301_image_info.image_size, 1); + while (!gxl_scp_ready()) + ; } /******************************************************************************* diff --git a/plat/meson/gxl/gxl_def.h b/plat/meson/gxl/gxl_def.h index ada26560..089fa8db 100644 --- a/plat/meson/gxl/gxl_def.h +++ b/plat/meson/gxl/gxl_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -91,6 +91,12 @@ #define GXBB_SYS_CPU_CFG7 UL(0xC8834664) #define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) +#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C) +#define GXBB_AO_RTI_SCP_READY_OFF U(0x14) +#define GXBB_A0_RTI_SCP_READY_MASK U(3) +#define GXBB_AO_RTI_SCP_IS_READY(v) \ + ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \ + GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK) #define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) #define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) diff --git a/plat/meson/gxl/gxl_pm.c b/plat/meson/gxl/gxl_pm.c index d9b69ef8..4a5d26e9 100644 --- a/plat/meson/gxl/gxl_pm.c +++ b/plat/meson/gxl/gxl_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,20 +27,29 @@ static uintptr_t gxbb_sec_entrypoint; static volatile uint32_t gxbb_cpu0_go; -static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value) +static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) { unsigned int core = plat_gxbb_calc_core_pos(mpidr); uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); mmio_write_64(cpu_mailbox_addr, value); - flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t)); +} + +static void gxl_pm_reset(u_register_t mpidr) +{ + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8; + + mmio_write_32(cpu_mailbox_addr, 0); } static void __dead2 gxbb_system_reset(void) { INFO("BL31: PSCI_SYSTEM_RESET\n"); + u_register_t mpidr = read_mpidr_el1(); uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); + int ret; NOTICE("BL31: Reboot reason: 0x%x\n", status); @@ -50,13 +59,15 @@ static void __dead2 gxbb_system_reset(void) mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); - int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); + ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); if (ret != 0) { - ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret); + ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret); panic(); } + gxl_pm_reset(mpidr); + wfi(); ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n"); @@ -67,14 +78,18 @@ static void __dead2 gxbb_system_off(void) { INFO("BL31: PSCI_SYSTEM_OFF\n"); - unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); + u_register_t mpidr = read_mpidr_el1(); + int ret; + + ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); if (ret != 0) { - ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret); + ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret); panic(); } - gxbb_program_mailbox(read_mpidr_el1(), 0); + gxl_pm_set_reset_addr(mpidr, 0); + gxl_pm_reset(mpidr); wfi(); @@ -101,7 +116,7 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr) return PSCI_E_SUCCESS; } - gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint); + gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint); scpi_set_css_power_state(mpidr, SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); dmbsy(); @@ -133,10 +148,6 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); unsigned int core = plat_gxbb_calc_core_pos(mpidr); - uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4); - - mmio_write_32(addr, 0xFFFFFFFF); - flush_dcache_range(addr, sizeof(uint32_t)); gicv2_cpuif_disable(); @@ -151,7 +162,8 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) { - unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + u_register_t mpidr = read_mpidr_el1(); + unsigned int core = plat_gxbb_calc_core_pos(mpidr); /* CPU0 can't be turned OFF, emulate it with a WFE loop */ if (core == GXBB_PRIMARY_CPU) { @@ -162,10 +174,19 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t VERBOSE("BL31: CPU0 resumed.\n"); - write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT); + /* + * Because setting CPU0's warm reset entrypoint through PSCI + * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem + * to work, jump to it manually. + * In order to avoid an assert, mmu has to be disabled. + */ + disable_mmu_el3(); + ((void(*)(void))gxbb_sec_entrypoint)(); } dsbsy(); + gxl_pm_set_reset_addr(mpidr, 0); + gxl_pm_reset(mpidr); for (;;) wfi(); diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h index 9cbadd3e..a4085e24 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h @@ -9,7 +9,7 @@ #include <tegra_def.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <lib/mmio.h> #include <stdint.h> @@ -173,6 +173,6 @@ tegra_mc_settings_t *tegra_get_mc_settings(void); ******************************************************************************/ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* MEMCTRL_V2_H */ diff --git a/plat/nvidia/tegra/include/tegra_platform.h b/plat/nvidia/tegra/include/tegra_platform.h index b9c37824..d83ce48b 100644 --- a/plat/nvidia/tegra/include/tegra_platform.h +++ b/plat/nvidia/tegra/include/tegra_platform.h @@ -30,7 +30,7 @@ #define TEGRA_CHIPID_TEGRA21 U(0x21) #define TEGRA_CHIPID_TEGRA18 U(0x18) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* * Tegra chip ID major/minor identifiers @@ -57,6 +57,6 @@ bool tegra_platform_is_fpga(void); bool tegra_platform_is_unit_fpga(void); bool tegra_platform_is_virt_dev_kit(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* TEGRA_PLATFORM_H */ diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h index 2dd10ad8..d7f77cc7 100644 --- a/plat/qemu/include/platform_def.h +++ b/plat/qemu/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -197,7 +197,7 @@ #define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE #define DEVICE0_BASE 0x08000000 -#define DEVICE0_SIZE 0x00021000 +#define DEVICE0_SIZE 0x01000000 #define DEVICE1_BASE 0x09000000 #define DEVICE1_SIZE 0x00041000 @@ -207,7 +207,7 @@ #define GICD_BASE 0x8000000 #define GICC_BASE 0x8010000 -#define GICR_BASE 0 +#define GICR_BASE 0x80A0000 #define QEMU_IRQ_SEC_SGI_0 8 @@ -219,6 +219,30 @@ #define QEMU_IRQ_SEC_SGI_6 14 #define QEMU_IRQ_SEC_SGI_7 15 +/****************************************************************************** + * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 + * interrupts. + *****************************************************************************/ +#define PLATFORM_G1S_PROPS(grp) \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE) + +#define PLATFORM_G0_PROPS(grp) + /* * DT related constants */ diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk index 85d83eaa..6b9749c7 100644 --- a/plat/qemu/platform.mk +++ b/plat/qemu/platform.mk @@ -1,9 +1,12 @@ # -# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # +# Use the GICv2 driver on QEMU by default +QEMU_USE_GIC_DRIVER := QEMU_GICV2 + ifeq (${ARM_ARCH_MAJOR},7) # ARMv7 Qemu support in trusted firmware expects the Cortex-A15 model. # Qemu Cortex-A15 model does not implement the virtualization extension. @@ -120,20 +123,36 @@ ifeq ($(add-lib-optee),yes) BL2_SOURCES += lib/optee/optee_utils.c endif +QEMU_GICV2_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/plat_gicv2.c \ + plat/qemu/qemu_gicv2.c + +QEMU_GICV3_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/plat_gicv3.c \ + plat/qemu/qemu_gicv3.c + +ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV2) +QEMU_GIC_SOURCES := ${QEMU_GICV2_SOURCES} +else ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV3) +QEMU_GIC_SOURCES := ${QEMU_GICV3_SOURCES} +else +$(error "Incorrect GIC driver chosen for QEMU platform") +endif ifeq (${ARM_ARCH_MAJOR},8) BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ - drivers/arm/gic/v2/gicv2_helpers.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/common/gic_common.c \ - plat/common/plat_gicv2.c \ plat/common/plat_psci_common.c \ plat/qemu/qemu_pm.c \ plat/qemu/topology.c \ plat/qemu/aarch64/plat_helpers.S \ - plat/qemu/qemu_bl31_setup.c + plat/qemu/qemu_bl31_setup.c \ + ${QEMU_GIC_SOURCES} endif # Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c index b5821517..67f33273 100644 --- a/plat/qemu/qemu_bl1_setup.c +++ b/plat/qemu/qemu_bl1_setup.c @@ -41,10 +41,10 @@ void bl1_early_platform_setup(void) * does basic initialization. Later architectural setup (bl1_arch_setup()) * does not do anything platform specific. *****************************************************************************/ -#ifdef AARCH32 -#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) -#else +#ifdef __aarch64__ #define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__) +#else +#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) #endif void bl1_plat_arch_setup(void) diff --git a/plat/qemu/qemu_bl2_mem_params_desc.c b/plat/qemu/qemu_bl2_mem_params_desc.c index ba6a4db2..a01f2dc9 100644 --- a/plat/qemu/qemu_bl2_mem_params_desc.c +++ b/plat/qemu/qemu_bl2_mem_params_desc.c @@ -35,7 +35,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { .next_handoff_image_id = INVALID_IMAGE_ID, }, #else /* EL3_PAYLOAD_BASE */ -#ifdef AARCH64 +#ifdef __aarch64__ /* Fill BL31 related information */ { .image_id = BL31_IMAGE_ID, @@ -59,10 +59,10 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { .next_handoff_image_id = BL33_IMAGE_ID, # endif }, -#endif /* AARCH64 */ +#endif /* __aarch64__ */ # ifdef QEMU_LOAD_BL32 -#ifdef AARCH64 +#ifdef __aarch64__ #define BL32_EP_ATTRIBS (SECURE | EXECUTABLE) #define BL32_IMG_ATTRIBS 0 #else diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c index b8ca895f..4c97c8dd 100644 --- a/plat/qemu/qemu_bl2_setup.c +++ b/plat/qemu/qemu_bl2_setup.c @@ -81,10 +81,10 @@ void bl2_platform_setup(void) /* TODO Initialize timer */ } -#ifdef AARCH32 -#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) -#else +#ifdef __aarch64__ #define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__) +#else +#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) #endif void bl2_plat_arch_setup(void) @@ -101,7 +101,7 @@ void bl2_plat_arch_setup(void) ******************************************************************************/ static uint32_t qemu_get_spsr_for_bl32_entry(void) { -#ifdef AARCH64 +#ifdef __aarch64__ /* * The Secure Payload Dispatcher service is responsible for * setting the SPSR prior to entry into the BL3-2 image. @@ -119,7 +119,7 @@ static uint32_t qemu_get_spsr_for_bl32_entry(void) static uint32_t qemu_get_spsr_for_bl33_entry(void) { uint32_t spsr; -#ifdef AARCH64 +#ifdef __aarch64__ unsigned int mode; /* Figure out what mode we enter the non-secure world in */ diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c index 7453b890..4d36b039 100644 --- a/plat/qemu/qemu_bl31_setup.c +++ b/plat/qemu/qemu_bl31_setup.c @@ -1,16 +1,12 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> -#include <platform_def.h> - #include <common/bl_common.h> -#include <drivers/arm/gic_common.h> -#include <drivers/arm/gicv2.h> #include <plat/common/platform.h> #include "qemu_private.h" @@ -73,49 +69,9 @@ void bl31_plat_arch_setup(void) BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); } -/****************************************************************************** - * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 - * interrupts. - *****************************************************************************/ -#define PLATFORM_G1S_PROPS(grp) \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE) - -#define PLATFORM_G0_PROPS(grp) - -static const interrupt_prop_t qemu_interrupt_props[] = { - PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), - PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) -}; - -static const struct gicv2_driver_data plat_gicv2_driver_data = { - .gicd_base = GICD_BASE, - .gicc_base = GICC_BASE, - .interrupt_props = qemu_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), -}; - void bl31_platform_setup(void) { - /* Initialize the gic cpu and distributor interfaces */ - gicv2_driver_init(&plat_gicv2_driver_data); - gicv2_distif_init(); - gicv2_pcpu_distif_init(); - gicv2_cpuif_enable(); + plat_qemu_gic_init(); } unsigned int plat_get_syscnt_freq2(void) diff --git a/plat/qemu/qemu_common.c b/plat/qemu/qemu_common.c index aee8321c..56bf9532 100644 --- a/plat/qemu/qemu_common.c +++ b/plat/qemu/qemu_common.c @@ -132,11 +132,11 @@ static const mmap_region_t plat_qemu_mmap[] = { } /* Define EL1 and EL3 variants of the function initialising the MMU */ -#ifdef AARCH32 -DEFINE_CONFIGURE_MMU_EL(svc_mon) -#else +#ifdef __aarch64__ DEFINE_CONFIGURE_MMU_EL(el1) DEFINE_CONFIGURE_MMU_EL(el3) +#else +DEFINE_CONFIGURE_MMU_EL(svc_mon) #endif diff --git a/plat/qemu/qemu_gicv2.c b/plat/qemu/qemu_gicv2.c new file mode 100644 index 00000000..fb566227 --- /dev/null +++ b/plat/qemu/qemu_gicv2.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <drivers/arm/gicv2.h> +#include <drivers/arm/gic_common.h> +#include <platform_def.h> + +static const interrupt_prop_t qemu_interrupt_props[] = { + PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), + PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) +}; + +static const struct gicv2_driver_data plat_gicv2_driver_data = { + .gicd_base = GICD_BASE, + .gicc_base = GICC_BASE, + .interrupt_props = qemu_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), +}; + +void plat_qemu_gic_init(void) +{ + /* Initialize the gic cpu and distributor interfaces */ + gicv2_driver_init(&plat_gicv2_driver_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +void qemu_pwr_gic_on_finish(void) +{ + /* TODO: This setup is needed only after a cold boot */ + gicv2_pcpu_distif_init(); + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); +} diff --git a/plat/qemu/qemu_gicv3.c b/plat/qemu/qemu_gicv3.c new file mode 100644 index 00000000..28572c5e --- /dev/null +++ b/plat/qemu/qemu_gicv3.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <drivers/arm/gicv3.h> +#include <drivers/arm/gic_common.h> +#include <platform_def.h> +#include <plat/common/platform.h> + +static const interrupt_prop_t qemu_interrupt_props[] = { + PLATFORM_G1S_PROPS(INTR_GROUP1S), + PLATFORM_G0_PROPS(INTR_GROUP0) +}; + +static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr) +{ + return (unsigned int)plat_core_pos_by_mpidr(mpidr); +} + +static const gicv3_driver_data_t qemu_gicv3_driver_data = { + .gicd_base = GICD_BASE, + .gicr_base = GICR_BASE, + .interrupt_props = qemu_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = qemu_rdistif_base_addrs, + .mpidr_to_core_pos = qemu_mpidr_to_core_pos +}; + +void plat_qemu_gic_init(void) +{ + gicv3_driver_init(&qemu_gicv3_driver_data); + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +void qemu_pwr_gic_on_finish(void) +{ + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} diff --git a/plat/qemu/qemu_pm.c b/plat/qemu/qemu_pm.c index 3249d6e2..a199688d 100644 --- a/plat/qemu/qemu_pm.c +++ b/plat/qemu/qemu_pm.c @@ -1,19 +1,19 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> - #include <platform_def.h> #include <arch_helpers.h> #include <common/debug.h> -#include <drivers/arm/gicv2.h> #include <lib/psci/psci.h> #include <plat/common/platform.h> +#include "qemu_private.h" + /* * The secure entry point to be used on warm reset. */ @@ -173,11 +173,7 @@ void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state) assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == PLAT_LOCAL_STATE_OFF); - /* TODO: This setup is needed only after a cold boot */ - gicv2_pcpu_distif_init(); - - /* Enable the gic cpu interface */ - gicv2_cpuif_enable(); + qemu_pwr_gic_on_finish(); } /******************************************************************************* diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h index 754831ab..46b1ca1e 100644 --- a/plat/qemu/qemu_private.h +++ b/plat/qemu/qemu_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,4 +33,7 @@ int dt_add_psci_cpu_enable_methods(void *fdt); void qemu_console_init(void); +void plat_qemu_gic_init(void); +void qemu_pwr_gic_on_finish(void); + #endif /* QEMU_PRIVATE_H */ diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h index bbe4a548..b7f0ca11 100644 --- a/plat/renesas/rcar/include/platform_def.h +++ b/plat/renesas/rcar/include/platform_def.h @@ -7,7 +7,7 @@ #ifndef PLATFORM_DEF_H #define PLATFORM_DEF_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdlib.h> #endif diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h index 98143b7f..990d1065 100644 --- a/plat/rockchip/common/include/plat_private.h +++ b/plat/rockchip/common/include/plat_private.h @@ -7,7 +7,7 @@ #ifndef PLAT_PRIVATE_H #define PLAT_PRIVATE_H -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -60,16 +60,7 @@ extern uint32_t __sram_incbin_real_end; /****************************************************************************** * Function and variable prototypes *****************************************************************************/ -#ifdef AARCH32 -void plat_configure_mmu_svc_mon(unsigned long total_base, - unsigned long total_size, - unsigned long, - unsigned long, - unsigned long, - unsigned long); - -void rockchip_plat_mmu_svc_mon(void); -#else +#ifdef __aarch64__ void plat_configure_mmu_el3(unsigned long total_base, unsigned long total_size, unsigned long, @@ -78,6 +69,15 @@ void plat_configure_mmu_el3(unsigned long total_base, unsigned long); void rockchip_plat_mmu_el3(void); +#else +void plat_configure_mmu_svc_mon(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); + +void rockchip_plat_mmu_svc_mon(void); #endif void plat_cci_init(void); @@ -142,7 +142,7 @@ uint32_t rockchip_get_uart_base(void); uint32_t rockchip_get_uart_baudrate(void); uint32_t rockchip_get_uart_clock(void); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ /****************************************************************************** * cpu up status diff --git a/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h index b22ddc29..34af29a8 100644 --- a/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h +++ b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h @@ -26,7 +26,7 @@ #define PM_WARM_BOOT_SHT 0 #define PM_WARM_BOOT_BIT (1 << PM_WARM_BOOT_SHT) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ struct psram_data_t { uint64_t sp; @@ -50,6 +50,6 @@ CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR, extern void *sys_sleep_flag_sram; -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c index bf78a145..440e6aa1 100644 --- a/plat/socionext/uniphier/uniphier_bl31_setup.c +++ b/plat/socionext/uniphier/uniphier_bl31_setup.c @@ -35,7 +35,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, { void *from_bl2; - from_bl2 = (void *) arg0; + from_bl2 = (void *)arg0; bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head; @@ -76,7 +76,7 @@ void bl31_platform_setup(void) /* Enable and initialize the System level generic timer */ mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF, - CNTCR_FCREQ(0U) | CNTCR_EN); + CNTCR_FCREQ(0U) | CNTCR_EN); } void bl31_plat_arch_setup(void) diff --git a/plat/socionext/uniphier/uniphier_gicv3.c b/plat/socionext/uniphier/uniphier_gicv3.c index 5148e8f9..266efe7b 100644 --- a/plat/socionext/uniphier/uniphier_gicv3.c +++ b/plat/socionext/uniphier/uniphier_gicv3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,34 +21,34 @@ static const interrupt_prop_t uniphier_interrupt_props[] = { /* SGI0 */ INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI6 */ INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* G1S interrupts */ /* Timer */ INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_LEVEL), + GIC_INTR_CFG_LEVEL), /* SGI1 */ INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI2 */ INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI3 */ INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI4 */ INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI5 */ INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI7 */ INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE) + GIC_INTR_CFG_EDGE) }; static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr) diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c index 451e84f9..b456bc53 100644 --- a/plat/socionext/uniphier/uniphier_io_storage.c +++ b/plat/socionext/uniphier/uniphier_io_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -331,7 +331,7 @@ int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, assert(image_id < ARRAY_SIZE(uniphier_io_policies)); - *dev_handle = *(uniphier_io_policies[image_id].dev_handle); + *dev_handle = *uniphier_io_policies[image_id].dev_handle; *image_spec = uniphier_io_policies[image_id].image_spec; init_params = uniphier_io_policies[image_id].init_params; diff --git a/plat/socionext/uniphier/uniphier_nand.c b/plat/socionext/uniphier/uniphier_nand.c index 271aa0f4..27e10e4b 100644 --- a/plat/socionext/uniphier/uniphier_nand.c +++ b/plat/socionext/uniphier/uniphier_nand.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,8 +16,6 @@ #include "uniphier.h" -#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) - #define NAND_CMD_READ0 0 #define NAND_CMD_READSTART 0x30 @@ -166,7 +164,7 @@ static size_t __uniphier_nand_read(struct uniphier_nand *nand, int lba, int pages_per_block = nand->pages_per_block; int page_size = nand->page_size; int blocks_to_skip = lba / pages_per_block; - int pages_to_read = DIV_ROUND_UP(size, page_size); + int pages_to_read = div_round_up(size, page_size); int page = lba % pages_per_block; int block = 0; uintptr_t p = buf; diff --git a/plat/socionext/uniphier/uniphier_psci.c b/plat/socionext/uniphier/uniphier_psci.c index ce11aa7c..464252dd 100644 --- a/plat/socionext/uniphier/uniphier_psci.c +++ b/plat/socionext/uniphier/uniphier_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ #define UNIPHIER_ROM_RSV0 0x59801200 #define UNIPHIER_SLFRSTSEL 0x61843010 -#define UNIPHIER_SLFRSTSEL_MASK (0x3 << 0) +#define UNIPHIER_SLFRSTSEL_MASK GENMASK(1, 0) #define UNIPHIER_SLFRSTCTL 0x61843014 -#define UNIPHIER_SLFRSTCTL_RST (1 << 0) +#define UNIPHIER_SLFRSTCTL_RST BIT(0) #define MPIDR_AFFINITY_INVALID ((u_register_t)-1) @@ -58,7 +58,7 @@ static void __dead2 uniphier_psci_pwr_domain_pwr_down_wfi( const psci_power_state_t *target_state) { /* - * The Boot ROM cannot distinguish warn and cold resets. + * The Boot ROM cannot distinguish warm and cold resets. * Instead of the CPU reset, fake it. */ uniphier_holding_pen_release = MPIDR_AFFINITY_INVALID; diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 94c4c5b3..37941aa7 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -14,7 +14,7 @@ #include <lib/utils_def.h> #include <lib/xlat_tables/xlat_tables_defs.h> -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <drivers/st/stm32mp1_clk.h> #include <boot_api.h> @@ -40,7 +40,7 @@ #endif /* DDR power initializations */ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ enum ddr_type { STM32MP_DDR3, STM32MP_LPDDR2, @@ -254,7 +254,7 @@ enum ddr_type { #define TAMP_BASE U(0x5C00A000) #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) -#if !(defined(__LINKER__) || defined(__ASSEMBLY__)) +#if !(defined(__LINKER__) || defined(__ASSEMBLER__)) static inline uint32_t tamp_bkpr(uint32_t idx) { return TAMP_BKP_REGISTER_BASE + (idx << 2); diff --git a/services/spd/opteed/opteed.mk b/services/spd/opteed/opteed.mk index b1b21751..643b0542 100644 --- a/services/spd/opteed/opteed.mk +++ b/services/spd/opteed/opteed.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -13,3 +13,6 @@ SPD_SOURCES := services/spd/opteed/opteed_common.c \ services/spd/opteed/opteed_pm.c NEED_BL32 := yes + +# required so that optee code can control access to the timer registers +NS_TIMER_SWITCH := 1 diff --git a/services/spd/opteed/opteed_private.h b/services/spd/opteed/opteed_private.h index 847b9c5c..242154f0 100644 --- a/services/spd/opteed/opteed_private.h +++ b/services/spd/opteed/opteed_private.h @@ -79,7 +79,7 @@ #define OPTEED_C_RT_CTX_SIZE 0x60 #define OPTEED_C_RT_CTX_ENTRIES (OPTEED_C_RT_CTX_SIZE >> DWORD_SHIFT) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -157,6 +157,6 @@ void opteed_init_optee_ep_state(struct entry_point_info *optee_entry_point, extern optee_context_t opteed_sp_context[OPTEED_CORE_COUNT]; extern uint32_t opteed_rw; extern struct optee_vectors *optee_vector_table; -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* OPTEED_PRIVATE_H */ diff --git a/services/spd/tlkd/tlkd_private.h b/services/spd/tlkd/tlkd_private.h index 53f9e20c..5d5d0e85 100644 --- a/services/spd/tlkd/tlkd_private.h +++ b/services/spd/tlkd/tlkd_private.h @@ -71,7 +71,7 @@ #define TLKD_C_RT_CTX_SIZE 0x60 #define TLKD_C_RT_CTX_ENTRIES (TLKD_C_RT_CTX_SIZE >> DWORD_SHIFT) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -119,6 +119,6 @@ void tlkd_init_tlk_ep_state(struct entry_point_info *tlk_entry_point, uint64_t pc, tlk_context_t *tlk_ctx); -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* TLKD_PRIVATE_H */ diff --git a/services/spd/tspd/tspd_private.h b/services/spd/tspd/tspd_private.h index 50f3b875..a81eb212 100644 --- a/services/spd/tspd/tspd_private.h +++ b/services/spd/tspd/tspd_private.h @@ -126,7 +126,7 @@ #define TSPD_SP_CTX_SIZE 0x90 #define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -227,6 +227,6 @@ uint64_t tspd_handle_sp_preemption(void *handle); extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; extern tsp_vectors_t *tsp_vectors; -#endif /*__ASSEMBLY__*/ +#endif /*__ASSEMBLER__*/ #endif /* TSPD_PRIVATE_H */ diff --git a/services/std_svc/sdei/sdei_private.h b/services/std_svc/sdei/sdei_private.h index 8cc66e76..44a73013 100644 --- a/services/std_svc/sdei/sdei_private.h +++ b/services/std_svc/sdei/sdei_private.h @@ -22,7 +22,7 @@ #include <services/sdei.h> #include <setjmp.h> -#ifdef AARCH32 +#ifndef __aarch64__ # error SDEI is implemented only for AArch64 systems #endif diff --git a/services/std_svc/spm/spm_buffers.c b/services/std_svc/spm/spm_buffers.c index 3e0c9496..79398ba1 100644 --- a/services/std_svc/spm/spm_buffers.c +++ b/services/std_svc/spm/spm_buffers.c @@ -38,6 +38,8 @@ int spm_response_add(uint16_t client_id, uint16_t handle, uint32_t token, struct sprt_response *resp = &(responses[i]); if ((resp->is_valid == 1) && (resp->token == token)) { + spin_unlock(&responses_lock); + return -1; } } diff --git a/services/std_svc/spm/spm_private.h b/services/std_svc/spm/spm_private.h index 740fee58..efc91cb4 100644 --- a/services/std_svc/spm/spm_private.h +++ b/services/std_svc/spm/spm_private.h @@ -32,7 +32,7 @@ /* Value returned by spm_sp_synchronous_entry() when a partition is preempted */ #define SPM_SECURE_PARTITION_PREEMPTED U(0x1234) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -114,6 +114,6 @@ int spm_response_add(uint16_t client_id, uint16_t handle, uint32_t token, int spm_response_get(uint16_t client_id, uint16_t handle, uint32_t token, u_register_t *x1, u_register_t *x2, u_register_t *x3); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* SPM_PRIVATE_H */ diff --git a/services/std_svc/spm_mm/spm_private.h b/services/std_svc/spm_mm/spm_private.h index 8e94a282..ba94a4d0 100644 --- a/services/std_svc/spm_mm/spm_private.h +++ b/services/std_svc/spm_mm/spm_private.h @@ -29,7 +29,7 @@ #define SP_C_RT_CTX_SIZE 0x60 #define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <stdint.h> @@ -66,6 +66,6 @@ int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx, u_register_t pages_count, u_register_t smc_attributes); -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* SPM_PRIVATE_H */ |