diff options
| -rw-r--r-- | include/drivers/arm/gic_v2.h | 35 | ||||
| -rw-r--r-- | include/plat/arm/common/arm_def.h | 34 | ||||
| -rw-r--r-- | include/plat/arm/css/common/css_def.h | 23 | ||||
| -rw-r--r-- | plat/arm/board/fvp/include/platform_def.h | 9 | ||||
| -rw-r--r-- | plat/arm/board/juno/include/platform_def.h | 38 | ||||
| -rw-r--r-- | plat/arm/common/arm_gicv2.c | 10 | ||||
| -rw-r--r-- | plat/arm/common/arm_gicv3.c | 18 |
7 files changed, 92 insertions, 75 deletions
diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h index 3a3d7aaa..258b8981 100644 --- a/include/drivers/arm/gic_v2.h +++ b/include/drivers/arm/gic_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,9 @@ #ifndef __GIC_V2_H__ #define __GIC_V2_H__ +/* The macros required here are additional to those in gic_common.h. */ +#include <gic_common.h> + /****************************************************************************** * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h * and for GICv3 systems, use the driver in gicv3.h. @@ -19,50 +22,20 @@ #define MAX_PPIS U(14) #define MAX_SGIS U(16) -#define MIN_SGI_ID U(0) -#define MIN_PPI_ID U(16) -#define MIN_SPI_ID U(32) #define GRP0 U(0) #define GRP1 U(1) -#define GIC_PRI_MASK U(0xff) -#define GIC_HIGHEST_SEC_PRIORITY U(0) -#define GIC_LOWEST_SEC_PRIORITY U(127) -#define GIC_HIGHEST_NS_PRIORITY U(128) -#define GIC_LOWEST_NS_PRIORITY U(254) /* 255 would disable an interrupt */ -#define GIC_SPURIOUS_INTERRUPT U(1023) #define GIC_TARGET_CPU_MASK U(0xff) #define ENABLE_GRP0 (U(1) << 0) #define ENABLE_GRP1 (U(1) << 1) /* Distributor interface definitions */ -#define GICD_CTLR U(0x0) -#define GICD_TYPER U(0x4) -#define GICD_IGROUPR U(0x80) -#define GICD_ISENABLER U(0x100) -#define GICD_ICENABLER U(0x180) -#define GICD_ISPENDR U(0x200) -#define GICD_ICPENDR U(0x280) -#define GICD_ISACTIVER U(0x300) -#define GICD_ICACTIVER U(0x380) -#define GICD_IPRIORITYR U(0x400) #define GICD_ITARGETSR U(0x800) -#define GICD_ICFGR U(0xC00) #define GICD_SGIR U(0xF00) #define GICD_CPENDSGIR U(0xF10) #define GICD_SPENDSGIR U(0xF20) -#define IGROUPR_SHIFT U(5) -#define ISENABLER_SHIFT U(5) -#define ICENABLER_SHIFT ISENABLER_SHIFT -#define ISPENDR_SHIFT U(5) -#define ICPENDR_SHIFT ISPENDR_SHIFT -#define ISACTIVER_SHIFT U(5) -#define ICACTIVER_SHIFT ISACTIVER_SHIFT -#define IPRIORITYR_SHIFT U(2) -#define ITARGETSR_SHIFT U(2) -#define ICFGR_SHIFT U(4) #define CPENDSGIR_SHIFT U(2) #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index dbf102b8..c84fabd9 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -8,6 +8,8 @@ #include <arch.h> #include <common_def.h> +#include <gic_common.h> +#include <interrupt_props.h> #include <platform_def.h> #include <tbbr_img_def.h> #include <utils_def.h> @@ -152,9 +154,8 @@ #define ARM_IRQ_SEC_SGI_7 15 /* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. + * List of secure interrupts are deprecated, but are retained only to support + * legacy configurations. */ #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ ARM_IRQ_SEC_SGI_1, \ @@ -167,6 +168,33 @@ #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ ARM_IRQ_SEC_SGI_6 +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE) + #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ ARM_SHARED_RAM_BASE, \ ARM_SHARED_RAM_SIZE, \ diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index ac0769c3..a2c0b4e8 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -8,6 +8,8 @@ #define __CSS_DEF_H__ #include <arm_def.h> +#include <gic_common.h> +#include <interrupt_props.h> #include <tzc400.h> /************************************************************************* @@ -41,14 +43,21 @@ #define MHU_CPU_INTR_S_SET_OFFSET 0x308 /* - * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a - * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. + * Define a list of Group 1 Secure interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the interrupts will be treated as + * Group 0 interrupts. */ -#define CSS_G1S_IRQS CSS_IRQ_MHU, \ - CSS_IRQ_GPU_SMMU_0, \ - CSS_IRQ_TZC, \ - CSS_IRQ_TZ_WDOG, \ - CSS_IRQ_SEC_SYS_TIMER +#define CSS_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) #if CSS_USE_SCMI_SDS_DRIVER /* Memory region for shared data storage */ diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index e4f94259..e9535803 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -136,4 +136,13 @@ #define PLAT_ARM_G0_IRQS ARM_G0_IRQS +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 3c44a1e9..395d1fb6 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -193,23 +193,27 @@ */ #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 -/* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ - ARM_G1S_IRQS, \ - JUNO_IRQ_DMA_SMMU, \ - JUNO_IRQ_HDLCD0_SMMU, \ - JUNO_IRQ_HDLCD1_SMMU, \ - JUNO_IRQ_USB_SMMU, \ - JUNO_IRQ_THIN_LINKS_SMMU, \ - JUNO_IRQ_SEC_I2C, \ - JUNO_IRQ_GPU_SMMU_1, \ - JUNO_IRQ_ETR_SMMU - -#define PLAT_ARM_G0_IRQS ARM_G0_IRQS +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + CSS_G1S_IRQ_PROPS(grp), \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) /* * Required ARM CSS SoC based platform porting definitions diff --git a/plat/arm/common/arm_gicv2.c b/plat/arm/common/arm_gicv2.c index 6dd847b2..aac0248c 100644 --- a/plat/arm/common/arm_gicv2.c +++ b/plat/arm/common/arm_gicv2.c @@ -23,9 +23,9 @@ * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 * interrupts. *****************************************************************************/ -static const unsigned int g0_interrupt_array[] = { - PLAT_ARM_G1S_IRQS, - PLAT_ARM_G0_IRQS +static const interrupt_prop_t arm_interrupt_props[] = { + PLAT_ARM_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), + PLAT_ARM_G0_IRQ_PROPS(GICV2_INTR_GROUP0) }; static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; @@ -33,8 +33,8 @@ static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; static const gicv2_driver_data_t arm_gic_data = { .gicd_base = PLAT_ARM_GICD_BASE, .gicc_base = PLAT_ARM_GICC_BASE, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, + .interrupt_props = arm_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), .target_masks = target_mask_array, .target_masks_num = ARRAY_SIZE(target_mask_array), }; diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index c9bba095..cec6a9df 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -6,6 +6,7 @@ #include <arm_def.h> #include <gicv3.h> +#include <interrupt_props.h> #include <plat_arm.h> #include <platform.h> #include <platform_def.h> @@ -25,14 +26,9 @@ /* The GICv3 driver only needs to be initialized in EL3 */ static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; -/* Array of Group1 secure interrupts to be configured by the gic driver */ -static const unsigned int g1s_interrupt_array[] = { - PLAT_ARM_G1S_IRQS -}; - -/* Array of Group0 interrupts to be configured by the gic driver */ -static const unsigned int g0_interrupt_array[] = { - PLAT_ARM_G0_IRQS +static const interrupt_prop_t arm_interrupt_props[] = { + PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), + PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0) }; /* @@ -58,10 +54,8 @@ static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr) const gicv3_driver_data_t arm_gic_data = { .gicd_base = PLAT_ARM_GICD_BASE, .gicr_base = PLAT_ARM_GICR_BASE, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, - .g1s_interrupt_array = g1s_interrupt_array, + .interrupt_props = arm_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), .rdistif_num = PLATFORM_CORE_COUNT, .rdistif_base_addrs = rdistif_base_addrs, .mpidr_to_core_pos = arm_gicv3_mpidr_hash |