diff options
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 16 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a57.h | 1 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a72.h | 1 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 1 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a72.h | 1 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cortex_a57.S | 32 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cortex_a72.S | 56 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 31 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a72.S | 57 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 16 | ||||
| -rw-r--r-- | plat/arm/board/juno/platform.mk | 12 |
11 files changed, 216 insertions, 8 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 5738927c..f74b4593 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -21,6 +21,7 @@ by ARM: - `Cortex-A53 MPCore Software Developers Errata Notice`_ - `Cortex-A57 MPCore Software Developers Errata Notice`_ +- `Cortex-A72 MPCore Software Developers Errata Notice`_ The errata workarounds are implemented for a particular revision or a set of processor revisions. This is checked by the reset handler at runtime. Each @@ -30,7 +31,8 @@ errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor nam is for example ``A57`` for the ``Cortex_A57`` CPU. Refer to the section *CPU errata status reporting* in -`Firmware Design guide`_ for information on to write errata workaround functions. +`Firmware Design guide`_ for information on how to write errata workaround +functions. All workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the @@ -98,6 +100,15 @@ For Cortex-A57, following errata build flags are defined : - ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. +- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p3 of the CPU. + + +For Cortex-A72, following errata build flags are defined : + +- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 + CPU. This needs to be enabled only for revision <= r0p3 of the CPU. + CPU Specific optimizations -------------------------- @@ -131,7 +142,8 @@ architecture that can be enabled by the platform as desired. *Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.* -.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html +.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf +.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html .. _Firmware Design guide: firmware-design.rst .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index d3ae5b92..3fac9c7b 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -49,6 +49,7 @@ #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) #define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) #define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27) #define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25) #define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index 306253d5..f7da1f01 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -34,6 +34,7 @@ #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) /******************************************************************************* * L2 Control register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 070108d5..6c45c066 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -49,6 +49,7 @@ #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index aed714c6..6fbb7076 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -34,6 +34,7 @@ #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) /******************************************************************************* * L2 Control register specific definitions. diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S index e4aad790..b5189e77 100644 --- a/lib/cpus/aarch32/cortex_a57.S +++ b/lib/cpus/aarch32/cortex_a57.S @@ -306,6 +306,32 @@ func check_errata_833471 b cpu_rev_var_ls endfunc check_errata_833471 + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #859972. + * This applies only to revision <= r1p3 of Cortex A57. + * Inputs: + * r0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: r0-r3 + * --------------------------------------------------- + */ +func errata_a57_859972_wa + mov r2, lr + bl check_errata_859972 + mov lr, r2 + cmp r0, #ERRATA_NOT_APPLIES + beq 1f + ldcopr16 r0, r1, CORTEX_A57_CPUACTLR + orr64_imm r1, r1, CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH + stcopr16 r0, r1, CORTEX_A57_CPUACTLR +1: + bx lr +endfunc errata_a57_859972_wa + +func check_errata_859972 + mov r1, #0x13 + b cpu_rev_var_ls +endfunc check_errata_859972 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Shall clobber: r0-r6 @@ -356,6 +382,11 @@ func cortex_a57_reset_func bl errata_a57_833471_wa #endif +#if ERRATA_A57_859972 + mov r0, r4 + bl errata_a57_859972_wa +#endif + /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- @@ -487,6 +518,7 @@ func cortex_a57_errata_report report_errata ERRATA_A57_828024, cortex_a57, 828024 report_errata ERRATA_A57_829520, cortex_a57, 829520 report_errata ERRATA_A57_833471, cortex_a57, 833471 + report_errata ERRATA_A57_859972, cortex_a57, 859972 pop {r12, lr} bx lr diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S index d164cfd2..69cc2ea5 100644 --- a/lib/cpus/aarch32/cortex_a72.S +++ b/lib/cpus/aarch32/cortex_a72.S @@ -61,11 +61,46 @@ func cortex_a72_disable_ext_debug bx lr endfunc cortex_a72_disable_ext_debug + /* --------------------------------------------------- + * Errata Workaround for Cortex A72 Errata #859971. + * This applies only to revision <= r0p3 of Cortex A72. + * Inputs: + * r0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: r0-r3 + * --------------------------------------------------- + */ +func errata_a72_859971_wa + mov r2,lr + bl check_errata_859971 + mov lr, r2 + cmp r0, #ERRATA_NOT_APPLIES + beq 1f + ldcopr16 r0, r1, CORTEX_A72_CPUACTLR + orr64_imm r1, r1, CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH + stcopr16 r0, r1, CORTEX_A72_CPUACTLR +1: + bx lr +endfunc errata_a72_859971_wa + +func check_errata_859971 + mov r1, #0x03 + b cpu_rev_var_ls +endfunc check_errata_859971 + + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A72. * ------------------------------------------------- */ func cortex_a72_reset_func + mov r5, lr + bl cpu_get_rev_var + mov r4, r0 + +#if ERRATA_A72_859971 + mov r0, r4 + bl errata_a72_859971_wa +#endif /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- @@ -186,6 +221,27 @@ func cortex_a72_cluster_pwr_dwn b cortex_a72_disable_ext_debug endfunc cortex_a72_cluster_pwr_dwn +#if REPORT_ERRATA +/* + * Errata printing function for Cortex A72. Must follow AAPCS. + */ +func cortex_a72_errata_report + push {r12, lr} + + bl cpu_get_rev_var + mov r4, r0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_A72_859971, cortex_a72, 859971 + + pop {r12, lr} + bx lr +endfunc cortex_a72_errata_report +#endif + declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ cortex_a72_reset_func, \ cortex_a72_core_pwr_dwn, \ diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 289d0d4e..a720e984 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -304,6 +304,30 @@ func check_errata_833471 b cpu_rev_var_ls endfunc check_errata_833471 + /* -------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #859972. + * This applies only to revision <= r1p3 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: + * -------------------------------------------------- + */ +func errata_a57_859972_wa + mov x17, x30 + bl check_errata_859972 + cbz x0, 1f + mrs x1, CORTEX_A57_CPUACTLR_EL1 + orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH + msr CORTEX_A57_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_a57_859972_wa + +func check_errata_859972 + mov x1, #0x13 + b cpu_rev_var_ls +endfunc check_errata_859972 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Shall clobber: x0-x19 @@ -354,6 +378,11 @@ func cortex_a57_reset_func bl errata_a57_833471_wa #endif +#if ERRATA_A57_859972 + mov x0, x18 + bl errata_a57_859972_wa +#endif + /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- @@ -483,6 +512,8 @@ func cortex_a57_errata_report report_errata ERRATA_A57_828024, cortex_a57, 828024 report_errata ERRATA_A57_829520, cortex_a57, 829520 report_errata ERRATA_A57_833471, cortex_a57, 833471 + report_errata ERRATA_A57_859972, cortex_a57, 859972 + ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S index 5de2bf0f..b0341256 100644 --- a/lib/cpus/aarch64/cortex_a72.S +++ b/lib/cpus/aarch64/cortex_a72.S @@ -73,20 +73,52 @@ func cortex_a72_disable_ext_debug ret endfunc cortex_a72_disable_ext_debug + /* -------------------------------------------------- + * Errata Workaround for Cortex A72 Errata #859971. + * This applies only to revision <= r0p3 of Cortex A72. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: + * -------------------------------------------------- + */ +func errata_a72_859971_wa + mov x17,x30 + bl check_errata_859971 + cbz x0, 1f + mrs x1, CORTEX_A72_CPUACTLR_EL1 + orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH + msr CORTEX_A72_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_a72_859971_wa + +func check_errata_859971 + mov x1, #0x03 + b cpu_rev_var_ls +endfunc check_errata_859971 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A72. * ------------------------------------------------- */ func cortex_a72_reset_func + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_A72_859971 + mov x0, x18 + bl errata_a72_859971_wa +#endif /* --------------------------------------------- - * As a bare minimum enable the SMP bit. + * Enable the SMP bit. * --------------------------------------------- */ mrs x0, CORTEX_A72_ECTLR_EL1 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT msr CORTEX_A72_ECTLR_EL1, x0 isb - ret + ret x19 endfunc cortex_a72_reset_func /* ---------------------------------------------------- @@ -196,6 +228,27 @@ func cortex_a72_cluster_pwr_dwn b cortex_a72_disable_ext_debug endfunc cortex_a72_cluster_pwr_dwn +#if REPORT_ERRATA +/* + * Errata printing function for Cortex A72. Must follow AAPCS. + */ +func cortex_a72_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_A72_859971, cortex_a72, 859971 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_a72_errata_report +#endif + /* --------------------------------------------- * This function provides cortex_a72 specific * register information for crash reporting. diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index ad329719..31adfb42 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -91,6 +91,14 @@ ERRATA_A57_829520 ?=0 # only to revision <= r1p2 of the Cortex A57 cpu. ERRATA_A57_833471 ?=0 +# Flag to apply erratum 855972 workaround during reset. This erratum applies +# only to revision <= r1p3 of the Cortex A57 cpu. +ERRATA_A57_859972 ?=0 + +# Flag to apply erratum 855971 workaround during reset. This erratum applies +# only to revision <= r0p3 of the Cortex A72 cpu. +ERRATA_A72_859971 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -143,6 +151,14 @@ $(eval $(call add_define,ERRATA_A57_829520)) $(eval $(call assert_boolean,ERRATA_A57_833471)) $(eval $(call add_define,ERRATA_A57_833471)) +# Process ERRATA_A57_859972 flag +$(eval $(call assert_boolean,ERRATA_A57_859972)) +$(eval $(call add_define,ERRATA_A57_859972)) + +# Process ERRATA_A72_859971 flag +$(eval $(call assert_boolean,ERRATA_A72_859971)) +$(eval $(call add_define,ERRATA_A72_859971)) + # Errata build flags ifneq (${ERRATA_A53_843419},0) TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419 diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index b972d26a..79916cda 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -55,10 +55,14 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ ${JUNO_SECURITY_SOURCES} endif -# Enable workarounds for selected Cortex-A53 and A57 errata. +# Errata workarounds for Cortex-A53: +ERRATA_A53_826319 := 1 ERRATA_A53_835769 := 1 +ERRATA_A53_836870 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 + +# Errata workarounds for Cortex-A57: ERRATA_A57_806969 := 0 ERRATA_A57_813419 := 1 ERRATA_A57_813420 := 1 @@ -67,10 +71,10 @@ ERRATA_A57_826977 := 1 ERRATA_A57_828024 := 1 ERRATA_A57_829520 := 1 ERRATA_A57_833471 := 1 +ERRATA_A57_859972 := 0 -# Enable workarounds for selected Cortex-A53 errata. -ERRATA_A53_826319 := 1 -ERRATA_A53_836870 := 1 +# Errata workarounds for Cortex-A72: +ERRATA_A72_859971 := 0 # Enable option to skip L1 data cache flush during the Cortex-A57 cluster # power down sequence |