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-rw-r--r--docs/plat/hikey.rst18
-rw-r--r--docs/plat/hikey960.rst22
-rw-r--r--plat/hisilicon/hikey/aarch64/hikey_common.c14
-rw-r--r--plat/hisilicon/hikey/hikey_bl2_setup.c35
-rw-r--r--plat/hisilicon/hikey/hikey_def.h21
-rw-r--r--plat/hisilicon/hikey/hikey_io_storage.c9
-rw-r--r--plat/hisilicon/hikey/include/platform_def.h40
-rw-r--r--plat/hisilicon/hikey/platform.mk13
-rw-r--r--plat/hisilicon/hikey960/aarch64/hikey960_common.c14
-rw-r--r--plat/hisilicon/hikey960/hikey960_bl2_setup.c35
-rw-r--r--plat/hisilicon/hikey960/hikey960_def.h19
-rw-r--r--plat/hisilicon/hikey960/hikey960_io_storage.c9
-rw-r--r--plat/hisilicon/hikey960/include/platform_def.h25
-rw-r--r--plat/hisilicon/hikey960/platform.mk17
14 files changed, 267 insertions, 24 deletions
diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst
index 027e14c7..125941f8 100644
--- a/docs/plat/hikey.rst
+++ b/docs/plat/hikey.rst
@@ -14,6 +14,9 @@ Code Locations
- ARM Trusted Firmware:
`link <https://github.com/ARM-software/arm-trusted-firmware>`__
+- OP-TEE
+ `link <https://github.com/OP-TEE/optee_os>`__
+
- edk2:
`link <https://github.com/96boards-hikey/edk2/tree/testing/hikey960_v2.5>`__
@@ -24,7 +27,7 @@ Code Locations
`link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__
- uefi-tools:
- `link <https://github.com/96boards-hikey/uefi-tools/tree/testing/hikey960_v1>`__
+ `link <https://git.linaro.org/uefi/uefi-tools.git>`__
- atf-fastboot:
`link <https://github.com/96boards-hikey/atf-fastboot/tree/master>`__
@@ -70,13 +73,11 @@ Build Procedure
FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]')
cd ${EDK2_DIR}
# Build UEFI & ARM Trust Firmware
- ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware hikey
+ ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey
# Generate l-loader.bin
cd ${BUILD_PATH}/l-loader
ln -sf ${EDK2_OUTPUT_DIR}/FV/bl1.bin
- ln -sf ${EDK2_OUTPUT_DIR}/FV/fip.bin
ln -sf ${BUILD_PATH}/atf-fastboot/build/hikey/${FASTBOOT_BUILD_OPTION}/bl1.bin fastboot.bin
- python gen_loader.py -o l-loader.bin --img_bl1=bl1.bin --img_ns_bl1u=BL33_AP_UEFI.fd
arm-linux-gnueabihf-gcc -c -o start.o start.S
arm-linux-gnueabihf-ld -Bstatic -Tl-loader.lds -Ttext 0xf9800800 start.o -o loader
arm-linux-gnueabihf-objcopy -O binary loader temp
@@ -86,7 +87,7 @@ Build Procedure
.. code:: shell
- $PTABLE=aosp-4g SECTOR_SIZE=512 bash -x generate_ptable.sh
+ PTABLE=aosp-4g SECTOR_SIZE=512 bash -x generate_ptable.sh
Setup Console
-------------
@@ -110,6 +111,13 @@ Setup Console
2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
+- Start ser2net
+
+ .. code:: shell
+
+ $sudo killall ser2net
+ $sudo ser2net -u
+
- Open the console.
.. code:: shell
diff --git a/docs/plat/hikey960.rst b/docs/plat/hikey960.rst
index c28ef3ae..cd1880e1 100644
--- a/docs/plat/hikey960.rst
+++ b/docs/plat/hikey960.rst
@@ -14,6 +14,9 @@ Code Locations
- ARM Trusted Firmware:
`link <https://github.com/ARM-software/arm-trusted-firmware>`__
+- OP-TEE:
+ `link <https://github.com/OP-TEE/optee_os>`__
+
- edk2:
`link <https://github.com/96boards-hikey/edk2/tree/testing/hikey960_v2.5>`__
@@ -24,7 +27,7 @@ Code Locations
`link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__
- uefi-tools:
- `link <https://github.com/96boards-hikey/uefi-tools/tree/hikey960_v1>`__
+ `link <https://git.linaro.org/uefi/uefi-tools.git>`__
Build Procedure
---------------
@@ -56,26 +59,26 @@ Build Procedure
.. code:: shell
BUILD_OPTION=DEBUG
- export AARCH64_TOOLCHAIN=GCC48
+ export AARCH64_TOOLCHAIN=GCC5
export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools
export EDK2_DIR=${BUILD_PATH}/edk2
EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey960/${BUILD_OPTION}_${AARCH64_TOOLCHAIN}
cd ${EDK2_DIR}
# Build UEFI & ARM Trust Firmware
- ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware hikey960
+ ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey960
# Generate l-loader.bin
cd ${BUILD_PATH}/l-loader
ln -sf ${EDK2_OUTPUT_DIR}/FV/bl1.bin
ln -sf ${EDK2_OUTPUT_DIR}/FV/fip.bin
ln -sf ${EDK2_OUTPUT_DIR}/FV/BL33_AP_UEFI.fd
- python gen_loader.py -o l-loader.bin --img_bl1=bl1.bin --img_ns_bl1u=BL33_AP_UEFI.fd
+ python gen_loader_hikey960.py -o l-loader.bin --img_bl1=bl1.bin --img_ns_bl1u=BL33_AP_UEFI.fd
- Generate partition table.
*Make sure that you're using the sgdisk in the l-loader directory.*
.. code:: shell
- $PTABLE=aosp-32g SECTOR_SIZE=4096 SGDISK=./sgdisk bash -x generate_ptable.sh
+ PTABLE=aosp-32g SECTOR_SIZE=4096 SGDISK=./sgdisk bash -x generate_ptable.sh
Setup Console
-------------
@@ -99,6 +102,13 @@ Setup Console
2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
+- Start ser2net
+
+ .. code:: shell
+
+ $sudo killall ser2net
+ $sudo ser2net -u
+
- Open the console.
.. code:: shell
@@ -126,7 +136,7 @@ Boot UEFI in recovery mode
$vi config
# The content of config file
- ./sec_user_xloader.img 0x00020000
+ ./sec_usb_xloader.img 0x00020000
./sec_uce_boot.img 0x6A908000
./l-loader.bin 0x1AC00000
diff --git a/plat/hisilicon/hikey/aarch64/hikey_common.c b/plat/hisilicon/hikey/aarch64/hikey_common.c
index d8a68cf6..20a95bf7 100644
--- a/plat/hisilicon/hikey/aarch64/hikey_common.c
+++ b/plat/hisilicon/hikey/aarch64/hikey_common.c
@@ -24,6 +24,10 @@
DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
+#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
+ TSP_SEC_MEM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
#define MAP_ROM_PARAM MAP_REGION_FLAT(XG2RAM0_BASE, \
BL1_XG2RAM0_OFFSET, \
MT_DEVICE | MT_RO | MT_SECURE)
@@ -59,6 +63,7 @@ static const mmap_region_t hikey_mmap[] = {
static const mmap_region_t hikey_mmap[] = {
MAP_DDR,
MAP_DEVICE,
+ MAP_TSP_MEM,
{0}
};
#endif
@@ -67,6 +72,15 @@ static const mmap_region_t hikey_mmap[] = {
static const mmap_region_t hikey_mmap[] = {
MAP_DEVICE,
MAP_SRAM,
+ MAP_TSP_MEM,
+ {0}
+};
+#endif
+
+#if IMAGE_BL32
+static const mmap_region_t hikey_mmap[] = {
+ MAP_DEVICE,
+ MAP_DDR,
{0}
};
#endif
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index 9e9909b9..13dc6c9b 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -144,6 +144,41 @@ void bl2_plat_set_bl31_ep_info(image_info_t *image,
DISABLE_ALL_EXCEPTIONS);
}
+/*******************************************************************************
+ * Before calling this function BL32 is loaded in memory and its entrypoint
+ * is set by load_image. This is a placeholder for the platform to change
+ * the entrypoint of BL32 and set SPSR and security state.
+ * On Hikey we only set the security state of the entrypoint
+ ******************************************************************************/
+#ifdef BL32_BASE
+void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
+ entry_point_info_t *bl32_ep_info)
+{
+ SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
+ /*
+ * The Secure Payload Dispatcher service is responsible for
+ * setting the SPSR prior to entry into the BL32 image.
+ */
+ bl32_ep_info->spsr = 0;
+}
+
+/*******************************************************************************
+ * Populate the extents of memory available for loading BL32
+ ******************************************************************************/
+void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
+{
+ /*
+ * Populate the extents of memory available for loading BL32.
+ */
+ bl32_meminfo->total_base = BL32_BASE;
+ bl32_meminfo->free_base = BL32_BASE;
+ bl32_meminfo->total_size =
+ (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
+ bl32_meminfo->free_size =
+ (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
+}
+#endif /* BL32_BASE */
+
void bl2_plat_set_bl33_ep_info(image_info_t *image,
entry_point_info_t *bl33_ep_info)
{
diff --git a/plat/hisilicon/hikey/hikey_def.h b/plat/hisilicon/hikey/hikey_def.h
index 28ff553d..bbad10f7 100644
--- a/plat/hisilicon/hikey/hikey_def.h
+++ b/plat/hisilicon/hikey/hikey_def.h
@@ -12,7 +12,7 @@
/* Always assume DDR is 1GB size. */
#define DDR_BASE 0x0
-#define DDR_SIZE 0x80000000
+#define DDR_SIZE 0x40000000
#define DEVICE_BASE 0xF4000000
#define DEVICE_SIZE 0x05800000
@@ -20,6 +20,25 @@
#define XG2RAM0_BASE 0xF9800000
#define XG2RAM0_SIZE 0x00400000
+/* Memory location options for TSP */
+#define HIKEY_SRAM_ID 0
+#define HIKEY_DRAM_ID 1
+
+/*
+ * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
+ * regions
+ * - Secure DDR (default is the top 16MB) used by OP-TEE
+ * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
+ * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
+ * - Non-secure DDR (8MB) reserved for OP-TEE's future use
+ */
+#define DDR_SEC_SIZE 0x01000000
+#define DDR_SEC_BASE (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE)
+
+#define DDR_SDP_SIZE 0x00400000
+#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
+ DDR_SDP_SIZE)
+
#define SRAM_BASE 0xFFF80000
#define SRAM_SIZE 0x00012000
diff --git a/plat/hisilicon/hikey/hikey_io_storage.c b/plat/hisilicon/hikey/hikey_io_storage.c
index 4ca1846f..c61ec2c1 100644
--- a/plat/hisilicon/hikey/hikey_io_storage.c
+++ b/plat/hisilicon/hikey/hikey_io_storage.c
@@ -73,6 +73,10 @@ static const io_uuid_spec_t bl31_uuid_spec = {
.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
};
+static const io_uuid_spec_t bl32_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32,
+};
+
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
@@ -102,6 +106,11 @@ static const struct plat_io_policy policies[] = {
(uintptr_t)&bl31_uuid_spec,
check_fip
},
+ [BL32_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_uuid_spec,
+ check_fip
+ },
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl33_uuid_spec,
diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h
index a91a9b06..af152322 100644
--- a/plat/hisilicon/hikey/include/platform_def.h
+++ b/plat/hisilicon/hikey/include/platform_def.h
@@ -11,13 +11,6 @@
#include "../hikey_def.h"
/*
- * Platform binary types for linking
- */
-#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH aarch64
-
-
-/*
* Generic platform constants
*/
@@ -104,6 +97,33 @@
#define BL31_BASE BL2_LIMIT
#define BL31_LIMIT 0xF9898000
+/*
+ * BL3-2 specific defines.
+ */
+
+/*
+ * The TSP currently executes from TZC secured area of DRAM or SRAM.
+ */
+#define BL32_SRAM_BASE BL31_LIMIT
+#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
+
+#define BL32_DRAM_BASE DDR_SEC_BASE
+#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
+
+#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
+#define BL32_BASE BL32_DRAM_BASE
+#define BL32_LIMIT BL32_DRAM_LIMIT
+#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
+#define BL32_BASE BL32_SRAM_BASE
+#define BL32_LIMIT BL32_SRAM_LIMIT
+#else
+#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
+#endif
+
#define NS_BL1U_BASE (BL2_BASE)
#define NS_BL1U_SIZE (0x00010000)
#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
@@ -113,10 +133,14 @@
*/
#define ADDR_SPACE_SIZE (1ull << 32)
-#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31
+#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL32
#define MAX_XLAT_TABLES 3
#endif
+#if IMAGE_BL31
+#define MAX_XLAT_TABLES 4
+#endif
+
#define MAX_MMAP_REGIONS 16
#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index 08a3047f..8da39988 100644
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk
@@ -4,6 +4,17 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+# On Hikey, the TSP can execute from TZC secure area in DRAM (default)
+# or SRAM.
+HIKEY_TSP_RAM_LOCATION := dram
+ifeq (${HIKEY_TSP_RAM_LOCATION}, dram)
+ HIKEY_TSP_RAM_LOCATION_ID = HIKEY_DRAM_ID
+else ifeq (${HIKEY_TSP_RAM_LOCATION}, sram)
+ HIKEY_TSP_RAM_LOCATION_ID := HIKEY_SRAM_ID
+else
+ $(error "Currently unsupported HIKEY_TSP_RAM_LOCATION value")
+endif
+
CONSOLE_BASE := PL011_UART3_BASE
CRASH_CONSOLE_BASE := PL011_UART3_BASE
PLAT_PARTITION_MAX_ENTRIES := 12
@@ -12,11 +23,11 @@ COLD_BOOT_SINGLE_CPU := 1
PROGRAMMABLE_RESET_ADDRESS := 1
# Process flags
+$(eval $(call add_define,HIKEY_TSP_RAM_LOCATION_ID))
$(eval $(call add_define,CONSOLE_BASE))
$(eval $(call add_define,CRASH_CONSOLE_BASE))
$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
$(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
-$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
ENABLE_PLAT_COMPAT := 0
diff --git a/plat/hisilicon/hikey960/aarch64/hikey960_common.c b/plat/hisilicon/hikey960/aarch64/hikey960_common.c
index d7894b3e..7068fb68 100644
--- a/plat/hisilicon/hikey960/aarch64/hikey960_common.c
+++ b/plat/hisilicon/hikey960/aarch64/hikey960_common.c
@@ -37,6 +37,10 @@
HIKEY960_UFS_DESC_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
+#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
+ TSP_SEC_MEM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
/*
* Table of regions for different BL stages to map using the MMU.
* This doesn't include Trusted RAM as the 'mem_layout' argument passed to
@@ -56,6 +60,7 @@ static const mmap_region_t hikey960_mmap[] = {
static const mmap_region_t hikey960_mmap[] = {
MAP_DDR,
MAP_DEVICE,
+ MAP_TSP_MEM,
{0}
};
#endif
@@ -63,6 +68,15 @@ static const mmap_region_t hikey960_mmap[] = {
#if IMAGE_BL31
static const mmap_region_t hikey960_mmap[] = {
MAP_DEVICE,
+ MAP_TSP_MEM,
+ {0}
+};
+#endif
+
+#if IMAGE_BL32
+static const mmap_region_t hikey960_mmap[] = {
+ MAP_DEVICE,
+ MAP_DDR,
{0}
};
#endif
diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
index e2257937..de676a71 100644
--- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
@@ -177,6 +177,41 @@ void bl2_plat_set_bl31_ep_info(image_info_t *image,
DISABLE_ALL_EXCEPTIONS);
}
+/*******************************************************************************
+ * Before calling this function BL32 is loaded in memory and its entrypoint
+ * is set by load_image. This is a placeholder for the platform to change
+ * the entrypoint of BL32 and set SPSR and security state.
+ * On Hikey we only set the security state of the entrypoint
+ ******************************************************************************/
+#ifdef BL32_BASE
+void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
+ entry_point_info_t *bl32_ep_info)
+{
+ SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
+ /*
+ * The Secure Payload Dispatcher service is responsible for
+ * setting the SPSR prior to entry into the BL32 image.
+ */
+ bl32_ep_info->spsr = 0;
+}
+
+/*******************************************************************************
+ * Populate the extents of memory available for loading BL32
+ ******************************************************************************/
+void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
+{
+ /*
+ * Populate the extents of memory available for loading BL32.
+ */
+ bl32_meminfo->total_base = BL32_BASE;
+ bl32_meminfo->free_base = BL32_BASE;
+ bl32_meminfo->total_size =
+ (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
+ bl32_meminfo->free_size =
+ (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
+}
+#endif /* BL32_BASE */
+
void bl2_plat_set_bl33_ep_info(image_info_t *image,
entry_point_info_t *bl33_ep_info)
{
diff --git a/plat/hisilicon/hikey960/hikey960_def.h b/plat/hisilicon/hikey960/hikey960_def.h
index e713e2e0..fc46d71a 100644
--- a/plat/hisilicon/hikey960/hikey960_def.h
+++ b/plat/hisilicon/hikey960/hikey960_def.h
@@ -16,6 +16,25 @@
#define DEVICE_BASE 0xE0000000
#define DEVICE_SIZE 0x20000000
+/* Memory location options for TSP */
+#define HIKEY960_SRAM_ID 0
+#define HIKEY960_DRAM_ID 1
+
+/*
+ * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
+ * regions:
+ * - Secure DDR (default is the top 16MB) used by OP-TEE
+ * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
+ * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
+ * - Non-secure DDR (8MB) reserved for OP-TEE's future use
+ */
+#define DDR_SEC_SIZE 0x01000000
+#define DDR_SEC_BASE 0x3F000000
+
+#define DDR_SDP_SIZE 0x00400000
+#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
+ DDR_SDP_SIZE)
+
/*
* PL011 related constants
*/
diff --git a/plat/hisilicon/hikey960/hikey960_io_storage.c b/plat/hisilicon/hikey960/hikey960_io_storage.c
index de54e886..57d97e59 100644
--- a/plat/hisilicon/hikey960/hikey960_io_storage.c
+++ b/plat/hisilicon/hikey960/hikey960_io_storage.c
@@ -69,6 +69,10 @@ static const io_uuid_spec_t bl31_uuid_spec = {
.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
};
+static const io_uuid_spec_t bl32_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32,
+};
+
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
@@ -94,6 +98,11 @@ static const struct plat_io_policy policies[] = {
(uintptr_t)&bl31_uuid_spec,
check_fip
},
+ [BL32_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_uuid_spec,
+ check_fip
+ },
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl33_uuid_spec,
diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h
index 369117b8..8bf32c33 100644
--- a/plat/hisilicon/hikey960/include/platform_def.h
+++ b/plat/hisilicon/hikey960/include/platform_def.h
@@ -63,6 +63,27 @@
#define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */
#define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */
+/*
+ * BL3-2 specific defines.
+ */
+
+/*
+ * The TSP currently executes from TZC secured area of DRAM.
+ */
+#define BL32_DRAM_BASE DDR_SEC_BASE
+#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
+
+#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
+#define BL32_BASE BL32_DRAM_BASE
+#define BL32_LIMIT BL32_DRAM_LIMIT
+#elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID)
+#error "SRAM storage of TSP payload is currently unsupported"
+#else
+#error "Currently unsupported HIKEY960_TSP_LOCATION_ID value"
+#endif
+
#define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
#define NS_BL1U_SIZE (0x00100000)
#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
@@ -70,7 +91,7 @@
#define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */
#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
-#define SCP_BL2_BASE BL31_BASE
+#define SCP_BL2_BASE BL31_BASE /* 1AC5_8000 */
#define SCP_MEM_BASE (0x89C80000)
#define SCP_MEM_SIZE (0x00040000)
@@ -80,7 +101,7 @@
*/
#define ADDR_SPACE_SIZE (1ull << 32)
-#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31
+#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 || IMAGE_BL32
#define MAX_XLAT_TABLES 3
#endif
diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk
index 145eee0e..edbce636 100644
--- a/plat/hisilicon/hikey960/platform.mk
+++ b/plat/hisilicon/hikey960/platform.mk
@@ -4,13 +4,23 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+# On Hikey960, the TSP can execute from TZC secure area in DRAM.
+HIKEY960_TSP_RAM_LOCATION := dram
+ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram)
+ HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_DRAM_ID
+else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram)
+ HIKEY960_TSP_RAM_LOCATION_ID := HIKEY960_SRAM_ID
+else
+ $(error "Currently unsupported HIKEY960_TSP_RAM_LOCATION value")
+endif
+
CRASH_CONSOLE_BASE := PL011_UART6_BASE
COLD_BOOT_SINGLE_CPU := 1
PROGRAMMABLE_RESET_ADDRESS := 1
# Process flags
+$(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID))
$(eval $(call add_define,CRASH_CONSOLE_BASE))
-$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
ENABLE_PLAT_COMPAT := 0
@@ -63,3 +73,8 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c \
plat/hisilicon/hikey960/drivers/ipc/hisi_ipc.c \
${HIKEY960_GIC_SOURCES}
+
+# Enable workarounds for selected Cortex-A53 errata.
+ERRATA_A53_836870 := 1
+ERRATA_A53_843419 := 1
+ERRATA_A53_855873 := 1
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-19 23:39:14 +0000