diff options
41 files changed, 643 insertions, 271 deletions
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index 90c06afe..89664cd0 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -34,6 +34,7 @@ #include <auth_mod.h> #include <bl1.h> #include <bl_common.h> +#include <console.h> #include <debug.h> #include <errata_report.h> #include <platform.h> @@ -166,6 +167,8 @@ void bl1_main(void) NOTICE("BL1-FWU: *******FWU Process Started*******\n"); bl1_prepare_next_image(image_id); + + console_flush(); } /******************************************************************************* diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c index 514c0053..d187f2e3 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -32,6 +32,7 @@ #include <auth_mod.h> #include <bl1.h> #include <bl_common.h> +#include <console.h> #include <debug.h> #include <platform.h> #include "bl2_private.h" @@ -69,6 +70,8 @@ void bl2_main(void) disable_mmu_icache_secure(); #endif /* AARCH32 */ + console_flush(); + /* * Run next BL image via an SMC to BL1. Information on how to pass * control to the BL32 (if present) and BL33 software images will diff --git a/bl2u/bl2u_main.c b/bl2u/bl2u_main.c index 515ddfb7..3ed5be73 100644 --- a/bl2u/bl2u_main.c +++ b/bl2u/bl2u_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,6 +34,7 @@ #include <auth_mod.h> #include <bl_common.h> #include <bl1.h> +#include <console.h> #include <debug.h> #include <platform.h> #include <platform_def.h> @@ -63,6 +64,8 @@ void bl2u_main(void) /* Perform platform setup in BL2U after loading SCP_BL2U */ bl2u_platform_setup(); + console_flush(); + /* * Indicate that BL2U is done and resume back to * normal world via an SMC to BL1. diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S index 8e603862..c6d5c6c3 100644 --- a/bl31/aarch64/crash_reporting.S +++ b/bl31/aarch64/crash_reporting.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -349,6 +349,8 @@ func do_crash_reporting /* Print some platform registers */ plat_crash_print_regs + bl plat_crash_console_flush + /* Done reporting */ no_ret plat_panic_handler endfunc do_crash_reporting diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index 85b3ea1e..c74b72b7 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ #include <assert.h> #include <bl_common.h> #include <bl31.h> +#include <console.h> #include <context_mgmt.h> #include <debug.h> #include <platform.h> @@ -129,6 +130,8 @@ void bl31_main(void) */ bl31_prepare_next_image_entry(); + console_flush(); + /* * Perform any platform specific runtime setup prior to cold boot exit * from BL31 diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S index ecf9faff..77298a12 100644 --- a/common/aarch32/debug.S +++ b/common/aarch32/debug.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -70,9 +70,12 @@ func do_panic /* Print new line */ ldr r4, =panic_end bl asm_print_str + + bl plat_crash_console_flush + 1: mov lr, r6 - b plat_panic_handler + no_ret plat_panic_handler endfunc do_panic /*********************************************************** @@ -140,6 +143,9 @@ dec_print_loop: udiv r5, r5, r6 /* Reduce divisor */ cmp r5, #0 bne dec_print_loop + + bl plat_crash_console_flush + 1: no_ret plat_panic_handler endfunc asm_assert diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S index 9dd53ca9..fb6924ea 100644 --- a/common/aarch64/debug.S +++ b/common/aarch64/debug.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -96,8 +96,9 @@ func asm_assert b.ne _assert_loop mov x4, x6 asm_print_line_dec + bl plat_crash_console_flush _assert_loop: - b _assert_loop + no_ret plat_panic_handler endfunc asm_assert #endif @@ -187,6 +188,8 @@ el3_panic: sub x4, x4, #4 bl asm_print_hex + bl plat_crash_console_flush + _panic_handler: /* Pass to plat_panic_handler the address from where el3_panic was * called, not the address of the call from el3_panic. */ diff --git a/docs/porting-guide.md b/docs/porting-guide.md index 690f307a..0189ec40 100644 --- a/docs/porting-guide.md +++ b/docs/porting-guide.md @@ -2242,6 +2242,17 @@ designated crash console. It must only use general purpose registers x1 and x2 to do its work. The parameter and the return value are in general purpose register x0. +### Function : plat_crash_console_flush + + Argument : void + Return : int + +This API is used by the crash reporting mechanism to force write of all buffered +data on the designated crash console. It should only use general purpose +registers x0 and x1 to do its work. The return value is 0 on successful +completion; otherwise the return value is -1. + + 4. Build flags --------------- diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S index 5b735283..6c4046a6 100644 --- a/drivers/arm/pl011/aarch32/pl011_console.S +++ b/drivers/arm/pl011/aarch32/pl011_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -40,6 +40,7 @@ .globl console_core_init .globl console_core_putc .globl console_core_getc + .globl console_core_flush /* ----------------------------------------------- @@ -158,3 +159,29 @@ getc_error: mov r0, #-1 bx lr endfunc console_core_getc + + /* --------------------------------------------- + * int console_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : r0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : r0, r1 + * --------------------------------------------- + */ +func console_core_flush + cmp r0, #0 + beq flush_error + +1: + /* Loop while the transmit FIFO is busy */ + ldr r1, [r0, #UARTFR] + tst r1, #PL011_UARTFR_BUSY + bne 1b + + mov r0, #0 + bx lr +flush_error: + mov r0, #-1 + bx lr +endfunc console_core_flush diff --git a/drivers/arm/pl011/aarch64/pl011_console.S b/drivers/arm/pl011/aarch64/pl011_console.S index 11e3df77..11030089 100644 --- a/drivers/arm/pl011/aarch64/pl011_console.S +++ b/drivers/arm/pl011/aarch64/pl011_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -41,6 +41,7 @@ .globl console_core_init .globl console_core_putc .globl console_core_getc + .globl console_core_flush /* ----------------------------------------------- @@ -151,3 +152,27 @@ getc_error: mov w0, #-1 ret endfunc console_core_getc + + /* --------------------------------------------- + * int console_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_flush + cbz x0, flush_error + +1: + /* Loop until the transmit FIFO is empty */ + ldr w1, [x0, #UARTFR] + tbnz w1, #PL011_UARTFR_BUSY_BIT, 1b + + mov w0, #0 + ret +flush_error: + mov w0, #-1 + ret +endfunc console_core_flush diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S index 2c7960d8..e16646e8 100644 --- a/drivers/cadence/uart/aarch64/cdns_console.S +++ b/drivers/cadence/uart/aarch64/cdns_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,9 +31,10 @@ #include <asm_macros.S> #include <cadence/cdns_uart.h> - .globl console_core_init - .globl console_core_putc - .globl console_core_getc + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + .globl console_core_flush /* ----------------------------------------------- * int console_core_init(unsigned long base_addr, @@ -125,3 +126,18 @@ getc_error: mov w0, #-1 ret endfunc console_core_getc + + /* --------------------------------------------- + * int console_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_flush + /* Placeholder */ + mov w0, #0 + ret +endfunc console_core_flush diff --git a/drivers/console/aarch32/console.S b/drivers/console/aarch32/console.S index 29933452..6f85a21f 100644 --- a/drivers/console/aarch32/console.S +++ b/drivers/console/aarch32/console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ .globl console_uninit .globl console_putc .globl console_getc + .globl console_flush /* * The console base is in the data section and not in .bss @@ -112,3 +113,18 @@ func console_getc ldr r0, [r1] b console_core_getc endfunc console_getc + + /* --------------------------------------------- + * int console_flush(void) + * Function to force a write of all buffered + * data that hasn't been output. It returns 0 + * upon successful completion, otherwise it + * returns -1. + * Clobber list : r0, r1 + * --------------------------------------------- + */ +func console_flush + ldr r1, =console_base + ldr r0, [r1] + b console_core_flush +endfunc console_flush diff --git a/drivers/console/aarch32/skeleton_console.S b/drivers/console/aarch32/skeleton_console.S index 383874e6..0b60bc75 100644 --- a/drivers/console/aarch32/skeleton_console.S +++ b/drivers/console/aarch32/skeleton_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -38,6 +38,7 @@ .globl console_core_init .globl console_core_putc .globl console_core_getc + .globl console_core_flush /* ----------------------------------------------- * int console_core_init(uintptr_t base_addr, @@ -109,3 +110,23 @@ getc_error: mov r0, #-1 bx lr endfunc console_core_getc + + /* --------------------------------------------- + * int console_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : r0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : r0, r1 + * --------------------------------------------- + */ +func console_core_flush + cmp r0, #0 + beq flush_error + /* Insert implementation here */ + mov r0, #0 + bx lr +flush_error: + mov r0, #-1 + bx lr +endfunc console_core_flush diff --git a/drivers/console/aarch64/console.S b/drivers/console/aarch64/console.S index bdd5f4c3..cd6579cf 100644 --- a/drivers/console/aarch64/console.S +++ b/drivers/console/aarch64/console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ .globl console_uninit .globl console_putc .globl console_getc + .globl console_flush /* * The console base is in the data section and not in .bss @@ -111,3 +112,18 @@ func console_getc ldr x0, [x1, :lo12:console_base] b console_core_getc endfunc console_getc + + /* --------------------------------------------- + * int console_flush(void) + * Function to force a write of all buffered + * data that hasn't been output. It returns 0 + * upon successful completion, otherwise it + * returns -1. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_flush + adrp x1, console_base + ldr x0, [x1, :lo12:console_base] + b console_core_flush +endfunc console_flush diff --git a/drivers/console/aarch64/skeleton_console.S b/drivers/console/aarch64/skeleton_console.S index 1583ee7d..01a42672 100644 --- a/drivers/console/aarch64/skeleton_console.S +++ b/drivers/console/aarch64/skeleton_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -38,6 +38,7 @@ .globl console_core_init .globl console_core_putc .globl console_core_getc + .globl console_core_flush /* ----------------------------------------------- * int console_core_init(uintptr_t base_addr, @@ -104,3 +105,22 @@ getc_error: mov w0, #-1 ret endfunc console_core_getc + + /* --------------------------------------------- + * int console_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_flush + cbz x0, flush_error + /* Insert implementation here */ + mov w0, #0 + ret +flush_error: + mov w0, #-1 + ret +endfunc console_core_flush diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S index 84664829..489fcbea 100644 --- a/drivers/ti/uart/aarch64/16550_console.S +++ b/drivers/ti/uart/aarch64/16550_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,6 +35,7 @@ .globl console_core_init .globl console_core_putc .globl console_core_getc + .globl console_core_flush /* ----------------------------------------------- * int console_core_init(unsigned long base_addr, @@ -153,3 +154,18 @@ getc_error: mov w0, #-1 ret endfunc console_core_getc + + /* --------------------------------------------- + * int console_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_flush + /* Placeholder */ + mov w0, #0 + ret +endfunc console_core_flush diff --git a/include/drivers/console.h b/include/drivers/console.h index 69ad0bd7..e6e3a1cb 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -38,6 +38,7 @@ int console_init(uintptr_t base_addr, void console_uninit(void); int console_putc(int c); int console_getc(void); +int console_flush(void); #endif /* __CONSOLE_H__ */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index f13b30d8..ddb1cab1 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -100,6 +100,7 @@ uintptr_t plat_get_my_stack(void); void plat_report_exception(unsigned int exception_type); int plat_crash_console_init(void); int plat_crash_console_putc(int c); +int plat_crash_console_flush(void); void plat_error_handler(int err) __dead2; void plat_panic_handler(void) __dead2; diff --git a/lib/psci/psci_system_off.c b/lib/psci/psci_system_off.c index de9ec643..eb3e7fbc 100644 --- a/lib/psci/psci_system_off.c +++ b/lib/psci/psci_system_off.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,6 +31,7 @@ #include <stddef.h> #include <arch_helpers.h> #include <assert.h> +#include <console.h> #include <debug.h> #include <platform.h> #include "psci_private.h" @@ -46,6 +47,8 @@ void psci_system_off(void) psci_spd_pm->svc_system_off(); } + console_flush(); + /* Call the platform specific hook */ psci_plat_pm_ops->system_off(); @@ -63,6 +66,8 @@ void psci_system_reset(void) psci_spd_pm->svc_system_reset(); } + console_flush(); + /* Call the platform specific hook */ psci_plat_pm_ops->system_reset(); diff --git a/lib/stdlib/assert.c b/lib/stdlib/assert.c index 90a1afe5..3486e50b 100644 --- a/lib/stdlib/assert.c +++ b/lib/stdlib/assert.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -28,7 +28,9 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include <console.h> #include <debug.h> +#include <platform.h> /* * This is a basic implementation. This could be improved. @@ -37,5 +39,8 @@ void __assert (const char *function, const char *file, unsigned int line, const char *assertion) { tf_printf("ASSERT: %s <%d> : %s\n", function, line, assertion); - while(1); + + console_flush(); + + plat_panic_handler(); } diff --git a/plat/arm/common/aarch32/arm_helpers.S b/plat/arm/common/aarch32/arm_helpers.S index 5d238ecb..51e5ee9a 100644 --- a/plat/arm/common/aarch32/arm_helpers.S +++ b/plat/arm/common/aarch32/arm_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,9 +31,10 @@ #include <platform_def.h> .weak plat_arm_calc_core_pos - .weak plat_crash_console_init - .weak plat_crash_console_putc .weak plat_my_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush /* ----------------------------------------------------- * unsigned int plat_my_core_pos(void) @@ -85,3 +86,16 @@ func plat_crash_console_putc ldr r1, =PLAT_ARM_CRASH_UART_BASE b console_core_putc endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : return -1 on error else return 0. + * Clobber list : r0 - r1 + * --------------------------------------------- + */ +func plat_crash_console_flush + ldr r1, =PLAT_ARM_CRASH_UART_BASE + b console_core_flush +endfunc plat_crash_console_flush diff --git a/plat/arm/common/aarch64/arm_helpers.S b/plat/arm/common/aarch64/arm_helpers.S index d782020a..60ff834a 100644 --- a/plat/arm/common/aarch64/arm_helpers.S +++ b/plat/arm/common/aarch64/arm_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,6 +34,7 @@ .weak plat_my_core_pos .globl plat_crash_console_init .globl plat_crash_console_putc + .globl plat_crash_console_flush .globl platform_mem_init @@ -88,6 +89,19 @@ func plat_crash_console_putc b console_core_putc endfunc plat_crash_console_putc + /* --------------------------------------------- + * int plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : return -1 on error else return 0. + * Clobber list : r0 - r1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x1, PLAT_ARM_CRASH_UART_BASE + b console_core_flush +endfunc plat_crash_console_flush + /* --------------------------------------------------------------------- * We don't need to carry out any memory initialization on ARM * platforms. The Secure RAM is accessible straight away. diff --git a/plat/common/aarch32/platform_helpers.S b/plat/common/aarch32/platform_helpers.S index 802e1fe6..357719bf 100644 --- a/plat/common/aarch32/platform_helpers.S +++ b/plat/common/aarch32/platform_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,6 +31,9 @@ #include <arch.h> #include <asm_macros.S> + .weak plat_crash_console_init + .weak plat_crash_console_putc + .weak plat_crash_console_flush .weak plat_reset_handler .weak plat_disable_acp .weak platform_mem_init @@ -41,6 +44,35 @@ * each platform. * ----------------------------------------------------- */ +func plat_crash_console_init + mov r0, #0 + bx lr +endfunc plat_crash_console_init + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_crash_console_putc + bx lr +endfunc plat_crash_console_putc + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_crash_console_flush + mov r0, #0 + bx lr +endfunc plat_crash_console_flush + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ func plat_reset_handler bx lr endfunc plat_reset_handler diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S index 68bda223..ce477384 100644 --- a/plat/common/aarch64/platform_helpers.S +++ b/plat/common/aarch64/platform_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,6 +35,7 @@ .weak plat_report_exception .weak plat_crash_console_init .weak plat_crash_console_putc + .weak plat_crash_console_flush .weak plat_reset_handler .weak plat_disable_acp .weak bl1_plat_prepare_exit @@ -98,6 +99,15 @@ endfunc plat_crash_console_putc /* ----------------------------------------------------- * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_crash_console_flush + ret +endfunc plat_crash_console_flush + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by * each platform. This function should preserve x19 - x29. * ----------------------------------------------------- */ diff --git a/plat/mediatek/common/drivers/uart/8250_console.S b/plat/mediatek/common/drivers/uart/8250_console.S index 5b0ae6df..8da248c1 100644 --- a/plat/mediatek/common/drivers/uart/8250_console.S +++ b/plat/mediatek/common/drivers/uart/8250_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ .globl console_core_init .globl console_core_putc .globl console_core_getc + .globl console_core_flush /* ----------------------------------------------- * int console_core_init(unsigned long base_addr, @@ -170,3 +171,18 @@ getc_error: mov w0, #-1 ret endfunc console_core_getc + + /* --------------------------------------------- + * int console_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_flush + /* Placeholder */ + mov w0, #0 + ret +endfunc console_core_flush diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c index c4170504..859ecd53 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c @@ -43,7 +43,7 @@ #define GPU_RESET_BIT (1 << 24) /* Video Memory base and size (live values) */ -static uintptr_t video_mem_base; +static uint64_t video_mem_base; static uint64_t video_mem_size; /* @@ -85,7 +85,9 @@ void tegra_memctrl_setup(void) (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ /* video memory carveout */ - tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, + (uint32_t)(video_mem_base >> 32)); + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base); tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); } @@ -208,7 +210,8 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) enable_mmu_el3(0); done: - tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32)); + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); /* store new values */ diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index bd16b991..fb57b2b7 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -136,7 +136,7 @@ const static mc_streamid_security_cfg_t sec_cfgs[] = { mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(AONDMAW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), @@ -178,8 +178,8 @@ const static mc_streamid_security_cfg_t sec_cfgs[] = { mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(AONDMAR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(AONW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), @@ -188,24 +188,17 @@ const static mc_streamid_security_cfg_t sec_cfgs[] = { mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(AONR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE), -#if ENABLE_CHIP_VERIFICATION_HARNESS - mc_make_sec_cfg(APEDMAW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(APER, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(APEW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(APEDMAR, NON_SECURE, OVERRIDE, ENABLE), -#else mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), -#endif }; const static mc_txn_override_cfg_t mc_override_cfgs[] = { @@ -623,6 +616,20 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); /* + * When TZ encryption enabled, + * We need setup TZDRAM before CPU to access TZ Carveout, + * otherwise CPU will fetch non-decrypted data. + * So save TZDRAM setting for retore by SC7 resume FW. + */ + + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, + tegra_mc_read_32(MC_SECURITY_CFG0_0)); + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, + tegra_mc_read_32(MC_SECURITY_CFG3_0)); + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI, + tegra_mc_read_32(MC_SECURITY_CFG1_0)); + + /* * MCE propogates the security configuration values across the * CCPLEX. */ diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v1.h b/plat/nvidia/tegra/include/drivers/memctrl_v1.h index e44a9ea9..b504594b 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v1.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v1.h @@ -60,14 +60,6 @@ #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 #define MC_SMMU_TRANSLATION_ENABLE (~0) -/* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 - -/* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c - static inline uint32_t tegra_mc_read_32(uint32_t off) { return mmio_read_32(TEGRA_MC_BASE + off); diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h index e1abe143..559ea2c5 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h @@ -353,51 +353,6 @@ typedef struct mc_streamid_security_cfg { #endif /* __ASSEMBLY__ */ /******************************************************************************* - * TZDRAM carveout configuration registers - ******************************************************************************/ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 -#define MC_SECURITY_CFG3_0 0x9BC - -/******************************************************************************* - * Video Memory carveout configuration registers - ******************************************************************************/ -#define MC_VIDEO_PROTECT_BASE_HI 0x978 -#define MC_VIDEO_PROTECT_BASE_LO 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c - -/******************************************************************************* - * TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers - ******************************************************************************/ -#define MC_TZRAM_BASE_LO 0x2194 -#define TZRAM_BASE_LO_SHIFT 12 -#define TZRAM_BASE_LO_MASK 0xFFFFF -#define MC_TZRAM_BASE_HI 0x2198 -#define TZRAM_BASE_HI_SHIFT 0 -#define TZRAM_BASE_HI_MASK 3 -#define MC_TZRAM_SIZE 0x219C -#define TZRAM_SIZE_RANGE_4KB_SHIFT 27 - -#define MC_TZRAM_CARVEOUT_CFG 0x2190 -#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) -#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 -#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) -#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 - -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC - -/******************************************************************************* * Memory Controller Reset Control registers ******************************************************************************/ #define MC_CLIENT_HOTRESET_CTRL0 0x200 @@ -438,43 +393,6 @@ typedef struct mc_streamid_security_cfg { #define MC_CLIENT_HOTRESET_STATUS1 0x974 /******************************************************************************* - * TSA configuration registers - ******************************************************************************/ -#define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 -#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 -#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 -#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 -#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 -#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 -#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 -#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 -#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 -#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 -#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 -#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 -#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 -#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 -#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 -#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 -#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 - -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) - -/******************************************************************************* * Memory Controller's PCFIFO client configuration registers ******************************************************************************/ #define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index 314b7007..4ba4f12c 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -104,6 +104,16 @@ ******************************************************************************/ #define TEGRA_MC_BASE 0x70019000 +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 +#define MC_SECURITY_CFG3_0 0x9BC + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE_HI 0x978 +#define MC_VIDEO_PROTECT_BASE_LO 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index e0eddfd3..6bac0d71 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -32,6 +32,36 @@ #define __TEGRA_DEF_H__ /******************************************************************************* + * MCE apertures used by the ARI interface + * + * Aperture 0 - Cpu0 (ARM Cortex A-57) + * Aperture 1 - Cpu1 (ARM Cortex A-57) + * Aperture 2 - Cpu2 (ARM Cortex A-57) + * Aperture 3 - Cpu3 (ARM Cortex A-57) + * Aperture 4 - Cpu4 (Denver15) + * Aperture 5 - Cpu5 (Denver15) + ******************************************************************************/ +#define MCE_ARI_APERTURE_0_OFFSET 0x0 +#define MCE_ARI_APERTURE_1_OFFSET 0x10000 +#define MCE_ARI_APERTURE_2_OFFSET 0x20000 +#define MCE_ARI_APERTURE_3_OFFSET 0x30000 +#define MCE_ARI_APERTURE_4_OFFSET 0x40000 +#define MCE_ARI_APERTURE_5_OFFSET 0x50000 +#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET + +/* number of apertures */ +#define MCE_ARI_APERTURES_MAX 6 + +/* each ARI aperture is 64KB */ +#define MCE_ARI_APERTURE_SIZE 0x10000 + +/******************************************************************************* + * CPU core id macros for the MCE_ONLINE_CORE ARI + ******************************************************************************/ +#define MCE_CORE_ID_MAX 8 +#define MCE_CORE_ID_MASK 0x7 + +/******************************************************************************* * These values are used by the PSCI implementation during the `CPU_SUSPEND` * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' * parameter. @@ -85,11 +115,87 @@ #define TEGRA_TSA_BASE 0x02400000 /******************************************************************************* + * TSA configuration registers + ******************************************************************************/ +#define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 +#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 +#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 +#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 +#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 +#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 +#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 +#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 +#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 +#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 +#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 +#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 + +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) + +/******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ #define TEGRA_MC_STREAMID_BASE 0x02C00000 #define TEGRA_MC_BASE 0x02C10000 +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 +#define MC_SECURITY_CFG3_0 0x9BC + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE_HI 0x978 +#define MC_VIDEO_PROTECT_BASE_LO 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + +/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ +#define MC_TZRAM_BASE_LO 0x2194 +#define TZRAM_BASE_LO_SHIFT 12 +#define TZRAM_BASE_LO_MASK 0xFFFFF +#define MC_TZRAM_BASE_HI 0x2198 +#define TZRAM_BASE_HI_SHIFT 0 +#define TZRAM_BASE_HI_MASK 3 +#define MC_TZRAM_SIZE 0x219C +#define TZRAM_SIZE_RANGE_4KB_SHIFT 27 + +#define MC_TZRAM_CARVEOUT_CFG 0x2190 +#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) +#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 +#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) +#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 + +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC + /******************************************************************************* * Tegra UART Controller constants ******************************************************************************/ @@ -148,6 +254,9 @@ #define SECURE_SCRATCH_RSV11_HI 0x6AC #define SECURE_SCRATCH_RSV53_LO 0x7F8 #define SECURE_SCRATCH_RSV53_HI 0x7FC +#define SECURE_SCRATCH_RSV54_HI 0x804 +#define SECURE_SCRATCH_RSV55_LO 0x808 +#define SECURE_SCRATCH_RSV55_HI 0x80C /******************************************************************************* * Tegra Memory Mapped Control Register Access Bus constants diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index d24377da..09613551 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -129,6 +129,16 @@ ******************************************************************************/ #define TEGRA_MC_BASE 0x70019000 +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 +#define MC_SECURITY_CFG3_0 0x9BC + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE_HI 0x978 +#define MC_VIDEO_PROTECT_BASE_LO 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h index 66e212bf..441a2c1b 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h @@ -35,67 +35,28 @@ #include <tegra_def.h> /******************************************************************************* - * MCE apertures used by the ARI interface - * - * Aperture 0 - Cpu0 (ARM Cortex A-57) - * Aperture 1 - Cpu1 (ARM Cortex A-57) - * Aperture 2 - Cpu2 (ARM Cortex A-57) - * Aperture 3 - Cpu3 (ARM Cortex A-57) - * Aperture 4 - Cpu4 (Denver15) - * Aperture 5 - Cpu5 (Denver15) - ******************************************************************************/ -#define MCE_ARI_APERTURE_0_OFFSET 0x0 -#define MCE_ARI_APERTURE_1_OFFSET 0x10000 -#define MCE_ARI_APERTURE_2_OFFSET 0x20000 -#define MCE_ARI_APERTURE_3_OFFSET 0x30000 -#define MCE_ARI_APERTURE_4_OFFSET 0x40000 -#define MCE_ARI_APERTURE_5_OFFSET 0x50000 -#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET - -/* number of apertures */ -#define MCE_ARI_APERTURES_MAX 6 - -/* each ARI aperture is 64KB */ -#define MCE_ARI_APERTURE_SIZE 0x10000 - -/******************************************************************************* - * CPU core ids - used by the MCE_ONLINE_CORE ARI - ******************************************************************************/ -typedef enum mce_core_id { - MCE_CORE_ID_DENVER_15_0, - MCE_CORE_ID_DENVER_15_1, - /* 2 and 3 are reserved */ - MCE_CORE_ID_A57_0 = 4, - MCE_CORE_ID_A57_1, - MCE_CORE_ID_A57_2, - MCE_CORE_ID_A57_3, - MCE_CORE_ID_MAX -} mce_core_id_t; - -#define MCE_CORE_ID_MASK 0x7 - -/******************************************************************************* * MCE commands ******************************************************************************/ typedef enum mce_cmd { MCE_CMD_ENTER_CSTATE = 0, - MCE_CMD_UPDATE_CSTATE_INFO, - MCE_CMD_UPDATE_CROSSOVER_TIME, - MCE_CMD_READ_CSTATE_STATS, - MCE_CMD_WRITE_CSTATE_STATS, - MCE_CMD_IS_SC7_ALLOWED, - MCE_CMD_ONLINE_CORE, - MCE_CMD_CC3_CTRL, - MCE_CMD_ECHO_DATA, - MCE_CMD_READ_VERSIONS, - MCE_CMD_ENUM_FEATURES, - MCE_CMD_ROC_FLUSH_CACHE_TRBITS, - MCE_CMD_ENUM_READ_MCA, - MCE_CMD_ENUM_WRITE_MCA, - MCE_CMD_ROC_FLUSH_CACHE, - MCE_CMD_ROC_CLEAN_CACHE, - MCE_CMD_ENABLE_LATIC, - MCE_CMD_UNCORE_PERFMON_REQ, + MCE_CMD_UPDATE_CSTATE_INFO = 1, + MCE_CMD_UPDATE_CROSSOVER_TIME = 2, + MCE_CMD_READ_CSTATE_STATS = 3, + MCE_CMD_WRITE_CSTATE_STATS = 4, + MCE_CMD_IS_SC7_ALLOWED = 5, + MCE_CMD_ONLINE_CORE = 6, + MCE_CMD_CC3_CTRL = 7, + MCE_CMD_ECHO_DATA = 8, + MCE_CMD_READ_VERSIONS = 9, + MCE_CMD_ENUM_FEATURES = 10, + MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11, + MCE_CMD_ENUM_READ_MCA = 12, + MCE_CMD_ENUM_WRITE_MCA = 13, + MCE_CMD_ROC_FLUSH_CACHE = 14, + MCE_CMD_ROC_CLEAN_CACHE = 15, + MCE_CMD_ENABLE_LATIC = 16, + MCE_CMD_UNCORE_PERFMON_REQ = 17, + MCE_CMD_MISC_CCPLEX = 18, MCE_CMD_IS_CCX_ALLOWED = 0xFE, MCE_CMD_MAX = 0xFF, } mce_cmd_t; @@ -337,9 +298,7 @@ typedef struct arch_mce_ops { * This ARI request allows updating the reset vector register for * D15 and A57 CPUs. */ - int (*update_reset_vector)(uint32_t ari_base, - uint32_t addr_low, - uint32_t addr_high); + int (*update_reset_vector)(uint32_t ari_base); /* * This ARI request instructs the ROC to flush A57 data caches in * order to maintain coherency with the Denver cluster. @@ -386,11 +345,17 @@ typedef struct arch_mce_ops { */ int (*read_write_uncore_perfmon)(uint32_t ari_base, uncore_perfmon_req_t req, uint64_t *data); + /* + * This ARI implements ARI_MISC_CCPLEX commands. This can be + * used to enable/disable coresight clock gating. + */ + void (*misc_ccplex)(uint32_t ari_base, uint32_t index, + uint32_t value); } arch_mce_ops_t; int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, uint64_t arg2); -int mce_update_reset_vector(uint32_t addr_lo, uint32_t addr_hi); +int mce_update_reset_vector(void); int mce_update_gsc_videomem(void); int mce_update_gsc_tzdram(void); int mce_update_gsc_tzram(void); @@ -411,7 +376,7 @@ int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); int ari_online_core(uint32_t ari_base, uint32_t core); int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); -int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi); +int ari_reset_vector_update(uint32_t ari_base); int ari_roc_flush_cache_trbits(uint32_t ari_base); int ari_roc_flush_cache(uint32_t ari_base); int ari_roc_clean_cache(uint32_t ari_base); @@ -420,6 +385,7 @@ int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); int ari_read_write_uncore_perfmon(uint32_t ari_base, uncore_perfmon_req_t req, uint64_t *data); +void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h index 3e6054bd..cb48de62 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h @@ -40,8 +40,8 @@ */ enum { - TEGRA_ARI_VERSION_MAJOR = 2, - TEGRA_ARI_VERSION_MINOR = 19, + TEGRA_ARI_VERSION_MAJOR = 3, + TEGRA_ARI_VERSION_MINOR = 0, }; typedef enum { @@ -107,15 +107,15 @@ typedef enum { typedef enum { TEGRA_ARI_CCPLEX_CCP0 = 0, TEGRA_ARI_CCPLEX_CCP1 = 1, - TEGRA_ARI_CCPLEX_CCP3 = 3, + TEGRA_ARI_CCPLEX_CCP3 = 3, /* obsoleted */ } tegra_ari_ccplex_sleep_state_t; typedef enum { TEGRA_ARI_SYSTEM_SC0 = 0, - TEGRA_ARI_SYSTEM_SC1 = 1, - TEGRA_ARI_SYSTEM_SC2 = 2, - TEGRA_ARI_SYSTEM_SC3 = 3, - TEGRA_ARI_SYSTEM_SC4 = 4, + TEGRA_ARI_SYSTEM_SC1 = 1, /* obsoleted */ + TEGRA_ARI_SYSTEM_SC2 = 2, /* obsoleted */ + TEGRA_ARI_SYSTEM_SC3 = 3, /* obsoleted */ + TEGRA_ARI_SYSTEM_SC4 = 4, /* obsoleted */ TEGRA_ARI_SYSTEM_SC7 = 7, TEGRA_ARI_SYSTEM_SC8 = 8, } tegra_ari_system_sleep_state_t; @@ -124,21 +124,22 @@ typedef enum { TEGRA_ARI_CROSSOVER_C1_C6 = 0, TEGRA_ARI_CROSSOVER_CC1_CC6 = 1, TEGRA_ARI_CROSSOVER_CC1_CC7 = 2, - TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3, - TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4, - TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5, - TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6, - TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7, - TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8, + TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7, /* obsoleted */ + TEGRA_ARI_CROSSOVER_SC0_SC7 = 7, + TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8, /* obsoleted */ } tegra_ari_crossover_index_t; typedef enum { TEGRA_ARI_CSTATE_STATS_CLEAR = 0, - TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES = 1, - TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, - TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, - TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, - TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, + TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES, + TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, /* obsoleted */ + TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, /* obsoleted */ + TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, /* obsoleted */ + TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, /* obsoleted */ TEGRA_ARI_CSTATE_STATS_A57_CC6_ENTRIES, TEGRA_ARI_CSTATE_STATS_A57_CC7_ENTRIES, TEGRA_ARI_CSTATE_STATS_D15_CC6_ENTRIES, @@ -403,17 +404,18 @@ typedef enum { TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5, TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6, TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12, + TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_SC0_SC7 = 12, TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13, TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14, - TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15, - TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16, - TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17, - TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18, + TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15, /* obsoleted */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16, /* obsoleted */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17, /* obsoleted */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18, /* obsoleted */ TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19, TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20, TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21, @@ -432,7 +434,7 @@ typedef enum { TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34, TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35, TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36, - TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /* Reserved (for Denver15 core 2) */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /* Reserved (for Denver15 core 2) */ TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38, /* Reserved (for Denver15 core 3) */ TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39, TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40, @@ -441,10 +443,8 @@ typedef enum { TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, TEGRA_NVG_CHANNEL_CC3_CTRL = 45, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46, + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46, /* obsoleted */ TEGRA_NVG_CHANNEL_LAST_INDEX, } tegra_nvg_channel_id_t; #endif /* T18X_TEGRA_ARI_H */ - - diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c index e11d1600..7597c12b 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c @@ -129,6 +129,9 @@ int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) return EINVAL; } + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* Enter the cstate, to be woken up after wake_time (TSC ticks) */ return ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT, TEGRA_ARI_ENTER_CSTATE, state, wake_time); @@ -140,6 +143,9 @@ int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, { uint32_t val = 0; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* update CLUSTER_CSTATE? */ if (cluster) val |= (cluster & CLUSTER_CSTATE_MASK) | @@ -172,6 +178,9 @@ int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) (type > TEGRA_ARI_CROSSOVER_CCP3_SC1)) return EINVAL; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* update crossover threshold time */ return ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CROSSOVER, type, time); @@ -185,6 +194,9 @@ uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state) if (state == 0) return EINVAL; + /* clean the previous response state */ + ari_clobber_response(ari_base); + ret = ari_request_wait(ari_base, 0, TEGRA_ARI_CSTATE_STATS, state, 0); if (ret != 0) return EINVAL; @@ -194,6 +206,9 @@ uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state) int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* write the cstate stats */ return ari_request_wait(ari_base, 0, TEGRA_ARI_WRITE_CSTATE_STATS, state, stats); @@ -226,6 +241,9 @@ int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) { int ret; + /* clean the previous response state */ + ari_clobber_response(ari_base); + ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7, wake_time); if (ret) { @@ -248,6 +266,9 @@ int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) return EINVAL; } + /* clean the previous response state */ + ari_clobber_response(ari_base); + ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_SC7_ALLOWED, state, wake_time); if (ret) { @@ -283,6 +304,9 @@ int ari_online_core(uint32_t ari_base, uint32_t core) return EINVAL; } + /* clean the previous response state */ + ari_clobber_response(ari_base); + return ari_request_wait(ari_base, 0, TEGRA_ARI_ONLINE_CORE, core, 0); } @@ -290,6 +314,9 @@ int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable { int val; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* * If the enable bit is cleared, Auto-CC3 will be disabled by setting * the SW visible voltage/frequency request registers for all non @@ -307,31 +334,43 @@ int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable return ari_request_wait(ari_base, 0, TEGRA_ARI_CC3_CTRL, val, 0); } -int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi) +int ari_reset_vector_update(uint32_t ari_base) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* * Need to program the CPU reset vector one time during cold boot * and SC7 exit */ - ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, lo, hi); + ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0, 0); return 0; } int ari_roc_flush_cache_trbits(uint32_t ari_base) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS, 0, 0); } int ari_roc_flush_cache(uint32_t ari_base) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY, 0, 0); } int ari_roc_clean_cache(uint32_t ari_base) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY, 0, 0); } @@ -372,6 +411,9 @@ int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx) if (gsc_idx > TEGRA_ARI_GSC_VPR_IDX) return EINVAL; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* * The MCE code will read the GSC carveout value, corrseponding to * the ID, from the MC registers and update the internal GSC registers @@ -384,6 +426,9 @@ int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx) void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* * The MCE will shutdown or restart the entire system */ @@ -396,6 +441,9 @@ int ari_read_write_uncore_perfmon(uint32_t ari_base, int ret; uint32_t val; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* sanity check input parameters */ if (req.perfmon_command.cmd == UNCORE_PERFMON_CMD_READ && !data) { ERROR("invalid parameters\n"); @@ -427,3 +475,22 @@ int ari_read_write_uncore_perfmon(uint32_t ari_base, return (int)req.perfmon_status.val; } + +void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value) +{ + /* + * This invokes the ARI_MISC_CCPLEX commands. This can be + * used to enable/disable coresight clock gating. + */ + + if ((index > TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) || + ((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) && + (value > 1))) { + ERROR("%s: invalid parameters \n", __func__); + return; + } + + /* clean the previous response state */ + ari_clobber_response(ari_base); + (void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, index, value); +} diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c index f87dfa4d..3a0edfb9 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c @@ -63,7 +63,8 @@ static arch_mce_ops_t nvg_mce_ops = { .read_write_mca = ari_read_write_mca, .update_ccplex_gsc = ari_update_ccplex_gsc, .enter_ccplex_state = ari_enter_ccplex_state, - .read_write_uncore_perfmon = ari_read_write_uncore_perfmon + .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, + .misc_ccplex = ari_misc_ccplex }; /* ARI functions handlers */ @@ -85,7 +86,8 @@ static arch_mce_ops_t ari_mce_ops = { .read_write_mca = ari_read_write_mca, .update_ccplex_gsc = ari_update_ccplex_gsc, .enter_ccplex_state = ari_enter_ccplex_state, - .read_write_uncore_perfmon = ari_read_write_uncore_perfmon + .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, + .misc_ccplex = ari_misc_ccplex }; typedef struct mce_config { @@ -307,14 +309,12 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, break; case MCE_CMD_ENUM_FEATURES: - ret = ops->call_enum_misc(cpu_ari_base, + ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0); /* update context to return features value */ write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); - ret = 0; - break; case MCE_CMD_ROC_FLUSH_CACHE_TRBITS: @@ -387,6 +387,11 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, write_ctx_reg(gp_regs, CTX_GPREG_X1, arg1); break; + case MCE_CMD_MISC_CCPLEX: + ops->misc_ccplex(cpu_ari_base, arg0, arg1); + + break; + default: ERROR("unknown MCE command (%d)\n", cmd); return EINVAL; @@ -398,11 +403,11 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, /******************************************************************************* * Handler to update the reset vector for CPUs ******************************************************************************/ -int mce_update_reset_vector(uint32_t addr_lo, uint32_t addr_hi) +int mce_update_reset_vector(void) { arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); - ops->update_reset_vector(mce_get_curr_cpu_ari_base(), addr_lo, addr_hi); + ops->update_reset_vector(mce_get_curr_cpu_ari_base()); return 0; } diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 35828787..a170b994 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -55,7 +55,7 @@ extern uint32_t __tegra186_cpu_reset_handler_data, /* state id mask */ #define TEGRA186_STATE_ID_MASK 0xF /* constants to get power state's wake time */ -#define TEGRA186_WAKE_TIME_MASK 0xFFFFFF +#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 #define TEGRA186_WAKE_TIME_SHIFT 4 /* default core wake mask for CPU_SUSPEND */ #define TEGRA186_CORE_WAKE_MASK 0x180c @@ -63,7 +63,9 @@ extern uint32_t __tegra186_cpu_reset_handler_data, #define TEGRA186_SE_CONTEXT_SIZE 3 static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; -static unsigned int wake_time[PLATFORM_CORE_COUNT]; +static struct t18x_psci_percpu_data { + unsigned int wake_time; +} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; /* System power down state */ uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; @@ -74,9 +76,19 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; int cpu = plat_my_core_pos(); - /* save the core wake time (us) */ - wake_time[cpu] = (power_state >> TEGRA186_WAKE_TIME_SHIFT) & - TEGRA186_WAKE_TIME_MASK; + /* save the core wake time (in TSC ticks)*/ + percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) + << TEGRA186_WAKE_TIME_SHIFT; + + /* + * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that + * the correct value is read in tegra_soc_pwr_domain_suspend(), which + * is called with caches disabled. It is possible to read a stale value + * from DRAM in that function, because the L2 cache is not flushed + * unless the cluster is entering CC6/CC7. + */ + clean_dcache_range((uint64_t)&percpu_data[cpu], + sizeof(percpu_data[cpu])); /* Sanity check the requested state id */ switch (state_id) { @@ -121,7 +133,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7; (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, - wake_time[cpu], 0); + percpu_data[cpu].wake_time, 0); } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { @@ -193,7 +205,8 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, /* Check if CCx state is allowed. */ ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, - TEGRA_ARI_CORE_C7, wake_time[cpu], 0); + TEGRA_ARI_CORE_C7, percpu_data[cpu].wake_time, + 0); if (ret) return PSTATE_ID_CORE_POWERDN; } diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c index 406c1e08..6576db11 100644 --- a/plat/nvidia/tegra/soc/t186/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c @@ -91,5 +91,5 @@ void plat_secondary_setup(void) addr_high); /* update reset vector address to the CCPLEX */ - mce_update_reset_vector(addr_low, addr_high); + mce_update_reset_vector(); } diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c index 8e337184..31e903eb 100644 --- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c @@ -66,6 +66,7 @@ extern uint32_t tegra186_system_powerdn_state; #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10 #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11 +#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12 /******************************************************************************* * This function is responsible for handling all T186 SiP calls @@ -104,6 +105,7 @@ int plat_sip_handler(uint32_t smc_fid, case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: + case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: /* clean up the high bits */ smc_fid &= MCE_CMD_MASK; diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S index 7619ed0c..21393d9b 100644 --- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S @@ -42,18 +42,14 @@ /* CPU reset handler routine */ func tegra186_cpu_reset_handler /* - * The Memory Controller loses state during System Suspend. We - * use this information to decide if the reset handler is running - * after a System Suspend. Resume from system suspend requires - * restoring the entire state from TZDRAM to TZRAM. + * The TZRAM loses state during System Suspend. We use this + * information to decide if the reset handler is running after a + * System Suspend. Resume from system suspend requires restoring + * the entire state from TZDRAM to TZRAM. */ - mov x1, #TEGRA_MC_BASE - ldr w0, [x1, #MC_SECURITY_CFG3_0] - lsl x0, x0, #32 - ldr w0, [x1, #MC_SECURITY_CFG0_0] - adr x1, tegra186_cpu_reset_handler - cmp x0, x1 - beq boot_cpu + mov x0, #BL31_BASE + ldr x0, [x0] + cbnz x0, boot_cpu /* resume from system suspend */ mov x0, #BL31_BASE diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index f589a8ad..267398ff 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -445,7 +445,7 @@ static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, } else if (timing_config->dram_type == LPDDR3) { mem_delay_ps = 5500; } else { - printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); + NOTICE("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); return 0; } round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; @@ -2009,21 +2009,6 @@ static uint32_t prepare_ddr_timing(uint32_t mhz) return index; } -void print_dram_status_info(void) -{ - uint32_t *p; - uint32_t i; - - p = (uint32_t *) &rk3399_dram_status.timing_config; - INFO("rk3399_dram_status.timing_config:\n"); - for (i = 0; i < sizeof(struct timing_related_config) / 4; i++) - tf_printf("%u\n", p[i]); - p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg; - INFO("rk3399_dram_status.drv_odt_lp_cfg:\n"); - for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++) - tf_printf("%u\n", p[i]); -} - uint32_t ddr_set_rate(uint32_t hz) { uint32_t low_power, index, ddr_index; |