diff options
| -rw-r--r-- | docs/firmware-design.rst | 11 | ||||
| -rw-r--r-- | include/lib/aarch32/arch.h | 5 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 5 | ||||
| -rw-r--r-- | include/lib/utils_def.h | 8 | ||||
| -rw-r--r-- | lib/locks/exclusive/aarch64/spinlock.S | 2 | ||||
| -rw-r--r-- | lib/xlat_tables_v2/aarch32/xlat_tables_arch.c | 8 | ||||
| -rw-r--r-- | lib/xlat_tables_v2/aarch64/xlat_tables_arch.c | 9 |
7 files changed, 47 insertions, 1 deletions
diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst index 36038ad6..997d29b8 100644 --- a/docs/firmware-design.rst +++ b/docs/firmware-design.rst @@ -2366,6 +2366,17 @@ This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when - The Compare and Swap instruction is used to implement spinlocks. Otherwise, the load-/store-exclusive instruction pair is used. +ARMv8.2 +~~~~~~~ + +This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 8 and +``ARM_ARCH_MINOR`` >= 2. + +- The Common not Private (CnP) bit is enabled to indicate that multiple + Page Entries in the same Inner Shareable domain use the same translation + table entries for a given stage of translation for a particular translation + regime. + Code Structure -------------- diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 661dbf81..56163c8b 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -323,6 +323,11 @@ ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) /* + * TTBR definitions + */ +#define TTBR_CNP_BIT 0x1 + +/* * CTR definitions */ #define CTR_CWG_SHIFT 24 diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 7bceea77..2adf7699 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -396,6 +396,11 @@ (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) /* + * TTBR Definitions + */ +#define TTBR_CNP_BIT 0x1 + +/* * CTR_EL0 definitions */ #define CTR_CWG_SHIFT U(24) diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 52496000..26ac4409 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -73,4 +73,12 @@ # define ULL(_x) (_x##ull) #endif +/* + * Test for the current architecture version to be at least the version + * expected. + */ +#define ARM_ARCH_AT_LEAST(_maj, _min) \ + ((ARM_ARCH_MAJOR > _maj) || \ + ((ARM_ARCH_MAJOR == _maj) && (ARM_ARCH_MINOR >= _min))) + #endif /* __UTILS_DEF_H__ */ diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S index 59305d84..e2f9eaa4 100644 --- a/lib/locks/exclusive/aarch64/spinlock.S +++ b/lib/locks/exclusive/aarch64/spinlock.S @@ -9,7 +9,7 @@ .globl spin_lock .globl spin_unlock -#if (ARM_ARCH_MAJOR > 8) || ((ARM_ARCH_MAJOR == 8) && (ARM_ARCH_MINOR >= 1)) +#if ARM_ARCH_AT_LEAST(8, 1) /* * When compiled for ARMv8.1 or later, choose spin locks based on Compare and diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c index be18552e..e66b9275 100644 --- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c @@ -10,6 +10,7 @@ #include <cassert.h> #include <platform_def.h> #include <utils.h> +#include <utils_def.h> #include <xlat_tables_v2.h> #include "../xlat_tables_private.h" @@ -153,6 +154,13 @@ void enable_mmu_arch(unsigned int flags, /* Set TTBR0 bits as well */ ttbr0 = (uint64_t)(uintptr_t) base_table; +#if ARM_ARCH_AT_LEAST(8, 2) + /* + * Enable CnP bit so as to share page tables with all PEs. + * Mandatory for ARMv8.2 implementations. + */ + ttbr0 |= TTBR_CNP_BIT; +#endif /* Now program the relevant system registers */ write_mair0(mair0); diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index 61eac106..097e815c 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c @@ -13,6 +13,7 @@ #include <platform_def.h> #include <sys/types.h> #include <utils.h> +#include <utils_def.h> #include <xlat_tables_v2.h> #include "../xlat_tables_private.h" @@ -166,6 +167,14 @@ uint64_t xlat_arch_get_xn_desc(int el) \ write_mair_el##_el(mair); \ write_tcr_el##_el(tcr); \ + \ + /* Set TTBR bits as well */ \ + if (ARM_ARCH_AT_LEAST(8, 2)) { \ + /* Enable CnP bit so as to share page tables */ \ + /* with all PEs. This is mandatory for */ \ + /* ARMv8.2 implementations. */ \ + ttbr |= TTBR_CNP_BIT; \ + } \ write_ttbr0_el##_el(ttbr); \ \ /* Ensure all translation table writes have drained */ \ |