diff options
81 files changed, 1016 insertions, 331 deletions
diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index ed027abc..49e4e8e2 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -87,6 +87,7 @@ register_t bl1_fwu_smc_handler(unsigned int smc_fid, case FWU_SMC_UPDATE_DONE: bl1_fwu_done((void *)x1, NULL); /* We should never return from bl1_fwu_done() */ + break; default: assert(0); @@ -747,6 +748,7 @@ static int bl1_fwu_image_reset(unsigned int image_id, unsigned int flags) case IMAGE_STATE_EXECUTED: default: assert(0); + break; } return 0; diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h index 6ac3b8c6..42a74d22 100644 --- a/bl1/bl1_private.h +++ b/bl1/bl1_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,18 +8,16 @@ #define __BL1_PRIVATE_H__ #include <types.h> +#include <utils_def.h> /******************************************************************************* * Declarations of linker defined symbols which will tell us where BL1 lives * in Trusted ROM and RAM ******************************************************************************/ -extern uintptr_t __BL1_ROM_END__; -#define BL1_ROM_END (uintptr_t)(&__BL1_ROM_END__) +IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END); -extern uintptr_t __BL1_RAM_START__; -extern uintptr_t __BL1_RAM_END__; -#define BL1_RAM_BASE (uintptr_t)(&__BL1_RAM_START__) -#define BL1_RAM_LIMIT (uintptr_t)(&__BL1_RAM_END__) +IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE); +IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT); /****************************************** * Function prototypes diff --git a/common/runtime_svc.c b/common/runtime_svc.c index 0ea4cd09..de80f30c 100644 --- a/common/runtime_svc.c +++ b/common/runtime_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,8 +19,6 @@ * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the * 'rt_svc_descs' array which contains the SMC handler. ******************************************************************************/ -#define RT_SVC_DESCS_START ((uintptr_t) (&__RT_SVC_DESCS_START__)) -#define RT_SVC_DESCS_END ((uintptr_t) (&__RT_SVC_DESCS_END__)) uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; static rt_svc_desc_t *rt_svc_descs; diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst index c30110ed..b7879a85 100644 --- a/docs/plat/rpi3.rst +++ b/docs/plat/rpi3.rst @@ -247,6 +247,11 @@ The following is not currently supported: - ``LOAD_IMAGE_V2=0``: Only version 2 is supported. +- ``MULTI_CONSOLE_API=0``: The multi console API must be enabled. Note that the + crash console uses the internal 16550 driver functions directly in order to be + able to print error messages during early crashes before setting up the + multi console API. + AArch64 kernel build instructions --------------------------------- @@ -300,7 +305,7 @@ Setup SD card The instructions assume that you have an SD card with a fresh install of `Raspbian`_ (or that, at least, the ``boot`` partition is untouched, or nearly -untouched). They have been tested with the image available in 2017-09-07. +untouched). They have been tested with the image available in 2018-03-13. 1. Insert the SD card and open the ``boot`` partition. diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c index e1568384..81808b9f 100644 --- a/drivers/arm/cci/cci.c +++ b/drivers/arm/cci/cci.c @@ -83,22 +83,25 @@ static unsigned int read_cci_part_number(uintptr_t base) */ static int get_slave_ports(unsigned int part_num) { - /* Macro to match CCI products */ -#define RET_ON_MATCH(product) \ - case CCI ## product ## _PART_NUM: \ - return CCI ## product ## _SLAVE_PORTS + int num_slave_ports = -1; switch (part_num) { - RET_ON_MATCH(400); - RET_ON_MATCH(500); - RET_ON_MATCH(550); - + case CCI400_PART_NUM: + num_slave_ports = CCI400_SLAVE_PORTS; + break; + case CCI500_PART_NUM: + num_slave_ports = CCI500_SLAVE_PORTS; + break; + case CCI550_PART_NUM: + num_slave_ports = CCI550_SLAVE_PORTS; + break; default: - return -1; + /* Do nothing in default case */ + break; } -#undef RET_ON_MATCH + return num_slave_ports; } #endif /* ENABLE_ASSERTIONS */ diff --git a/drivers/arm/gic/common/gic_common.c b/drivers/arm/gic/common/gic_common.c index d523772b..07ed63d7 100644 --- a/drivers/arm/gic/common/gic_common.c +++ b/drivers/arm/gic/common/gic_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -302,12 +302,15 @@ void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) { - unsigned bit_num = id & ((1 << ICFGR_SHIFT) - 1); + /* Interrupt configuration is a 2-bit field */ + unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1); + unsigned int bit_shift = bit_num << 1; + uint32_t reg_val = gicd_read_icfgr(base, id); /* Clear the field, and insert required configuration */ - reg_val &= ~(GIC_CFG_MASK << bit_num); - reg_val |= ((cfg & GIC_CFG_MASK) << bit_num); + reg_val &= ~(GIC_CFG_MASK << bit_shift); + reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); gicd_write_icfgr(base, id, reg_val); } diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index 7e2c7a7b..e25e501d 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -459,6 +459,7 @@ void gicv2_set_interrupt_type(unsigned int id, unsigned int type) break; default: assert(0); + break; } spin_unlock(&gic_lock); } diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c index dee63f18..69c69512 100644 --- a/drivers/arm/gic/v3/gicv3_helpers.c +++ b/drivers/arm/gic/v3/gicv3_helpers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -232,12 +232,15 @@ void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) */ void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg) { - unsigned bit_num = id & ((1 << ICFGR_SHIFT) - 1); + /* Interrupt configuration is a 2-bit field */ + unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1); + unsigned int bit_shift = bit_num << 1; + uint32_t reg_val = gicr_read_icfgr0(base); /* Clear the field, and insert required configuration */ - reg_val &= ~(GIC_CFG_MASK << bit_num); - reg_val |= ((cfg & GIC_CFG_MASK) << bit_num); + reg_val &= ~(GIC_CFG_MASK << bit_shift); + reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); gicr_write_icfgr0(base, reg_val); } @@ -248,12 +251,15 @@ void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg) */ void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg) { - unsigned bit_num = id & ((1 << ICFGR_SHIFT) - 1); + /* Interrupt configuration is a 2-bit field */ + unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1); + unsigned int bit_shift = bit_num << 1; + uint32_t reg_val = gicr_read_icfgr1(base); /* Clear the field, and insert required configuration */ - reg_val &= ~(GIC_CFG_MASK << bit_num); - reg_val |= ((cfg & GIC_CFG_MASK) << bit_num); + reg_val &= ~(GIC_CFG_MASK << bit_shift); + reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); gicr_write_icfgr1(base, reg_val); } diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index f4a3ef81..d8fc7d68 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -1004,6 +1004,7 @@ void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, break; default: assert(0); + break; } if (id < MIN_SPI_ID) { diff --git a/drivers/auth/img_parser_mod.c b/drivers/auth/img_parser_mod.c index 6a010711..63160141 100644 --- a/drivers/auth/img_parser_mod.c +++ b/drivers/auth/img_parser_mod.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,11 +12,10 @@ #include <limits.h> #include <stdint.h> #include <string.h> +#include <utils_def.h> -extern uintptr_t __PARSER_LIB_DESCS_START__; -extern uintptr_t __PARSER_LIB_DESCS_END__; -#define PARSER_LIB_DESCS_START ((uintptr_t) (&__PARSER_LIB_DESCS_START__)) -#define PARSER_LIB_DESCS_END ((uintptr_t) (&__PARSER_LIB_DESCS_END__)) +IMPORT_SYM(uintptr_t, __PARSER_LIB_DESCS_START__, PARSER_LIB_DESCS_START); +IMPORT_SYM(uintptr_t, __PARSER_LIB_DESCS_END__, PARSER_LIB_DESCS_END); static unsigned int parser_lib_indices[IMG_MAX_TYPES]; static img_parser_lib_desc_t *parser_lib_descs; diff --git a/drivers/synopsys/emmc/dw_mmc.c b/drivers/synopsys/emmc/dw_mmc.c index 701e6d53..156c2b4e 100644 --- a/drivers/synopsys/emmc/dw_mmc.c +++ b/drivers/synopsys/emmc/dw_mmc.c @@ -321,6 +321,7 @@ static int dw_set_ios(int clk, int width) break; default: assert(0); + break; } dw_set_clk(clk); return 0; diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S index b02209df..56e7e5c1 100644 --- a/drivers/ti/uart/aarch64/16550_console.S +++ b/drivers/ti/uart/aarch64/16550_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,10 +17,11 @@ .globl console_16550_core_init .globl console_16550_core_putc .globl console_16550_core_getc + .globl console_16550_core_flush .globl console_16550_putc .globl console_16550_getc - + .globl console_16550_flush /* ----------------------------------------------- * int console_16550_core_init(uintptr_t base_addr, @@ -119,6 +120,7 @@ endfunc console_16550_register .equ console_core_init,console_16550_core_init .equ console_core_putc,console_16550_core_putc .equ console_core_getc,console_16550_core_getc + .equ console_core_flush,console_16550_core_flush #endif /* -------------------------------------------------------- @@ -222,8 +224,7 @@ func console_16550_getc endfunc console_16550_getc /* --------------------------------------------- - * int console_core_flush(uintptr_t base_addr) - * DEPRECATED: Not used with MULTI_CONSOLE_API! + * int console_16550_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address @@ -231,8 +232,36 @@ endfunc console_16550_getc * Clobber list : x0, x1 * --------------------------------------------- */ -func console_core_flush - /* Placeholder */ +func console_16550_core_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + + /* Loop until the transmit FIFO is empty */ +1: ldr w1, [x0, #UARTLSR] + and w1, w1, #(UARTLSR_TEMT | UARTLSR_THRE) + cmp w1, #(UARTLSR_TEMT | UARTLSR_THRE) + b.ne 1b + mov w0, #0 ret -endfunc console_core_flush +endfunc console_16550_core_flush + + /* --------------------------------------------- + * int console_16550_flush(console_pl011_t *console) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - pointer to console_t structure + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_16550_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_16550_BASE] + b console_16550_core_flush +endfunc console_16550_flush diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index 254866f8..515fc278 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -271,6 +271,7 @@ static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun, break; default: assert(0); + break; } if (hd->dd == DD_IN) flush_dcache_range(buf, length); @@ -359,6 +360,7 @@ static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn, break; default: assert(0); + break; } flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t)); flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); @@ -511,6 +513,9 @@ static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, case QUERY_WRITE_ATTR: assert(((buf & 3) == 0) && (size != 0)); break; + default: + /* Do nothing in default case */ + break; } get_utrd(&utrd); ufs_prepare_query(&utrd, op, idn, index, sel, buf, size); @@ -533,6 +538,9 @@ static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)), size); break; + default: + /* Do nothing in default case */ + break; } (void)result; } diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 4ef916f5..09a394dd 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -64,33 +64,41 @@ #include <types.h> #include <utils_def.h> /* To retain compatibility */ + /* * Declarations of linker defined symbols to help determine memory layout of * BL images */ #if SEPARATE_CODE_AND_RODATA -extern uintptr_t __TEXT_START__; -extern uintptr_t __TEXT_END__; -extern uintptr_t __RODATA_START__; -extern uintptr_t __RODATA_END__; +IMPORT_SYM(unsigned long, __TEXT_START__, BL_CODE_BASE); +IMPORT_SYM(unsigned long, __TEXT_END__, BL_CODE_END); +IMPORT_SYM(unsigned long, __RODATA_START__, BL_RO_DATA_BASE); +IMPORT_SYM(unsigned long, __RODATA_END__, BL_RO_DATA_END); #else -extern uintptr_t __RO_START__; -extern uintptr_t __RO_END__; +IMPORT_SYM(unsigned long, __RO_START__, BL_CODE_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL_CODE_END); #endif #if defined(IMAGE_BL2) -extern uintptr_t __BL2_END__; +IMPORT_SYM(unsigned long, __BL2_END__, BL2_END); #elif defined(IMAGE_BL2U) -extern uintptr_t __BL2U_END__; +IMPORT_SYM(unsigned long, __BL2U_END__, BL2U_END); #elif defined(IMAGE_BL31) -extern uintptr_t __BL31_END__; +IMPORT_SYM(unsigned long, __BL31_END__, BL31_END); #elif defined(IMAGE_BL32) -extern uintptr_t __BL32_END__; +IMPORT_SYM(unsigned long, __BL32_END__, BL32_END); #endif /* IMAGE_BLX */ +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ #if USE_COHERENT_MEM -extern uintptr_t __COHERENT_RAM_START__; -extern uintptr_t __COHERENT_RAM_END__; +IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE); +IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL_COHERENT_RAM_END); #endif /******************************************************************************* diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h index d12af227..5d9fa390 100644 --- a/include/common/runtime_svc.h +++ b/include/common/runtime_svc.h @@ -122,8 +122,8 @@ CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \ void runtime_svc_init(void); uintptr_t handle_runtime_svc(uint32_t smc_fid, void *cookie, void *handle, unsigned int flags); -extern uintptr_t __RT_SVC_DESCS_START__; -extern uintptr_t __RT_SVC_DESCS_END__; +IMPORT_SYM(uintptr_t, __RT_SVC_DESCS_START__, RT_SVC_DESCS_START); +IMPORT_SYM(uintptr_t, __RT_SVC_DESCS_END__, RT_SVC_DESCS_END); void init_crash_reporting(void); extern uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h index 001f5736..6e953a0d 100644 --- a/include/drivers/arm/gic_common.h +++ b/include/drivers/arm/gic_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,9 +29,9 @@ /* Constant to indicate a spurious interrupt in all GIC versions */ #define GIC_SPURIOUS_INTERRUPT 1023 -/* Interrupt configurations */ -#define GIC_INTR_CFG_LEVEL 0 -#define GIC_INTR_CFG_EDGE 1 +/* Interrupt configurations: 2-bit fields with LSB reserved */ +#define GIC_INTR_CFG_LEVEL (0 << 1) +#define GIC_INTR_CFG_EDGE (1 << 1) /* Constants to categorise priorities */ #define GIC_HIGHEST_SEC_PRIORITY 0x0 diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index a3d32263..2320760e 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h @@ -37,8 +37,8 @@ /* * Defines for PMF SMC function ids. */ -#define PMF_SMC_GET_TIMESTAMP_32 0x82000010 -#define PMF_SMC_GET_TIMESTAMP_64 0xC2000010 +#define PMF_SMC_GET_TIMESTAMP_32 0x82000010u +#define PMF_SMC_GET_TIMESTAMP_64 0xC2000010u #define PMF_NUM_SMC_CALLS 2 /* diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 4a5c3e0b..8abc73c0 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -99,4 +99,21 @@ ((ARM_ARCH_MAJOR > _maj) || \ ((ARM_ARCH_MAJOR == _maj) && (ARM_ARCH_MINOR >= _min))) +/* + * Import an assembly or linker symbol as a C expression with the specified + * type + */ +#define IMPORT_SYM(type, sym, name) \ + extern char sym[];\ + static const __attribute__((unused)) type name = (type) sym; + +/* + * When the symbol is used to hold a pointer, its alignment can be asserted + * with this macro. For example, if there is a linker symbol that is going to + * be used as a 64-bit pointer, the value of the linker symbol must also be + * aligned to 64 bit. This macro makes sure this is the case. + */ +#define ASSERT_SYM_PTR_ALIGN(sym) assert(((size_t)(sym) % __alignof__(*(sym))) == 0) + + #endif /* __UTILS_DEF_H__ */ diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h index a841c3db..84923b9a 100644 --- a/include/plat/common/common_def.h +++ b/include/plat/common/common_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,33 +74,13 @@ * page of it with the right memory attributes. */ #if SEPARATE_CODE_AND_RODATA -#define BL_CODE_BASE (unsigned long)(&__TEXT_START__) -#define BL_CODE_END (unsigned long)(&__TEXT_END__) -#define BL_RO_DATA_BASE (unsigned long)(&__RODATA_START__) -#define BL_RO_DATA_END (unsigned long)(&__RODATA_END__) #define BL1_CODE_END BL_CODE_END -#define BL1_RO_DATA_BASE (unsigned long)(&__RODATA_START__) +#define BL1_RO_DATA_BASE BL_RO_DATA_BASE #define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE) #else -#define BL_CODE_BASE (unsigned long)(&__RO_START__) -#define BL_CODE_END (unsigned long)(&__RO_END__) #define BL_RO_DATA_BASE 0 #define BL_RO_DATA_END 0 - #define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE) -#define BL1_RO_DATA_BASE 0 -#define BL1_RO_DATA_END 0 #endif /* SEPARATE_CODE_AND_RODATA */ - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL_COHERENT_RAM_END (unsigned long)(&__COHERENT_RAM_END__) - #endif /* __COMMON_DEF_H__ */ diff --git a/include/services/secure_partition.h b/include/services/secure_partition.h index 93df2a13..f68f711b 100644 --- a/include/services/secure_partition.h +++ b/include/services/secure_partition.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,15 +11,11 @@ #include <types.h> #include <utils_def.h> -/* Linker symbols */ -extern uintptr_t __SP_IMAGE_XLAT_TABLES_START__; -extern uintptr_t __SP_IMAGE_XLAT_TABLES_END__; +/* Import linker symbols */ +IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_START__, SP_IMAGE_XLAT_TABLES_START); +IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_END__, SP_IMAGE_XLAT_TABLES_END); /* Definitions */ -#define SP_IMAGE_XLAT_TABLES_START \ - (uintptr_t)(&__SP_IMAGE_XLAT_TABLES_START__) -#define SP_IMAGE_XLAT_TABLES_END \ - (uintptr_t)(&__SP_IMAGE_XLAT_TABLES_END__) #define SP_IMAGE_XLAT_TABLES_SIZE \ (SP_IMAGE_XLAT_TABLES_END - SP_IMAGE_XLAT_TABLES_START) diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c index 8f59215e..37697f52 100644 --- a/lib/locks/bakery/bakery_lock_normal.c +++ b/lib/locks/bakery/bakery_lock_normal.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <cpu_data.h> #include <platform.h> #include <string.h> +#include <utils_def.h> /* * Functions in this file implement Bakery Algorithm for mutual exclusion with the @@ -49,8 +50,7 @@ CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \ * Use the linker defined symbol which has evaluated the size reqiurement. * This is not as efficient as using a platform defined constant */ -extern void *__PERCPU_BAKERY_LOCK_SIZE__; -#define PERCPU_BAKERY_LOCK_SIZE ((uintptr_t)&__PERCPU_BAKERY_LOCK_SIZE__) +IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE); #endif #define get_bakery_info(cpu_ix, lock) \ diff --git a/lib/pmf/pmf_main.c b/lib/pmf/pmf_main.c index 2cf260ec..0208948f 100644 --- a/lib/pmf/pmf_main.c +++ b/lib/pmf/pmf_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #include <platform.h> #include <pmf.h> #include <string.h> +#include <utils_def.h> /******************************************************************************* * The 'pmf_svc_descs' array holds the PMF service descriptors exported by @@ -21,16 +22,12 @@ * index of the descriptor in the 'pmf_svc_descs' array which contains the * service function pointers. ******************************************************************************/ -extern uintptr_t __PMF_SVC_DESCS_START__; -extern uintptr_t __PMF_SVC_DESCS_END__; -#define PMF_SVC_DESCS_START ((uintptr_t)(&__PMF_SVC_DESCS_START__)) -#define PMF_SVC_DESCS_END ((uintptr_t)(&__PMF_SVC_DESCS_END__)) -extern void *__PERCPU_TIMESTAMP_SIZE__; -#define PMF_PERCPU_TIMESTAMP_SIZE ((uintptr_t)&__PERCPU_TIMESTAMP_SIZE__) -extern uintptr_t __PMF_TIMESTAMP_START__; -#define PMF_TIMESTAMP_ARRAY_START ((uintptr_t)&__PMF_TIMESTAMP_START__) -extern uintptr_t __PMF_TIMESTAMP_END__; -#define PMF_TIMESTAMP_ARRAY_END ((uintptr_t)&__PMF_TIMESTAMP_END__) + +IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_START__, PMF_SVC_DESCS_START); +IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_END__, PMF_SVC_DESCS_END); +IMPORT_SYM(uintptr_t, __PERCPU_TIMESTAMP_SIZE__, PMF_PERCPU_TIMESTAMP_SIZE); +IMPORT_SYM(intptr_t, __PMF_TIMESTAMP_START__, PMF_TIMESTAMP_ARRAY_START); +IMPORT_SYM(uintptr_t, __PMF_TIMESTAMP_END__, PMF_TIMESTAMP_ARRAY_END); #define PMF_SVC_DESCS_MAX 10 diff --git a/lib/pmf/pmf_smc.c b/lib/pmf/pmf_smc.c index 5cf193e2..e8661180 100644 --- a/lib/pmf/pmf_smc.c +++ b/lib/pmf/pmf_smc.c @@ -30,8 +30,7 @@ uintptr_t pmf_smc_handler(unsigned int smc_fid, x2 = (uint32_t)x2; x3 = (uint32_t)x3; - switch (smc_fid) { - case PMF_SMC_GET_TIMESTAMP_32: + if (smc_fid == PMF_SMC_GET_TIMESTAMP_32) { /* * Return error code and the captured * time-stamp to the caller. @@ -41,13 +40,9 @@ uintptr_t pmf_smc_handler(unsigned int smc_fid, rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value); SMC_RET3(handle, rc, (uint32_t)ts_value, (uint32_t)(ts_value >> 32)); - - default: - break; } } else { - switch (smc_fid) { - case PMF_SMC_GET_TIMESTAMP_64: + if (smc_fid == PMF_SMC_GET_TIMESTAMP_64) { /* * Return error code and the captured * time-stamp to the caller. @@ -56,9 +51,6 @@ uintptr_t pmf_smc_handler(unsigned int smc_fid, */ rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value); SMC_RET2(handle, rc, ts_value); - - default: - break; } } diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index d25d1775..607d0cd5 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c @@ -414,10 +414,12 @@ u_register_t psci_smc_handler(uint32_t smc_fid, case PSCI_SYSTEM_OFF: psci_system_off(); /* We should never return from psci_system_off() */ + break; case PSCI_SYSTEM_RESET: psci_system_reset(); /* We should never return from psci_system_reset() */ + break; case PSCI_FEATURES: return psci_features(x1); diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c index 3e79c5d7..e925d34e 100644 --- a/lib/psci/psci_stat.c +++ b/lib/psci/psci_stat.c @@ -24,7 +24,8 @@ typedef struct psci_stat { * Following is used to keep track of the last cpu * that goes to power down in non cpu power domains. */ -static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {-1}; +static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = { + [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS-1] = -1}; /* * Following are used to store PSCI STAT values for @@ -129,6 +130,10 @@ void psci_stats_update_pwr_up(unsigned int end_pwrlvl, * prior to this CPU powering on. */ parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + /* Return early if this is the first power up. */ + if (last_cpu_in_non_cpu_pd[parent_idx] == -1) + return; + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { local_state = state_info->pwr_domain_state[lvl]; if (is_local_state_run(local_state)) { diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index f61cdb3c..0fa83a5c 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c @@ -324,13 +324,11 @@ static int fvp_node_hw_state(u_register_t target_cpu, if (psysr == PSYSR_INVALID) return PSCI_E_INVALID_PARAMS; - switch (power_level) { - case ARM_PWR_LVL0: + if (power_level == ARM_PWR_LVL0) { ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF; - break; - case ARM_PWR_LVL1: + } else { + /* power_level == ARM_PWR_LVL1 */ ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF; - break; } return ret; diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk new file mode 100644 index 00000000..9893ba50 --- /dev/null +++ b/plat/arm/board/sgi575/platform.mk @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include plat/arm/css/sgi/sgi-common.mk diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 7add61da..8a6c7680 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -305,6 +305,9 @@ int arm_bl2_handle_post_image_load(unsigned int image_id) } break; #endif + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S new file mode 100644 index 00000000..c435d8b4 --- /dev/null +++ b/plat/arm/css/sgi/aarch64/sgi_helper.S @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <platform_def.h> + + .globl plat_is_my_cpu_primary + .globl plat_arm_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu (applicable only after a cold boot) + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mov x9, x30 + bl plat_my_core_pos + ldr x1, =SGI_BOOT_CFG_ADDR + ldr x1, [x1] + ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ + #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH + cmp x0, x1 + cset w0, eq + ret x9 +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(uint64_t mpidr) + * Helper function to calculate the core position. + * ----------------------------------------------------- + */ +func plat_arm_calc_core_pos + mrs x2, mpidr_el1 + ands x2, x2, #MPIDR_MT_MASK + beq 1f + lsr x0, x0, #MPIDR_AFF1_SHIFT +1: + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + and x0, x0, #MPIDR_AFFLVL_MASK + ret +endfunc plat_arm_calc_core_pos diff --git a/plat/arm/css/sgi/include/plat_macros.S b/plat/arm/css/sgi/include/plat_macros.S new file mode 100644 index 00000000..fe9a66c3 --- /dev/null +++ b/plat/arm/css/sgi/include/plat_macros.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include <css_macros.S> + +/* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * + * There are currently no platform specific regs + * to print. + * --------------------------------------------- + */ + .macro plat_crash_print_regs + .endm +#endif /* __PLAT_MACROS_S__ */ diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h new file mode 100644 index 00000000..62f40599 --- /dev/null +++ b/plat/arm/css/sgi/include/platform_def.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include <arm_def.h> +#include <board_arm_def.h> +#include <board_css_def.h> +#include <common_def.h> +#include <css_def.h> +#include <soc_css_def.h> + +#define CSS_SGI_MAX_CORES_PER_CLUSTER 4 + +/* CPU topology */ +#define PLAT_ARM_CLUSTER_COUNT 2 +#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ + CSS_SGI_MAX_CORES_PER_CLUSTER) + +#if ARM_BOARD_OPTIMISE_MEM + +#if defined(IMAGE_BL31) || defined(IMAGE_BL32) +# define PLAT_ARM_MMAP_ENTRIES 6 +# define MAX_XLAT_TABLES 4 +#else +# define PLAT_ARM_MMAP_ENTRIES 10 +# define MAX_XLAT_TABLES 5 +#endif + +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 +#else +# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 +#endif + +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 +#else +# define PLAT_ARM_MAX_BL2_SIZE 0xC000 +#endif + +#endif /* ARM_BOARD_OPTIMISE_MEM */ + +#define PLAT_ARM_NSTIMER_FRAME_ID 0 + +#define PLAT_CSS_MHU_BASE 0x45000000 + +#define PLAT_ARM_TRUSTED_ROM_BASE 0x0 +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ + +#define PLAT_MAX_PWR_LVL 1 + +#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ + CSS_IRQ_MHU + +#define PLAT_ARM_G0_IRQS ARM_G0_IRQS + +#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + +#define CSS_SGI_DEVICE_BASE (0x20000000) +#define CSS_SGI_DEVICE_SIZE (0x20000000) +#define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ + CSS_SGI_DEVICE_BASE, \ + CSS_SGI_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 +#define SGI_BOOT_CFG_ADDR 0x45410000 +#define PLAT_CSS_PRIMARY_CPU_SHIFT 8 +#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 6 + +/* GIC related constants */ +#define PLAT_ARM_GICD_BASE 0x30000000 +#define PLAT_ARM_GICC_BASE 0x2C000000 +#define PLAT_ARM_GICR_BASE 0x300C0000 + +/* Platform ID address */ +#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) +#ifndef __ASSEMBLY__ +/* SSC_VERSION related accessors */ +/* Returns the part number of the platform */ +#define GET_SGI_PART_NUM \ + GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) +/* Returns the configuration number of the platform */ +#define GET_SGI_CONFIG_NUM \ + GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) +#endif /* __ASSEMBLY__ */ + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/arm/css/sgi/include/sgi_plat_config.h b/plat/arm/css/sgi/include/sgi_plat_config.h new file mode 100644 index 00000000..c9ff1fe2 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_plat_config.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SGI_PLAT_CONFIG_H__ +#define __SGI_PLAT_CONFIG_H__ + +#include <arm_gic.h> +#include <ccn.h> +#include <gicv3.h> + +/* The type of interconnect */ +typedef enum { + ARM_CCI = 0, + ARM_CCN, + ARM_CMN +} css_inteconn_type_t; + +typedef ccn_desc_t inteconn_desc_t; + +/* Interconnect configurations */ +typedef struct css_inteconn_config { + css_inteconn_type_t ip_type; + const inteconn_desc_t *plat_inteconn_desc; +} css_inteconn_config_t; + +/* Topology configurations */ +typedef struct css_topology { + const unsigned char *power_tree; + unsigned int plat_cluster_core_count; +} css_topology_t; + +typedef struct css_plat_config { + const gicv3_driver_data_t *gic_data; + const css_inteconn_config_t *inteconn; + const css_topology_t *topology; +} css_plat_config_t; + +void plat_config_init(void); +css_plat_config_t *get_plat_config(void); + +#endif /* __SGI_PLAT_CONFIG_H__ */ diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h new file mode 100644 index 00000000..5698d0ab --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_variant.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SGI_VARIANT_H__ +#define __SGI_VARIANT_H__ + +/* SSC_VERSION values for SGI575 */ +#define SGI575_SSC_VER_PART_NUM 0x0783 + +#endif /* __SGI_VARIANT_H__ */ diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk new file mode 100644 index 00000000..9c398b76 --- /dev/null +++ b/plat/arm/css/sgi/sgi-common.mk @@ -0,0 +1,59 @@ +# +# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +ENABLE_PLAT_COMPAT := 0 + +CSS_ENT_BASE := plat/arm/css/sgi + +INTERCONNECT_SOURCES := ${CSS_ENT_BASE}/sgi_interconnect.c + +PLAT_INCLUDES += -I${CSS_ENT_BASE}/include + +ENT_CPU_SOURCES := lib/cpus/aarch64/cortex_a75.S + +ENT_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/v3/gicv3_helpers.c \ + plat/common/plat_gicv3.c \ + plat/arm/common/arm_gicv3.c \ + ${CSS_ENT_BASE}/sgi_gic_config.c \ + drivers/arm/gic/v3/gic600.c + + +PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c \ + ${CSS_ENT_BASE}/aarch64/sgi_helper.S + +BL1_SOURCES += ${INTERCONNECT_SOURCES} \ + ${ENT_CPU_SOURCES} \ + ${CSS_ENT_BASE}/sgi_bl1_setup.c \ + ${CSS_ENT_BASE}/sgi_plat_config.c + +BL2_SOURCES += ${CSS_ENT_BASE}/sgi_security.c + +BL31_SOURCES += ${ENT_CPU_SOURCES} \ + ${INTERCONNECT_SOURCES} \ + ${ENT_GIC_SOURCES} \ + ${CSS_ENT_BASE}/sgi_bl31_setup.c \ + ${CSS_ENT_BASE}/sgi_topology.c \ + ${CSS_ENT_BASE}/sgi_plat_config.c + +$(eval $(call add_define,SGI_PLAT)) + +override CSS_LOAD_SCP_IMAGES := 0 +override NEED_BL2U := no +override ARM_BL31_IN_DRAM := 1 + +# System coherency is managed in hardware +HW_ASSISTED_COHERENCY := 1 + +# When building for systems with hardware-assisted coherency, there's no need to +# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. +USE_COHERENT_MEM := 0 + +include plat/arm/common/arm_common.mk +include plat/arm/css/common/css_common.mk +include plat/arm/soc/common/soc_css.mk +include plat/arm/board/common/board_common.mk diff --git a/plat/arm/css/sgi/sgi_bl1_setup.c b/plat/arm/css/sgi/sgi_bl1_setup.c new file mode 100644 index 00000000..d3d98d92 --- /dev/null +++ b/plat/arm/css/sgi/sgi_bl1_setup.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <bl_common.h> +#include <debug.h> +#include <plat_arm.h> +#include <sgi_plat_config.h> +#include <soc_css.h> + +void bl1_early_platform_setup(void) +{ + /* Initialize the platform configuration structure */ + plat_config_init(); + + arm_bl1_early_platform_setup(); +} diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c new file mode 100644 index 00000000..0928b83b --- /dev/null +++ b/plat/arm/css/sgi/sgi_bl31_setup.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <bl_common.h> +#include <debug.h> +#include <plat_arm.h> +#include <sgi_plat_config.h> + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + uint32_t plat_version; + bl_params_node_t *bl_params; + + bl_params = ((bl_params_t *)arg0)->head; + + /* Initialize the platform configuration structure */ + plat_config_init(); + + while (bl_params) { + if (bl_params->image_id == BL33_IMAGE_ID) { + plat_version = mmio_read_32(SSC_VERSION); + bl_params->ep_info->args.arg2 = plat_version; + break; + } + + bl_params = bl_params->next_params_info; + } + + arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); +} diff --git a/plat/arm/css/sgi/sgi_gic_config.c b/plat/arm/css/sgi/sgi_gic_config.c new file mode 100644 index 00000000..dfccc1b6 --- /dev/null +++ b/plat/arm/css/sgi/sgi_gic_config.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <sgi_plat_config.h> + +void plat_arm_gic_driver_init(void) +{ + /* + * The GICv3 driver is initialized in EL3 and does not need + * to be initialized again in S-EL1. This is because the S-EL1 + * can use GIC system registers to manage interrupts and does + * not need GIC interface base addresses to be configured. + */ + gicv3_driver_init(get_plat_config()->gic_data); +} diff --git a/plat/arm/css/sgi/sgi_interconnect.c b/plat/arm/css/sgi/sgi_interconnect.c new file mode 100644 index 00000000..f4e7676a --- /dev/null +++ b/plat/arm/css/sgi/sgi_interconnect.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <debug.h> +#include <sgi_plat_config.h> + +/* + * For SGI575 which support FCM (with automatic interconnect enter/exit), + * we should not do anything in these interface functions. + * They are used to override the weak functions in cci drivers. + */ + +/****************************************************************************** + * Helper function to initialize ARM interconnect driver. + *****************************************************************************/ +void plat_arm_interconnect_init(void) +{ +} + +/****************************************************************************** + * Helper function to place current master into coherency + *****************************************************************************/ +void plat_arm_interconnect_enter_coherency(void) +{ +} + +/****************************************************************************** + * Helper function to remove current master from coherency + *****************************************************************************/ +void plat_arm_interconnect_exit_coherency(void) +{ +} diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c new file mode 100644 index 00000000..94d713d9 --- /dev/null +++ b/plat/arm/css/sgi/sgi_plat.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arm_def.h> +#include <bl_common.h> +#include <ccn.h> +#include <debug.h> +#include <plat_arm.h> +#include <platform.h> +#include "../../../../bl1/bl1_private.h" + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + +#define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__) +#endif + +#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_DEVICE | MT_RO | MT_SECURE) +/* + * Table of regions for different BL stages to map using the MMU. + * This doesn't include Trusted RAM as the 'mem_layout' argument passed to + * arm_configure_mmu_elx() will give the available subset of that. + * + * Replace or extend the below regions as required + */ +#if IMAGE_BL1 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + SGI_MAP_FLASH0_RO, + CSS_SGI_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif +#if IMAGE_BL2 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + SGI_MAP_FLASH0_RO, + CSS_SGI_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + ARM_MAP_NS_DRAM1, +#if ARM_BL31_IN_DRAM + ARM_MAP_BL31_SEC_DRAM, +#endif + {0} +}; +#endif +#if IMAGE_BL31 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_IOFPGA, + CSS_SGI_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif + +ARM_CASSERT_MMAP + +/* + * Set up the page tables for the generic and platform-specific memory regions. + * The extents of the generic memory regions are specified by the function + * arguments and consist of: + * - Trusted SRAM seen by the BL image; + * - Code section; + * - Read-only data section; + * - Coherent memory region, if applicable. + */ + +#if IMAGE_BL1 +void bl1_plat_arch_setup(void) +{ + arm_setup_page_tables(ARM_BL_RAM_BASE, + ARM_BL_RAM_SIZE, + BL_CODE_BASE, + BL1_CODE_END, + BL1_RO_DATA_BASE, + BL1_RO_DATA_END +#if USE_COHERENT_MEM + , BL1_COHERENT_RAM_BASE, + BL1_COHERENT_RAM_LIMIT +#endif /* USE_COHERENT_MEM */ + ); + + enable_mmu_el3(0); +} +#endif /* IMAGE_BL1 */ + +#if IMAGE_BL2 +void bl2_plat_arch_setup(void) +{ + arm_setup_page_tables(BL2_BASE, + BL2_LIMIT-BL2_BASE, + BL_CODE_BASE, + BL_CODE_END, + BL_RO_DATA_BASE, + BL_RO_DATA_END +#if USE_COHERENT_MEM + , BL2_COHERENT_RAM_BASE, + BL2_COHERENT_RAM_LIMIT +#endif /* USE_COHERENT_MEM */ + ); + enable_mmu_el1(0); +} +#endif /* IMAGE_BL2 */ diff --git a/plat/arm/css/sgi/sgi_plat_config.c b/plat/arm/css/sgi/sgi_plat_config.c new file mode 100644 index 00000000..96d31e21 --- /dev/null +++ b/plat/arm/css/sgi/sgi_plat_config.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <debug.h> +#include <plat_arm.h> +#include <platform_def.h> +#include <sgi_variant.h> +#include <sgi_plat_config.h> +#include <string.h> + +static css_plat_config_t *css_plat_info; + +/* GIC */ +/* The GICv3 driver only needs to be initialized in EL3 */ +uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +const interrupt_prop_t sgi575_interrupt_props[] = { + CSS_G1S_IRQ_PROPS(INTR_GROUP1S), + ARM_G0_IRQ_PROPS(INTR_GROUP0), +}; + +/* Special definition for SGI575 */ +/* GIC configuration for SGI575 */ +const gicv3_driver_data_t sgi575_gic_data = { + .gicd_base = PLAT_ARM_GICD_BASE, + .gicr_base = PLAT_ARM_GICR_BASE, + .interrupt_props = sgi575_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(sgi575_interrupt_props), + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = rdistif_base_addrs, + .mpidr_to_core_pos = plat_arm_calc_core_pos + }; + +/* Interconnect configuration for SGI575 */ +const css_inteconn_config_t sgi575_inteconn = { + .ip_type = ARM_CMN, + .plat_inteconn_desc = NULL +}; + +/* Configuration structure for SGI575 */ +css_plat_config_t sgi575_config = { + .gic_data = &sgi575_gic_data, + .inteconn = &sgi575_inteconn, +}; + +/******************************************************************************* + * This function initializes the platform sturcture. + ******************************************************************************/ +void plat_config_init(void) +{ + /* Get the platform configurations */ + switch (GET_SGI_PART_NUM) { + case SGI575_SSC_VER_PART_NUM: + css_plat_info = &sgi575_config; + break; + default: + ERROR("Not a valid sgi variant!\n"); + panic(); + } +} + +/******************************************************************************* + * This function returns the platform structure pointer. + ******************************************************************************/ +css_plat_config_t *get_plat_config(void) +{ + assert(css_plat_info != NULL); + return css_plat_info; +} diff --git a/plat/arm/css/sgi/sgi_security.c b/plat/arm/css/sgi/sgi_security.c new file mode 100644 index 00000000..23e1a64e --- /dev/null +++ b/plat/arm/css/sgi/sgi_security.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arm_config.h> +#include <plat_arm.h> + +/* + * We assume that all security programming is done by the primary core. + */ +void plat_arm_security_setup(void) +{ +} diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c new file mode 100644 index 00000000..21365911 --- /dev/null +++ b/plat/arm/css/sgi/sgi_topology.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat_arm.h> +#include <sgi_plat_config.h> + +/* Topology */ +/* + * The power domain tree descriptor. The cluster power domains are + * arranged so that when the PSCI generic code creates the power domain tree, + * the indices of the CPU power domain nodes it allocates match the linear + * indices returned by plat_core_pos_by_mpidr(). + */ +const unsigned char sgi_pd_tree_desc[] = { + PLAT_ARM_CLUSTER_COUNT, + CSS_SGI_MAX_CORES_PER_CLUSTER, + CSS_SGI_MAX_CORES_PER_CLUSTER +}; + +/* Topology configuration for sgi platform */ +const css_topology_t sgi_topology = { + .power_tree = sgi_pd_tree_desc, + .plat_cluster_core_count = CSS_SGI_MAX_CORES_PER_CLUSTER +}; + +/******************************************************************************* + * This function returns the topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return sgi_topology.power_tree; +} + +/******************************************************************************* + * This function returns the core count within the cluster corresponding to + * `mpidr`. + ******************************************************************************/ +unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) +{ + return sgi_topology.plat_cluster_core_count; +} diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c index ca6c03b0..026ea713 100644 --- a/plat/common/plat_gicv2.c +++ b/plat/common/plat_gicv2.c @@ -190,6 +190,8 @@ void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) int plat_ic_has_interrupt_type(unsigned int type) { + int has_interrupt_type = 0; + switch (type) { #if GICV2_G0_FOR_EL3 case INTR_TYPE_EL3: @@ -197,10 +199,14 @@ int plat_ic_has_interrupt_type(unsigned int type) case INTR_TYPE_S_EL1: #endif case INTR_TYPE_NS: - return 1; + has_interrupt_type = 1; + break; default: - return 0; + /* Do nothing in default case */ + break; } + + return has_interrupt_type; } void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) @@ -221,6 +227,7 @@ void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) break; default: assert(0); + break; } gicv2_set_interrupt_type(id, gicv2_type); @@ -260,6 +267,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, break; default: assert(0); + break; } gicv2_set_spi_routing(id, proc_num); diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c index 030eea72..26a4973f 100644 --- a/plat/common/plat_gicv3.c +++ b/plat/common/plat_gicv3.c @@ -158,15 +158,14 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, return __builtin_ctz(SCR_FIQ_BIT); else return __builtin_ctz(SCR_IRQ_BIT); - default: - assert(0); - /* Fall through in the release build */ case INTR_TYPE_EL3: /* * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and * NS-EL0/1/2 contexts */ return __builtin_ctz(SCR_FIQ_BIT); + default: + panic(); } } @@ -248,6 +247,7 @@ void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, break; default: assert(0); + break; } gicv3_set_spi_routing(id, irm, mpidr); diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c index b19de053..28ad9df2 100644 --- a/plat/hisilicon/hikey/hikey_bl1_setup.c +++ b/plat/hisilicon/hikey/hikey_bl1_setup.c @@ -23,23 +23,6 @@ #include "../../bl1/bl1_private.h" #include "hikey_private.h" -/* - * Declarations of linker defined symbols which will help us find the layout - * of trusted RAM - */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) - /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -103,8 +86,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } /* diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index 8bb28248..a78bb1e9 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -175,6 +175,9 @@ int hikey_bl2_handle_post_image_load(unsigned int image_id) } break; #endif + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/hisilicon/hikey960/hikey960_bl1_setup.c b/plat/hisilicon/hikey960/hikey960_bl1_setup.c index 9cadba0b..6a07f092 100644 --- a/plat/hisilicon/hikey960/hikey960_bl1_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl1_setup.c @@ -37,18 +37,6 @@ enum { * Declarations of linker defined symbols which will help us find the layout * of trusted RAM */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -131,8 +119,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } static void hikey960_ufs_reset(void) diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c index 11bbf9e1..6e726d2f 100644 --- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c @@ -267,6 +267,9 @@ int hikey960_bl2_handle_post_image_load(unsigned int image_id) } break; #endif + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/hisilicon/hikey960/hikey960_pm.c b/plat/hisilicon/hikey960/hikey960_pm.c index 22963c4f..ffe7fcf8 100644 --- a/plat/hisilicon/hikey960/hikey960_pm.c +++ b/plat/hisilicon/hikey960/hikey960_pm.c @@ -9,6 +9,7 @@ #include <cci.h> #include <console.h> #include <debug.h> +#include <delay_timer.h> #include <gicv2.h> #include <hi3660.h> #include <hi3660_crg.h> @@ -114,6 +115,9 @@ void hikey960_pwr_domain_off(const psci_power_state_t *target_state) static void __dead2 hikey960_system_reset(void) { + dsb(); + isb(); + mdelay(2000); mmio_write_32(SCTRL_SCPEREN1_REG, SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS); mmio_write_32(SCTRL_SCSYSSTAT_REG, 0xdeadbeef); diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c index 39551135..25eed593 100644 --- a/plat/hisilicon/poplar/bl1_plat_setup.c +++ b/plat/hisilicon/poplar/bl1_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,13 +23,6 @@ #include "hi3798cv200.h" #include "plat_private.h" -/* Symbols from link script for conherent section */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) - /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -92,8 +85,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, /* l-loader and BL1 ROM */ BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } void bl1_platform_setup(void) diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c index 177630b0..2671994a 100644 --- a/plat/hisilicon/poplar/bl2_plat_setup.c +++ b/plat/hisilicon/poplar/bl2_plat_setup.c @@ -193,6 +193,9 @@ int poplar_bl2_handle_post_image_load(unsigned int image_id) } break; #endif + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/mediatek/common/custom/oem_svc.c b/plat/mediatek/common/custom/oem_svc.c index 08baed87..49e7571d 100644 --- a/plat/mediatek/common/custom/oem_svc.c +++ b/plat/mediatek/common/custom/oem_svc.c @@ -41,15 +41,8 @@ uint64_t oem_smc_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - uint64_t rc; - - switch (smc_fid) { - default: - rc = SMC_UNK; - WARN("Unimplemented OEM Call: 0x%x\n", smc_fid); - } - - SMC_RET1(handle, rc); + WARN("Unimplemented OEM Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); } /* diff --git a/plat/mediatek/common/mtk_sip_svc.c b/plat/mediatek/common/mtk_sip_svc.c index beb2a697..869a9590 100644 --- a/plat/mediatek/common/mtk_sip_svc.c +++ b/plat/mediatek/common/mtk_sip_svc.c @@ -71,6 +71,9 @@ uint64_t mediatek_sip_handler(uint32_t smc_fid, boot_to_kernel(x1, x2, x3, x4); SMC_RET0(handle); #endif + default: + /* Do nothing in default case */ + break; } } diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c index 803f1ed8..32f01572 100644 --- a/plat/mediatek/mt6795/bl31_plat_setup.c +++ b/plat/mediatek/mt6795/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,22 +21,21 @@ #include <plat_private.h> #include <platform.h> #include <string.h> +#include <utils_def.h> #include <xlat_tables.h> + /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); /* * Placeholder variables for copying the arguments that have been passed to diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index 7b293077..e51bdbb9 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,24 +17,6 @@ #include <platform.h> #include <spm.h> -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted SRAM - ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL31 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) -#define BL31_END (unsigned long)(&__BL31_END__) - static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; @@ -156,10 +138,10 @@ void bl31_plat_arch_setup(void) plat_cci_init(); plat_cci_enable(); - plat_configure_mmu_el3(BL31_RO_BASE, - BL_COHERENT_RAM_END - BL31_RO_BASE, - BL31_RO_BASE, - BL31_RO_LIMIT, + plat_configure_mmu_el3(BL_CODE_BASE, + BL_COHERENT_RAM_END - BL_CODE_BASE, + BL_CODE_BASE, + BL_CODE_END, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); } diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index d89ad7b9..2fe4e7db 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,6 +23,7 @@ #include <string.h> #include <tegra_def.h> #include <tegra_private.h> +#include <utils_def.h> /* length of Trusty's input parameters (in bytes) */ #define TRUSTY_PARAMS_LEN_BYTES (4096*2) @@ -33,29 +34,17 @@ extern void zeromem16(void *mem, unsigned int length); * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ -extern unsigned long __TEXT_START__; -extern unsigned long __TEXT_END__; -extern unsigned long __RW_START__; -extern unsigned long __RW_END__; -extern unsigned long __RODATA_START__; -extern unsigned long __RODATA_END__; -extern unsigned long __BL31_END__; + +IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); +IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); +IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE); +IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END); +IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START); +IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END); extern uint64_t tegra_bl31_phys_base; extern uint64_t tegra_console_base; -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL3-1 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RW_START (unsigned long)(&__RW_START__) -#define BL31_RW_END (unsigned long)(&__RW_END__) -#define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__) -#define BL31_RODATA_END (unsigned long)(&__RODATA_END__) -#define BL31_END (unsigned long)(&__BL31_END__) static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { @@ -311,8 +300,8 @@ void bl31_plat_arch_setup(void) unsigned long rw_size = BL31_RW_END - BL31_RW_START; unsigned long rodata_start = BL31_RODATA_BASE; unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; - unsigned long code_base = (unsigned long)(&__TEXT_START__); - unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base; + unsigned long code_base = TEXT_START; + unsigned long code_size = TEXT_END - TEXT_START; const mmap_region_t *plat_mmio_map = NULL; #if USE_COHERENT_MEM unsigned long coh_start, coh_size; diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h index f8764fbf..2f2ca6f1 100644 --- a/plat/qemu/include/platform_def.h +++ b/plat/qemu/include/platform_def.h @@ -75,7 +75,7 @@ #define NS_DRAM0_SIZE 0x3de00000 #define SEC_SRAM_BASE 0x0e000000 -#define SEC_SRAM_SIZE 0x00040000 +#define SEC_SRAM_SIZE 0x00060000 #define SEC_DRAM_BASE 0x0e100000 #define SEC_DRAM_SIZE 0x00f00000 @@ -123,7 +123,7 @@ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug * size plus a little space for growth. */ -#define BL2_BASE (BL31_BASE - 0x1D000) +#define BL2_BASE (BL31_BASE - 0x25000) #define BL2_LIMIT BL31_BASE /* diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk index 017807b0..379ab3dc 100644 --- a/plat/qemu/platform.mk +++ b/plat/qemu/platform.mk @@ -169,6 +169,10 @@ $(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2)) endif SEPARATE_CODE_AND_RODATA := 1 +ENABLE_STACK_PROTECTOR := 0 +ifneq ($(ENABLE_STACK_PROTECTOR), 0) + PLAT_BL_COMMON_SOURCES += plat/qemu/qemu_stack_protector.c +endif # Use MULTI_CONSOLE_API by default only on AArch64 # as it is not yet supported on AArch32 diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c index 7650873e..997c85d7 100644 --- a/plat/qemu/qemu_bl2_setup.c +++ b/plat/qemu/qemu_bl2_setup.c @@ -287,6 +287,9 @@ static int qemu_bl2_handle_post_image_load(unsigned int image_id) bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry(); break; + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/qemu/qemu_stack_protector.c b/plat/qemu/qemu_stack_protector.c new file mode 100644 index 00000000..5b198283 --- /dev/null +++ b/plat/qemu/qemu_stack_protector.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <platform.h> +#include <stdint.h> + +#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL) + +u_register_t plat_get_stack_protector_canary(void) +{ + /* + * Ideally, a random number should be returned instead of the + * combination of a timer's value and a compile-time constant. + * As the virt platform does not have any random number generator, + * this is better than nothing but not necessarily really secure. + */ + return RANDOM_CANARY_VALUE ^ read_cntpct_el0(); +} + diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 6199edae..e5ee68f1 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,21 +17,14 @@ #include <platform_def.h> #include <uart_16550.h> -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted SRAM - ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; diff --git a/plat/rockchip/common/rockchip_sip_svc.c b/plat/rockchip/common/rockchip_sip_svc.c index 40cc94b7..eca4f99a 100644 --- a/plat/rockchip/common/rockchip_sip_svc.c +++ b/plat/rockchip/common/rockchip_sip_svc.c @@ -59,13 +59,11 @@ uint64_t sip_smc_handler(uint32_t smc_fid, case SIP_SVC_UID: /* Return UID to the caller */ SMC_UUID_RET(handle, rk_sip_svc_uid); - break; case SIP_SVC_VERSION: /* Return the version of current implementation */ SMC_RET2(handle, RK_SIP_SVC_VERSION_MAJOR, RK_SIP_SVC_VERSION_MINOR); - break; default: return rockchip_plat_sip_handler(smc_fid, x1, x2, x3, x4, diff --git a/plat/rockchip/rk3368/plat_sip_calls.c b/plat/rockchip/rk3368/plat_sip_calls.c index 7383d2f2..03fee88c 100644 --- a/plat/rockchip/rk3368/plat_sip_calls.c +++ b/plat/rockchip/rk3368/plat_sip_calls.c @@ -19,9 +19,6 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - switch (smc_fid) { - default: - ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); - SMC_RET1(handle, SMC_UNK); - } + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + SMC_RET1(handle, SMC_UNK); } diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index d629e4bf..70d9423b 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -207,6 +207,9 @@ static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, ptiming_config->rdbi = 0; ptiming_config->wdbi = 0; break; + default: + /* Do nothing in default case */ + break; } ptiming_config->dramds = drv_config->dram_side_drv; ptiming_config->dramodt = drv_config->dram_side_dq_odt; diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c index 2e196b54..3527f0e5 100644 --- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c +++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c @@ -1314,5 +1314,8 @@ void dram_get_parameter(struct timing_related_config *timing_config, case LPDDR4: lpddr4_get_parameter(timing_config, pdram_timing); break; + default: + /* Do nothing in default case */ + break; } } diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index f4893efe..ed1ea8b6 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -310,6 +310,7 @@ static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) pmu_bus_idle_req(BUS_ID_PERIHP, state); break; default: + /* Do nothing in default case */ break; } @@ -647,12 +648,8 @@ int rockchip_soc_cores_pwr_dm_off(void) int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, plat_local_state_t lvl_state) { - switch (lvl) { - case MPIDR_AFFLVL1: + if (lvl == MPIDR_AFFLVL1) { clst_pwr_domain_suspend(lvl_state); - break; - default: - break; } return PSCI_E_SUCCESS; @@ -675,12 +672,8 @@ int rockchip_soc_cores_pwr_dm_suspend(void) int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state) { - switch (lvl) { - case MPIDR_AFFLVL1: + if (lvl == MPIDR_AFFLVL1) { clst_pwr_domain_suspend(lvl_state); - break; - default: - break; } return PSCI_E_SUCCESS; @@ -698,12 +691,8 @@ int rockchip_soc_cores_pwr_dm_on_finish(void) int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, plat_local_state_t lvl_state) { - switch (lvl) { - case MPIDR_AFFLVL1: + if (lvl == MPIDR_AFFLVL1) { clst_pwr_domain_resume(lvl_state); - break; - default: - break; } return PSCI_E_SUCCESS; @@ -721,11 +710,8 @@ int rockchip_soc_cores_pwr_dm_resume(void) int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state) { - switch (lvl) { - case MPIDR_AFFLVL1: + if (lvl == MPIDR_AFFLVL1) { clst_pwr_domain_resume(lvl_state); - default: - break; } return PSCI_E_SUCCESS; @@ -1319,10 +1305,14 @@ void wdt_register_restore(void) { int i; - for (i = 0; i < 2; i++) { + for (i = 1; i >= 0; i--) { mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]); mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]); } + + /* write 0x76 to cnt_restart to keep watchdog alive */ + mmio_write_32(WDT0_BASE + 0x0c, 0x76); + mmio_write_32(WDT1_BASE + 0x0c, 0x76); } int rockchip_soc_sys_pwr_dm_suspend(void) @@ -1383,6 +1373,7 @@ int rockchip_soc_sys_pwr_dm_suspend(void) } mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); + wdt_register_save(); secure_watchdog_disable(); /* @@ -1398,7 +1389,6 @@ int rockchip_soc_sys_pwr_dm_suspend(void) suspend_uart(); grf_register_save(); cru_register_save(); - wdt_register_save(); sram_save(); plat_rockchip_save_gpio(); @@ -1411,7 +1401,6 @@ int rockchip_soc_sys_pwr_dm_resume(void) uint32_t status = 0; plat_rockchip_restore_gpio(); - wdt_register_restore(); cru_register_restore(); grf_register_restore(); resume_uart(); @@ -1426,6 +1415,7 @@ int rockchip_soc_sys_pwr_dm_resume(void) secure_watchdog_enable(); secure_sgrf_init(); secure_sgrf_ddr_rgn_init(); + wdt_register_restore(); /* restore clk_ddrc_bpll_src_en gate */ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), diff --git a/plat/rpi3/aarch64/plat_helpers.S b/plat/rpi3/aarch64/plat_helpers.S index 76a542f5..65c1bf2d 100644 --- a/plat/rpi3/aarch64/plat_helpers.S +++ b/plat/rpi3/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -137,7 +137,7 @@ func plat_crash_console_init mov_imm x0, PLAT_RPI3_UART_BASE mov_imm x1, PLAT_RPI3_UART_CLK_IN_HZ mov_imm x2, PLAT_RPI3_UART_BAUDRATE - b console_core_init + b console_16550_core_init endfunc plat_crash_console_init /* --------------------------------------------- @@ -149,7 +149,7 @@ endfunc plat_crash_console_init */ func plat_crash_console_putc mov_imm x1, PLAT_RPI3_UART_BASE - b console_core_putc + b console_16550_core_putc endfunc plat_crash_console_putc /* --------------------------------------------- @@ -161,8 +161,8 @@ endfunc plat_crash_console_putc * --------------------------------------------- */ func plat_crash_console_flush - mov_imm x1, PLAT_RPI3_UART_BASE - b console_core_flush + mov_imm x0, PLAT_RPI3_UART_BASE + b console_16550_core_flush endfunc plat_crash_console_flush /* --------------------------------------------- diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk index e201ceed..2cb7a152 100644 --- a/plat/rpi3/platform.mk +++ b/plat/rpi3/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -81,6 +81,9 @@ USE_COHERENT_MEM := 1 # Enable new version of image loading LOAD_IMAGE_V2 := 1 +# Use multi console API +MULTI_CONSOLE_API := 1 + # Platform build flags # -------------------- @@ -110,6 +113,10 @@ ifneq (${LOAD_IMAGE_V2}, 1) $(error Error: rpi3 needs LOAD_IMAGE_V2=1) endif +ifneq (${MULTI_CONSOLE_API}, 1) + $(error Error: rpi3 needs MULTI_CONSOLE_API=1) +endif + ifeq (${ARCH},aarch32) $(error Error: AArch32 not supported on rpi3) endif diff --git a/plat/rpi3/rpi3_bl1_setup.c b/plat/rpi3/rpi3_bl1_setup.c index 11c0f4af..c98715b9 100644 --- a/plat/rpi3/rpi3_bl1_setup.c +++ b/plat/rpi3/rpi3_bl1_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,6 @@ #include <arch.h> #include <arch_helpers.h> #include <bl_common.h> -#include <console.h> #include <platform_def.h> #include <xlat_mmu_helpers.h> #include <xlat_tables_defs.h> @@ -29,8 +28,7 @@ meminfo_t *bl1_plat_sec_mem_layout(void) void bl1_early_platform_setup(void) { /* Initialize the console to provide early debug support */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); + rpi3_console_init(); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = BL_RAM_BASE; diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c index 1fd822e9..f286caf0 100644 --- a/plat/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi3/rpi3_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,6 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> -#include <console.h> #include <debug.h> #include <desc_image_load.h> #include <platform_def.h> @@ -27,8 +26,7 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); void bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); + rpi3_console_init(); /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; @@ -40,7 +38,7 @@ void bl2_platform_setup(void) { /* * This is where a TrustZone address space controller and other - * security related peripherals, would be configured. + * security related peripherals would be configured. */ } @@ -83,6 +81,9 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); break; + default: + /* Do nothing in default case */ + break; } return err; diff --git a/plat/rpi3/rpi3_bl31_setup.c b/plat/rpi3/rpi3_bl31_setup.c index 39133564..58344ae9 100644 --- a/plat/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi3/rpi3_bl31_setup.c @@ -1,12 +1,11 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> #include <bl_common.h> -#include <console.h> #include <platform.h> #include <platform_def.h> #include <xlat_mmu_helpers.h> @@ -58,8 +57,7 @@ void bl31_early_platform_setup(void *from_bl2, void *plat_params_from_bl2) { /* Initialize the console to provide early debug support */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); + rpi3_console_init(); #if RESET_TO_BL31 @@ -159,10 +157,3 @@ void bl31_platform_setup(void) return; } - -void bl31_plat_runtime_setup(void) -{ - /* Initialize the runtime console */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); -} diff --git a/plat/rpi3/rpi3_common.c b/plat/rpi3/rpi3_common.c index 97dce091..03914a6d 100644 --- a/plat/rpi3/rpi3_common.c +++ b/plat/rpi3/rpi3_common.c @@ -1,14 +1,16 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch_helpers.h> #include <bl_common.h> +#include <console.h> #include <debug.h> #include <interrupt_mgmt.h> #include <platform_def.h> +#include <uart_16550.h> #include <xlat_tables_v2.h> #include "rpi3_hw.h" @@ -69,6 +71,30 @@ static const mmap_region_t plat_rpi3_mmap[] = { #endif /******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_16550_t rpi3_console; + +void rpi3_console_init(void) +{ + int rc = console_16550_register(PLAT_RPI3_UART_BASE, + PLAT_RPI3_UART_CLK_IN_HZ, + PLAT_RPI3_UART_BAUDRATE, + &rpi3_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&rpi3_console.console, + CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); +} + +/******************************************************************************* * Function that sets up the translation tables. ******************************************************************************/ void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, diff --git a/plat/rpi3/rpi3_private.h b/plat/rpi3/rpi3_private.h index 01c4055f..a9fbfe47 100644 --- a/plat/rpi3/rpi3_private.h +++ b/plat/rpi3/rpi3_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ ******************************************************************************/ /* Utility functions */ +void rpi3_console_init(void); void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, uintptr_t code_start, uintptr_t code_limit, uintptr_t rodata_start, uintptr_t rodata_limit diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c index 54b30e5b..f7ae4264 100644 --- a/plat/socionext/uniphier/uniphier_bl2_setup.c +++ b/plat/socionext/uniphier/uniphier_bl2_setup.c @@ -85,6 +85,7 @@ void bl2_el3_plat_arch_setup(void) break; default: plat_error_handler(-ENOTSUP); + break; } if (!skip_scp) { diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index d7a7d4e2..fd054beb 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -48,6 +48,9 @@ unsigned int zynqmp_get_uart_clk(void) return 25000000; case ZYNQMP_CSU_VERSION_QEMU: return 133000000; + default: + /* Do nothing in default case */ + break; } return 100000000; @@ -187,6 +190,9 @@ static void zynqmp_print_platform_name(void) case ZYNQMP_CSU_VERSION_SILICON: label = "silicon"; break; + default: + /* Do nothing in default case */ + break; } NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x%s\n", @@ -258,6 +264,9 @@ unsigned int plat_get_syscnt_freq2(void) return 4000000; case ZYNQMP_CSU_VERSION_QEMU: return 50000000; + default: + /* Do nothing in default case */ + break; } return mmio_read_32(IOU_SCNTRS_BASEFREQ); diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c index 13a307a2..3d679806 100644 --- a/services/spd/opteed/opteed_main.c +++ b/services/spd/opteed/opteed_main.c @@ -311,6 +311,7 @@ uint64_t opteed_smc_handler(uint32_t smc_fid, * OPTEE. Jump back to the original C runtime context. */ opteed_synchronous_sp_exit(optee_ctx, x1); + break; /* @@ -345,6 +346,7 @@ uint64_t opteed_smc_handler(uint32_t smc_fid, * return value to the caller */ opteed_synchronous_sp_exit(optee_ctx, x1); + break; /* * OPTEE is returning from a call or being preempted from a call, in diff --git a/services/spd/tlkd/tlkd_common.c b/services/spd/tlkd/tlkd_common.c index 483d45b6..d846269b 100644 --- a/services/spd/tlkd/tlkd_common.c +++ b/services/spd/tlkd/tlkd_common.c @@ -49,6 +49,7 @@ uint64_t tlkd_va_translate(uintptr_t va, int type) break; default: assert(0); + break; } /* get the (NS/S) physical address */ diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c index cb68bff7..da3b732e 100644 --- a/services/spd/tlkd/tlkd_main.c +++ b/services/spd/tlkd/tlkd_main.c @@ -350,6 +350,7 @@ uint64_t tlkd_smc_handler(uint32_t smc_fid, * context. */ tlkd_synchronous_sp_exit(&tlk_ctx, x1); + break; /* * These function IDs are used only by TLK to indicate it has @@ -375,6 +376,7 @@ uint64_t tlkd_smc_handler(uint32_t smc_fid, * return value to the caller */ tlkd_synchronous_sp_exit(&tlk_ctx, x1); + break; /* * Return the number of service function IDs implemented to diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c index 3d06e0b8..2312205c 100644 --- a/services/spd/tspd/tspd_main.c +++ b/services/spd/tspd/tspd_main.c @@ -435,6 +435,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid, * context. */ tspd_synchronous_sp_exit(tsp_ctx, x1); + break; #endif /* * This function ID is used only by the SP to indicate it has finished @@ -475,6 +476,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid, * return value to the caller */ tspd_synchronous_sp_exit(tsp_ctx, x1); + break; /* * Request from non-secure client to perform an @@ -591,7 +593,6 @@ uint64_t tspd_smc_handler(uint32_t smc_fid, SMC_RET3(ns_cpu_context, x1, x2, x3); } - break; /* * Request from the non-secure world to abort a preempted Yielding SMC * Call. diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c index 1969307f..9589a252 100644 --- a/services/std_svc/sdei/sdei_main.c +++ b/services/std_svc/sdei/sdei_main.c @@ -916,7 +916,6 @@ uint64_t sdei_smc_handler(uint32_t smc_fid, ret = sdei_version(); SDEI_LOG("< VER:%lx\n", ret); SMC_RET1(handle, ret); - break; case SDEI_EVENT_REGISTER: x5 = SMC_GET_GP(handle, CTX_GPREG_X5); @@ -925,32 +924,27 @@ uint64_t sdei_smc_handler(uint32_t smc_fid, ret = sdei_event_register(x1, x2, x3, x4, x5); SDEI_LOG("< REG:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_EVENT_ENABLE: SDEI_LOG("> ENABLE(n:%d)\n", (int) x1); ret = sdei_event_enable(x1); SDEI_LOG("< ENABLE:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_EVENT_DISABLE: SDEI_LOG("> DISABLE(n:%d)\n", (int) x1); ret = sdei_event_disable(x1); SDEI_LOG("< DISABLE:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_EVENT_CONTEXT: SDEI_LOG("> CTX(p:%d):%lx\n", (int) x1, read_mpidr_el1()); ret = sdei_event_context(handle, x1); SDEI_LOG("< CTX:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_EVENT_COMPLETE_AND_RESUME: resume = 1; - /* Fall through */ case SDEI_EVENT_COMPLETE: SDEI_LOG("> COMPLETE(r:%d sta/ep:%lx):%lx\n", resume, x1, @@ -969,92 +963,81 @@ uint64_t sdei_smc_handler(uint32_t smc_fid, SMC_RET1(handle, ret); SMC_RET0(handle); - break; case SDEI_EVENT_STATUS: SDEI_LOG("> STAT(n:%d)\n", (int) x1); ret = sdei_event_status(x1); SDEI_LOG("< STAT:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_EVENT_GET_INFO: SDEI_LOG("> INFO(n:%d, %d)\n", (int) x1, (int) x2); ret = sdei_event_get_info(x1, x2); SDEI_LOG("< INFO:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_EVENT_UNREGISTER: SDEI_LOG("> UNREG(n:%d)\n", (int) x1); ret = sdei_event_unregister(x1); SDEI_LOG("< UNREG:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_PE_UNMASK: SDEI_LOG("> UNMASK:%lx\n", read_mpidr_el1()); sdei_pe_unmask(); SDEI_LOG("< UNMASK:%d\n", 0); SMC_RET1(handle, 0); - break; case SDEI_PE_MASK: SDEI_LOG("> MASK:%lx\n", read_mpidr_el1()); ret = sdei_pe_mask(); SDEI_LOG("< MASK:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_INTERRUPT_BIND: SDEI_LOG("> BIND(%d)\n", (int) x1); ret = sdei_interrupt_bind(x1); SDEI_LOG("< BIND:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_INTERRUPT_RELEASE: SDEI_LOG("> REL(%d)\n", (int) x1); ret = sdei_interrupt_release(x1); SDEI_LOG("< REL:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_SHARED_RESET: SDEI_LOG("> S_RESET():%lx\n", read_mpidr_el1()); ret = sdei_shared_reset(); SDEI_LOG("< S_RESET:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_PRIVATE_RESET: SDEI_LOG("> P_RESET():%lx\n", read_mpidr_el1()); ret = sdei_private_reset(); SDEI_LOG("< P_RESET:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_EVENT_ROUTING_SET: SDEI_LOG("> ROUTE_SET(n:%d f:%lx aff:%lx)\n", (int) x1, x2, x3); ret = sdei_event_routing_set(x1, x2, x3); SDEI_LOG("< ROUTE_SET:%ld\n", ret); SMC_RET1(handle, ret); - break; case SDEI_FEATURES: SDEI_LOG("> FTRS(f:%lx)\n", x1); ret = sdei_features(x1); SDEI_LOG("< FTRS:%lx\n", ret); SMC_RET1(handle, ret); - break; case SDEI_EVENT_SIGNAL: SDEI_LOG("> SIGNAL(e:%lx t:%lx)\n", x1, x2); ret = sdei_signal(x1, x2); SDEI_LOG("< SIGNAL:%ld\n", ret); SMC_RET1(handle, ret); - break; + default: + /* Do nothing in default case */ break; } diff --git a/services/std_svc/spm/spm_shim_private.h b/services/std_svc/spm/spm_shim_private.h index ad953cde..8408d1e0 100644 --- a/services/std_svc/spm/spm_shim_private.h +++ b/services/std_svc/spm/spm_shim_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,21 +8,17 @@ #define __SPM_SHIM_PRIVATE__ #include <types.h> +#include <utils_def.h> /* Assembly source */ -extern uintptr_t spm_shim_exceptions_ptr; +IMPORT_SYM(uintptr_t, spm_shim_exceptions_ptr, SPM_SHIM_EXCEPTIONS_PTR); /* Linker symbols */ -extern uintptr_t __SPM_SHIM_EXCEPTIONS_START__; -extern uintptr_t __SPM_SHIM_EXCEPTIONS_END__; +IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START); +IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); /* Definitions */ -#define SPM_SHIM_EXCEPTIONS_PTR (uintptr_t)(&spm_shim_exceptions_ptr) -#define SPM_SHIM_EXCEPTIONS_START \ - (uintptr_t)(&__SPM_SHIM_EXCEPTIONS_START__) -#define SPM_SHIM_EXCEPTIONS_END \ - (uintptr_t)(&__SPM_SHIM_EXCEPTIONS_END__) #define SPM_SHIM_EXCEPTIONS_SIZE \ (SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START) |