diff options
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.c | 2 | ||||
| -rw-r--r-- | plat/rockchip/rk3399/drivers/soc/soc.c | 51 | ||||
| -rw-r--r-- | plat/rockchip/rk3399/drivers/soc/soc.h | 2 |
3 files changed, 0 insertions, 55 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 3631a304..05ca7fdd 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -1150,7 +1150,6 @@ static int sys_pwr_domain_suspend(void) * Disabling PLLs/PWM/DVFS is approaching WFI which is * the last steps in suspend. */ - plls_suspend_prepare(); disable_dvfs_plls(); disable_pwms(); disable_nodvfs_plls(); @@ -1173,7 +1172,6 @@ static int sys_pwr_domain_resume(void) /* PWM regulators take time to come up; give 300us to be safe. */ udelay(300); enable_dvfs_plls(); - plls_resume_finish(); secure_watchdog_restore(); diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c index f77b74f2..c769b73b 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.c +++ b/plat/rockchip/rk3399/drivers/soc/soc.c @@ -214,20 +214,6 @@ void secure_watchdog_restore(void) WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT)); } -static void pll_suspend_prepare(uint32_t pll_id) -{ - int i; - - if (pll_id == PPLL_ID) - for (i = 0; i < PLL_CON_COUNT; i++) - slp_data.plls_con[pll_id][i] = - mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); - else - for (i = 0; i < PLL_CON_COUNT; i++) - slp_data.plls_con[pll_id][i] = - mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); -} - static void set_pll_slow_mode(uint32_t pll_id) { if (pll_id == PPLL_ID) @@ -361,23 +347,6 @@ void restore_dpll(void) restore_pll(DPLL_ID, slp_data.plls_con[DPLL_ID]); } -void plls_suspend_prepare(void) -{ - uint32_t i, pll_id; - - for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) - pll_suspend_prepare(pll_id); - - for (i = 0; i < CRU_CLKSEL_COUNT; i++) - slp_data.cru_clksel_con[i] = - mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(i)); - - for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) - slp_data.pmucru_clksel_con[i] = - mmio_read_32(PMUCRU_BASE + - PMUCRU_CLKSEL_OFFSET + i * REG_SIZE); -} - void clk_gate_con_save(void) { uint32_t i = 0; @@ -431,26 +400,6 @@ static void _pll_resume(uint32_t pll_id) set_pll_normal_mode(pll_id); } -void plls_resume_finish(void) -{ - int i; - - for (i = 0; i < CRU_CLKSEL_COUNT; i++) { - /* CRU_CLKSEL_CON96~107 the high 16-bit isb't write_mask */ - if (i > 95) - mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), - slp_data.cru_clksel_con[i]); - else - mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), - REG_SOC_WMSK | - slp_data.cru_clksel_con[i]); - } - for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) - mmio_write_32((PMUCRU_BASE + - PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), - REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]); -} - /** * enable_dvfs_plls - To resume the specific PLLs * diff --git a/plat/rockchip/rk3399/drivers/soc/soc.h b/plat/rockchip/rk3399/drivers/soc/soc.h index bbca7bc0..742bb7b7 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.h +++ b/plat/rockchip/rk3399/drivers/soc/soc.h @@ -348,10 +348,8 @@ static inline void pmu_sgrf_rst_hld(void) void __dead2 soc_global_soft_reset(void); void secure_watchdog_disable(); void secure_watchdog_restore(); -void plls_suspend_prepare(void); void disable_dvfs_plls(void); void disable_nodvfs_plls(void); -void plls_resume_finish(void); void enable_dvfs_plls(void); void enable_nodvfs_plls(void); void prepare_abpll_for_ddrctrl(void); |