diff options
24 files changed, 482 insertions, 160 deletions
diff --git a/include/plat/arm/common/arm_config.h b/include/plat/arm/common/arm_config.h index 0b161276..24c1f0a1 100644 --- a/include/plat/arm/common/arm_config.h +++ b/include/plat/arm/common/arm_config.h @@ -42,12 +42,6 @@ enum arm_config_flags { }; typedef struct arm_config { - uintptr_t gicd_base; - uintptr_t gicc_base; - uintptr_t gich_base; - uintptr_t gicv_base; - unsigned int max_aff0; - unsigned int max_aff1; unsigned long flags; } arm_config_t; diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 4726d5e5..5c03feb9 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -135,6 +135,22 @@ #define ARM_IRQ_SEC_SGI_6 14 #define ARM_IRQ_SEC_SGI_7 15 +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ + ARM_IRQ_SEC_SGI_1, \ + ARM_IRQ_SEC_SGI_2, \ + ARM_IRQ_SEC_SGI_3, \ + ARM_IRQ_SEC_SGI_4, \ + ARM_IRQ_SEC_SGI_5, \ + ARM_IRQ_SEC_SGI_7 + +#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ + ARM_IRQ_SEC_SGI_6 + #define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \ MT_MEMORY : MT_DEVICE) \ | MT_RW | MT_SECURE) diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index aadf58d8..f0b3ff67 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -37,7 +37,6 @@ #include <stdint.h> #include <xlat_tables.h> - /* * Extern declarations common to ARM standard platforms */ @@ -179,7 +178,11 @@ void arm_tsp_early_platform_setup(void); /* * Mandatory functions required in ARM standard platforms */ +void plat_arm_gic_driver_init(void); void plat_arm_gic_init(void); +void plat_arm_gic_cpuif_enable(void); +void plat_arm_gic_cpuif_disable(void); +void plat_arm_gic_pcpu_init(void); void plat_arm_security_setup(void); void plat_arm_pwrc_setup(void); diff --git a/include/plat/arm/css/common/aarch64/css_macros.S b/include/plat/arm/css/common/aarch64/css_macros.S index 2a26eb70..9f18e09c 100644 --- a/include/plat/arm/css/common/aarch64/css_macros.S +++ b/include/plat/arm/css/common/aarch64/css_macros.S @@ -41,8 +41,8 @@ * --------------------------------------------- */ .macro plat_print_gic_regs - mov_imm x16, PLAT_CSS_GICD_BASE - mov_imm x17, PLAT_CSS_GICC_BASE + mov_imm x16, PLAT_ARM_GICD_BASE + mov_imm x17, PLAT_ARM_GICC_BASE arm_print_gic_regs .endm diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 98b69cb3..99491f88 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -61,6 +61,16 @@ #define CSS_IRQ_SEC_SYS_TIMER 91 /* + * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a + * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. + */ +#define CSS_G1S_IRQS CSS_IRQ_MHU, \ + CSS_IRQ_GPU_SMMU_0, \ + CSS_IRQ_TZC, \ + CSS_IRQ_TZ_WDOG, \ + CSS_IRQ_SEC_SYS_TIMER + +/* * SCP <=> AP boot configuration * * The SCP/AP boot configuration is a 32-bit word located at a known offset from diff --git a/plat/arm/board/fvp/aarch64/fvp_common.c b/plat/arm/board/fvp/aarch64/fvp_common.c index 8771e5b4..e089405d 100644 --- a/plat/arm/board/fvp/aarch64/fvp_common.c +++ b/plat/arm/board/fvp/aarch64/fvp_common.c @@ -30,14 +30,23 @@ #include <arm_config.h> #include <arm_def.h> -#include <arm_gic.h> #include <cci.h> #include <debug.h> +#include <gicv2.h> #include <mmio.h> #include <plat_arm.h> #include <v2m_def.h> #include "../fvp_def.h" +#if (FVP_USE_GIC_DRIVER == FVP_GICV2) +extern gicv2_driver_data_t arm_gic_data; +#endif + +/* Defines for GIC Driver build time selection */ +#define FVP_GICV2 1 +#define FVP_GICV3 2 +#define FVP_GICV3_LEGACY 3 + /******************************************************************************* * arm_config holds the characteristics of the differences between the three FVP * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot @@ -110,33 +119,6 @@ const mmap_region_t plat_arm_mmap[] = { ARM_CASSERT_MMAP -#if IMAGE_BL31 || IMAGE_BL32 -/* Array of secure interrupts to be configured by the gic driver */ -const unsigned int irq_sec_array[] = { - ARM_IRQ_SEC_PHY_TIMER, - ARM_IRQ_SEC_SGI_0, - ARM_IRQ_SEC_SGI_1, - ARM_IRQ_SEC_SGI_2, - ARM_IRQ_SEC_SGI_3, - ARM_IRQ_SEC_SGI_4, - ARM_IRQ_SEC_SGI_5, - ARM_IRQ_SEC_SGI_6, - ARM_IRQ_SEC_SGI_7, - FVP_IRQ_TZ_WDOG, - FVP_IRQ_SEC_SYS_TIMER -}; - -void plat_arm_gic_init(void) -{ - arm_gic_init(arm_config.gicc_base, - arm_config.gicd_base, - BASE_GICR_BASE, - irq_sec_array, - ARRAY_SIZE(irq_sec_array)); -} - -#endif - /******************************************************************************* * A single boot loader stack is expected to work on both the Foundation FVP * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The @@ -165,16 +147,28 @@ void fvp_config_setup(void) */ switch (bld) { case BLD_GIC_VE_MMAP: - arm_config.gicd_base = VE_GICD_BASE; - arm_config.gicc_base = VE_GICC_BASE; - arm_config.gich_base = VE_GICH_BASE; - arm_config.gicv_base = VE_GICV_BASE; +#if IMAGE_BL31 || IMAGE_BL32 +#if FVP_USE_GIC_DRIVER == FVP_GICV2 + /* + * If the FVP implements the VE compatible memory map, then the + * GICv2 driver must be included in the build. Update the platform + * data with the correct GICv2 base addresses before it is used + * to initialise the driver. + * + * This update of platform data is temporary and will be removed + * once VE memory map for FVP is no longer supported by Trusted + * Firmware. + */ + arm_gic_data.gicd_base = VE_GICD_BASE; + arm_gic_data.gicc_base = VE_GICC_BASE; + +#else + ERROR("Only GICv2 driver supported for VE memory map\n"); + panic(); +#endif /* __FVP_USE_GIC_DRIVER == FVP_GICV2__ */ +#endif /* __IMAGE_BL31 || IMAGE_BL32__ */ break; case BLD_GIC_A53A57_MMAP: - arm_config.gicd_base = BASE_GICD_BASE; - arm_config.gicc_base = BASE_GICC_BASE; - arm_config.gich_base = BASE_GICH_BASE; - arm_config.gicv_base = BASE_GICV_BASE; break; default: ERROR("Unsupported board build %x\n", bld); @@ -187,8 +181,6 @@ void fvp_config_setup(void) */ switch (hbi) { case HBI_FOUNDATION_FVP: - arm_config.max_aff0 = 4; - arm_config.max_aff1 = 1; arm_config.flags = 0; /* @@ -206,8 +198,6 @@ void fvp_config_setup(void) } break; case HBI_BASE_FVP: - arm_config.max_aff0 = 4; - arm_config.max_aff1 = 2; arm_config.flags |= ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_CCI | ARM_CONFIG_HAS_TZC; diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index d7b459d7..c5129a60 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c @@ -30,7 +30,6 @@ #include <arch_helpers.h> #include <arm_config.h> -#include <arm_gic.h> #include <assert.h> #include <debug.h> #include <errno.h> @@ -72,7 +71,7 @@ const unsigned int arm_pm_idle_states[] = { static void fvp_cpu_pwrdwn_common(void) { /* Prevent interrupts from spuriously waking up this cpu */ - arm_gic_cpuif_deactivate(); + plat_arm_gic_cpuif_disable(); /* Program the power controller to power off this cpu. */ fvp_pwrc_write_ppoffr(read_mpidr_el1()); @@ -235,9 +234,10 @@ void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) fvp_power_domain_on_finish_common(target_state); /* Enable the gic cpu interface */ - arm_gic_cpuif_setup(); - /* Program the gic per-cpu distributor interface */ - arm_gic_pcpu_distif_setup(); + plat_arm_gic_pcpu_init(); + + /* Program the gic per-cpu distributor or re-distributor interface */ + plat_arm_gic_cpuif_enable(); } /******************************************************************************* @@ -259,7 +259,7 @@ void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) fvp_power_domain_on_finish_common(target_state); /* Enable the gic cpu interface */ - arm_gic_cpuif_setup(); + plat_arm_gic_cpuif_enable(); } /******************************************************************************* diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 9ada6b2a..9cb88de5 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -121,5 +121,24 @@ TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) +/* + * GIC related constants to cater for both GICv2 and GICv3 instances of an + * FVP. They could be overriden at runtime in case the FVP implements the legacy + * VE memory map. + */ +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICR_BASE BASE_GICR_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ + FVP_IRQ_TZ_WDOG, \ + FVP_IRQ_SEC_SYS_TIMER + +#define PLAT_ARM_G0_IRQS ARM_G0_IRQS #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index c46d3b71..b6f07394 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -28,6 +28,35 @@ # POSSIBILITY OF SUCH DAMAGE. # +# Use the Legacy GICv3 driver on the FVP by default to maintain compatibility. +FVP_USE_GIC_DRIVER := FVP_GICV3_LEGACY + +# The FVP platform depends on this macro to build with correct GIC driver. +$(eval $(call add_define,FVP_USE_GIC_DRIVER)) + +# Choose the GIC sources depending upon the how the FVP will be invoked +ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) +FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/v3/gicv3_helpers.c \ + plat/common/plat_gicv3.c \ + plat/arm/common/arm_gicv3.c +else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) +FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c \ + plat/arm/common/arm_gicv2.c +else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3_LEGACY) +FVP_GIC_SOURCES := drivers/arm/gic/arm_gic.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + plat/common/plat_gic.c \ + plat/arm/common/arm_gicv3_legacy.c +else +$(error "Incorrect GIC driver chosen on FVP port") +endif + PLAT_INCLUDES := -Iplat/arm/board/fvp/include @@ -62,7 +91,8 @@ BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ plat/arm/board/fvp/fvp_security.c \ plat/arm/board/fvp/fvp_topology.c \ plat/arm/board/fvp/aarch64/fvp_helpers.S \ - plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c + plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \ + ${FVP_GIC_SOURCES} # Disable the PSCI platform compatibility layer ENABLE_PLAT_COMPAT := 0 diff --git a/plat/arm/board/fvp/tsp/tsp-fvp.mk b/plat/arm/board/fvp/tsp/tsp-fvp.mk index 99db2f49..54a76fde 100644 --- a/plat/arm/board/fvp/tsp/tsp-fvp.mk +++ b/plat/arm/board/fvp/tsp/tsp-fvp.mk @@ -31,6 +31,7 @@ # TSP source files specific to FVP platform BL32_SOURCES += plat/arm/board/fvp/fvp_topology.c \ plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \ - plat/arm/board/fvp/tsp/fvp_tsp_setup.c + plat/arm/board/fvp/tsp/fvp_tsp_setup.c \ + ${FVP_GIC_SOURCES} include plat/arm/common/tsp/arm_tsp.mk diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 39283c56..924eb0ab 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -94,17 +94,18 @@ */ /* GIC related constants (no GICR in GIC-400) */ -#define PLAT_CSS_GICD_BASE 0x2c010000 -#define PLAT_CSS_GICR_BASE 0x0 -#define PLAT_CSS_GICC_BASE 0x2c02f000 -#define PLAT_CSS_GICH_BASE 0x2c04f000 -#define PLAT_CSS_GICV_BASE 0x2c06f000 - -#define PLAT_CSS_IRQ_SEC_LIST CSS_IRQ_MHU, \ - CSS_IRQ_GPU_SMMU_0, \ - CSS_IRQ_TZC, \ - CSS_IRQ_TZ_WDOG, \ - CSS_IRQ_SEC_SYS_TIMER, \ +#define PLAT_ARM_GICD_BASE 0x2c010000 +#define PLAT_ARM_GICC_BASE 0x2c02f000 +#define PLAT_ARM_GICH_BASE 0x2c04f000 +#define PLAT_ARM_GICV_BASE 0x2c06f000 + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ + ARM_G1S_IRQS, \ JUNO_IRQ_DMA_SMMU, \ JUNO_IRQ_HDLCD0_SMMU, \ JUNO_IRQ_HDLCD1_SMMU, \ @@ -114,6 +115,8 @@ JUNO_IRQ_GPU_SMMU_1, \ JUNO_IRQ_ETR_SMMU +#define PLAT_ARM_G0_IRQS ARM_G0_IRQS + /* * Required ARM CSS SoC based platform porting definitions */ diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index 127dcbea..0212fdde 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -28,6 +28,12 @@ # POSSIBILITY OF SUCH DAMAGE. # +JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c \ + plat/arm/common/arm_gicv2.c + PLAT_INCLUDES := -Iplat/arm/board/juno/include PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S @@ -44,7 +50,8 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ plat/arm/board/juno/juno_pm.c \ - plat/arm/board/juno/juno_security.c + plat/arm/board/juno/juno_security.c \ + ${JUNO_GIC_SOURCES} # Enable workarounds for selected Cortex-A57 erratas. ERRATA_A57_806969 := 0 diff --git a/plat/arm/board/juno/tsp/tsp-juno.mk b/plat/arm/board/juno/tsp/tsp-juno.mk index bb67012f..2ef964e8 100644 --- a/plat/arm/board/juno/tsp/tsp-juno.mk +++ b/plat/arm/board/juno/tsp/tsp-juno.mk @@ -28,6 +28,7 @@ # POSSIBILITY OF SUCH DAMAGE. # -BL32_SOURCES += plat/arm/css/common/css_topology.c +BL32_SOURCES += plat/arm/css/common/css_topology.c \ + ${JUNO_GIC_SOURCES} include plat/arm/common/tsp/arm_tsp.mk diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 8682fd19..50b98c70 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -31,7 +31,6 @@ #include <arch.h> #include <arch_helpers.h> #include <arm_def.h> -#include <arm_gic.h> #include <assert.h> #include <bl_common.h> #include <cci.h> @@ -200,9 +199,9 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, ******************************************************************************/ void arm_bl31_platform_setup(void) { - /* Initialize the gic cpu and distributor interfaces */ + /* Initialize the GIC driver, cpu and distributor interfaces */ + plat_arm_gic_driver_init(); plat_arm_gic_init(); - arm_gic_setup(); #if RESET_TO_BL31 /* diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 1290cef3..1336e230 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -108,15 +108,11 @@ BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ BL31_SOURCES += drivers/arm/cci/cci.c \ drivers/arm/ccn/ccn.c \ - drivers/arm/gic/arm_gic.c \ - drivers/arm/gic/gic_v2.c \ - drivers/arm/gic/gic_v3.c \ drivers/arm/tzc400/tzc400.c \ plat/arm/common/arm_bl31_setup.c \ plat/arm/common/arm_pm.c \ plat/arm/common/arm_security.c \ plat/arm/common/arm_topology.c \ - plat/common/plat_gic.c \ plat/common/aarch64/platform_mp_stack.S \ plat/common/aarch64/plat_psci_common.c @@ -127,9 +123,9 @@ ifneq (${TRUSTED_BOARD_BOOT},0) # Include common TBB sources AUTH_SOURCES := drivers/auth/auth_mod.c \ - drivers/auth/crypto_mod.c \ - drivers/auth/img_parser_mod.c \ - drivers/auth/tbbr/tbbr_cot.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c \ + drivers/auth/tbbr/tbbr_cot.c \ BL1_SOURCES += ${AUTH_SOURCES} BL2_SOURCES += ${AUTH_SOURCES} diff --git a/plat/arm/common/arm_gicv2.c b/plat/arm/common/arm_gicv2.c new file mode 100644 index 00000000..76f04cd0 --- /dev/null +++ b/plat/arm/common/arm_gicv2.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <gicv2.h> +#include <plat_arm.h> +#include <platform.h> +#include <platform_def.h> + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way the GICv2 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_arm_gic_driver_init +#pragma weak plat_arm_gic_init +#pragma weak plat_arm_gic_cpuif_enable +#pragma weak plat_arm_gic_cpuif_disable +#pragma weak plat_arm_gic_pcpu_init + +/****************************************************************************** + * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 + * interrupts. + *****************************************************************************/ +const unsigned int g0_interrupt_array[] = { + PLAT_ARM_G1S_IRQS, + PLAT_ARM_G0_IRQS +}; + +/* + * Ideally `arm_gic_data` structure definition should be a `const` but it is + * kept as modifiable for overwriting with different GICD and GICC base when + * running on FVP with VE memory map. + */ +gicv2_driver_data_t arm_gic_data = { + .gicd_base = PLAT_ARM_GICD_BASE, + .gicc_base = PLAT_ARM_GICC_BASE, + .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), + .g0_interrupt_array = g0_interrupt_array, +}; + +/****************************************************************************** + * ARM common helper to initialize the GICv2 only driver. + *****************************************************************************/ +void plat_arm_gic_driver_init(void) +{ + gicv2_driver_init(&arm_gic_data); +} + +void plat_arm_gic_init(void) +{ + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * ARM common helper to enable the GICv2 CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_enable(void) +{ + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * ARM common helper to disable the GICv2 CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_disable(void) +{ + gicv2_cpuif_disable(); +} + +/****************************************************************************** + * ARM common helper to initialize the per cpu distributor interface in GICv2 + *****************************************************************************/ +void plat_arm_gic_pcpu_init(void) +{ + gicv2_pcpu_distif_init(); +} diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c new file mode 100644 index 00000000..33f80183 --- /dev/null +++ b/plat/arm/common/arm_gicv3.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arm_def.h> +#include <gicv3.h> +#include <plat_arm.h> +#include <platform.h> +#include <platform_def.h> + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way the GICv3 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_arm_gic_driver_init +#pragma weak plat_arm_gic_init +#pragma weak plat_arm_gic_cpuif_enable +#pragma weak plat_arm_gic_cpuif_disable +#pragma weak plat_arm_gic_pcpu_init + +/* The GICv3 driver only needs to be initialized in EL3 */ +uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +/* Array of Group1 secure interrupts to be configured by the gic driver */ +const unsigned int g1s_interrupt_array[] = { + PLAT_ARM_G1S_IRQS +}; + +/* Array of Group0 interrupts to be configured by the gic driver */ +const unsigned int g0_interrupt_array[] = { + PLAT_ARM_G0_IRQS +}; + +const gicv3_driver_data_t arm_gic_data = { + .gicd_base = PLAT_ARM_GICD_BASE, + .gicr_base = PLAT_ARM_GICR_BASE, + .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), + .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), + .g0_interrupt_array = g0_interrupt_array, + .g1s_interrupt_array = g1s_interrupt_array, + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = rdistif_base_addrs, + .mpidr_to_core_pos = plat_arm_calc_core_pos +}; + +void plat_arm_gic_driver_init(void) +{ + /* + * The GICv3 driver is initialized in EL3 and does not need + * to be initialized again in SEL1. This is because the S-EL1 + * can use GIC system registers to manage interrupts and does + * not need GIC interface base addresses to be configured. + */ +#if IMAGE_BL31 + gicv3_driver_init(&arm_gic_data); +#endif +} + +/****************************************************************************** + * ARM common helper to initialize the GIC. Only invoked by BL31 + *****************************************************************************/ +void plat_arm_gic_init(void) +{ + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * ARM common helper to enable the GIC CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_enable(void) +{ + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * ARM common helper to disable the GIC CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_disable(void) +{ + gicv3_cpuif_disable(plat_my_core_pos()); +} + +/****************************************************************************** + * ARM common helper to initialize the per-cpu redistributor interface in GICv3 + *****************************************************************************/ +void plat_arm_gic_pcpu_init(void) +{ + gicv3_rdistif_init(plat_my_core_pos()); +} diff --git a/plat/arm/common/arm_gicv3_legacy.c b/plat/arm/common/arm_gicv3_legacy.c new file mode 100644 index 00000000..61709334 --- /dev/null +++ b/plat/arm/common/arm_gicv3_legacy.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arm_def.h> +#include <arm_gic.h> +#include <plat_arm.h> +#include <platform.h> +#include <platform_def.h> + +/****************************************************************************** + * The following function is defined as weak to allow a platform to override + * the way the Legacy GICv3 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_arm_gic_driver_init +#pragma weak plat_arm_gic_init +#pragma weak plat_arm_gic_cpuif_enable +#pragma weak plat_arm_gic_cpuif_disable +#pragma weak plat_arm_gic_pcpu_init + +/* + * In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group + * 0 interrupts. + */ +const unsigned int irq_sec_array[] = { + PLAT_ARM_G0_IRQS, + PLAT_ARM_G1S_IRQS +}; + +void plat_arm_gic_driver_init(void) +{ + arm_gic_init(PLAT_ARM_GICC_BASE, + PLAT_ARM_GICD_BASE, + PLAT_ARM_GICR_BASE, + irq_sec_array, + ARRAY_SIZE(irq_sec_array)); +} + +/****************************************************************************** + * ARM common helper to initialize the GIC. + *****************************************************************************/ +void plat_arm_gic_init(void) +{ + arm_gic_setup(); +} + +/****************************************************************************** + * ARM common helper to enable the GIC CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_enable(void) +{ + arm_gic_cpuif_setup(); +} + +/****************************************************************************** + * ARM common helper to disable the GIC CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_disable(void) +{ + arm_gic_cpuif_deactivate(); +} + +/****************************************************************************** + * ARM common helper to initialize the per-cpu distributor in GICv2 or + * redistributor interface in GICv3. + *****************************************************************************/ +void plat_arm_gic_pcpu_init(void) +{ + arm_gic_pcpu_distif_setup(); +} diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index cae65970..bd5820b5 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -164,9 +164,13 @@ void arm_system_pwr_domain_resume(void) /* Assert system power domain is available on the platform */ assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); - arm_gic_setup(); + /* + * TODO: On GICv3 systems, figure out whether the core that wakes up + * first from system suspend need to initialize the re-distributor + * interface of all the other suspended cores. + */ + plat_arm_gic_init(); plat_arm_security_setup(); - arm_configure_sys_timer(); } diff --git a/plat/arm/common/tsp/arm_tsp.mk b/plat/arm/common/tsp/arm_tsp.mk index f285f585..691a2ab6 100644 --- a/plat/arm/common/tsp/arm_tsp.mk +++ b/plat/arm/common/tsp/arm_tsp.mk @@ -29,9 +29,6 @@ # # TSP source files common to ARM standard platforms -BL32_SOURCES += drivers/arm/gic/arm_gic.c \ - drivers/arm/gic/gic_v2.c \ - plat/arm/common/arm_topology.c \ +BL32_SOURCES += plat/arm/common/arm_topology.c \ plat/arm/common/tsp/arm_tsp_setup.c \ - plat/common/aarch64/platform_mp_stack.S \ - plat/common/plat_gic.c + plat/common/aarch64/platform_mp_stack.S diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c index 78db1605..3631c033 100644 --- a/plat/arm/common/tsp/arm_tsp_setup.c +++ b/plat/arm/common/tsp/arm_tsp_setup.c @@ -89,7 +89,7 @@ void tsp_early_platform_setup(void) ******************************************************************************/ void tsp_platform_setup(void) { - plat_arm_gic_init(); + plat_arm_gic_driver_init(); } /******************************************************************************* diff --git a/plat/arm/css/common/css_common.c b/plat/arm/css/common/css_common.c deleted file mode 100644 index 91813f2c..00000000 --- a/plat/arm/css/common/css_common.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arm_gic.h> -#include <bl_common.h> -#include <platform_def.h> - - -#if IMAGE_BL31 || IMAGE_BL32 - -const unsigned int irq_sec_array[] = { - PLAT_CSS_IRQ_SEC_LIST, - ARM_IRQ_SEC_PHY_TIMER, - ARM_IRQ_SEC_SGI_0, - ARM_IRQ_SEC_SGI_1, - ARM_IRQ_SEC_SGI_2, - ARM_IRQ_SEC_SGI_3, - ARM_IRQ_SEC_SGI_4, - ARM_IRQ_SEC_SGI_5, - ARM_IRQ_SEC_SGI_6, - ARM_IRQ_SEC_SGI_7 -}; - - -/* Weak definitions may be overridden in specific CSS based platform */ -#pragma weak plat_arm_gic_init - -void plat_arm_gic_init(void) -{ - arm_gic_init(PLAT_CSS_GICC_BASE, - PLAT_CSS_GICD_BASE, - PLAT_CSS_GICR_BASE, - irq_sec_array, - ARRAY_SIZE(irq_sec_array)); -} - -#endif /* IMAGE_BL31 || IMAGE_BL32 */ diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk index 6b05869e..63941979 100644 --- a/plat/arm/css/common/css_common.mk +++ b/plat/arm/css/common/css_common.mk @@ -32,8 +32,7 @@ PLAT_INCLUDES += -Iinclude/plat/arm/css/common \ -Iinclude/plat/arm/css/common/aarch64 -PLAT_BL_COMMON_SOURCES += plat/arm/css/common/aarch64/css_helpers.S \ - plat/arm/css/common/css_common.c +PLAT_BL_COMMON_SOURCES += plat/arm/css/common/aarch64/css_helpers.S #BL1_SOURCES += diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index 1d9bd594..6d6646e0 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c @@ -30,7 +30,6 @@ #include <arch_helpers.h> #include <assert.h> -#include <arm_gic.h> #include <cassert.h> #include <cci.h> #include <css_pm.h> @@ -127,10 +126,11 @@ void css_pwr_domain_on_finish(const psci_power_state_t *target_state) css_pwr_domain_on_finisher_common(target_state); + /* Program the gic per-cpu distributor or re-distributor interface */ + plat_arm_gic_pcpu_init(); + /* Enable the gic cpu interface */ - arm_gic_cpuif_setup(); - /* Program the gic per-cpu distributor interface */ - arm_gic_pcpu_distif_setup(); + plat_arm_gic_cpuif_enable(); } /******************************************************************************* @@ -145,7 +145,7 @@ static void css_power_down_common(const psci_power_state_t *target_state) uint32_t system_state = scpi_power_on; /* Prevent interrupts from spuriously waking up this cpu */ - arm_gic_cpuif_deactivate(); + plat_arm_gic_cpuif_disable(); /* Check if power down at system power domain level is requested */ if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) @@ -213,7 +213,7 @@ void css_pwr_domain_suspend_finish( arm_system_pwr_domain_resume(); else /* Enable the gic cpu interface */ - arm_gic_cpuif_setup(); + plat_arm_gic_cpuif_enable(); css_pwr_domain_on_finisher_common(target_state); } |