diff options
34 files changed, 272 insertions, 340 deletions
@@ -275,13 +275,6 @@ endif endif ################################################################################ -# Include libraries' Makefile that are used in all BL -################################################################################ - -include lib/stack_protector/stack_protector.mk - - -################################################################################ # Include the platform specific Makefile after the SPD Makefile (the platform # makefile may use all previous definitions in this file) ################################################################################ @@ -441,6 +434,12 @@ FIP_ARGS += --align ${FIP_ALIGN} endif ################################################################################ +# Include libraries' Makefile that are used in all BL +################################################################################ + +include lib/stack_protector/stack_protector.mk + +################################################################################ # Auxiliary tools (fiptool, cert_create, etc) ################################################################################ diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h index 6ac3b8c6..42a74d22 100644 --- a/bl1/bl1_private.h +++ b/bl1/bl1_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,18 +8,16 @@ #define __BL1_PRIVATE_H__ #include <types.h> +#include <utils_def.h> /******************************************************************************* * Declarations of linker defined symbols which will tell us where BL1 lives * in Trusted ROM and RAM ******************************************************************************/ -extern uintptr_t __BL1_ROM_END__; -#define BL1_ROM_END (uintptr_t)(&__BL1_ROM_END__) +IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END); -extern uintptr_t __BL1_RAM_START__; -extern uintptr_t __BL1_RAM_END__; -#define BL1_RAM_BASE (uintptr_t)(&__BL1_RAM_START__) -#define BL1_RAM_LIMIT (uintptr_t)(&__BL1_RAM_END__) +IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE); +IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT); /****************************************** * Function prototypes diff --git a/common/runtime_svc.c b/common/runtime_svc.c index 0ea4cd09..de80f30c 100644 --- a/common/runtime_svc.c +++ b/common/runtime_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,8 +19,6 @@ * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the * 'rt_svc_descs' array which contains the SMC handler. ******************************************************************************/ -#define RT_SVC_DESCS_START ((uintptr_t) (&__RT_SVC_DESCS_START__)) -#define RT_SVC_DESCS_END ((uintptr_t) (&__RT_SVC_DESCS_END__)) uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; static rt_svc_desc_t *rt_svc_descs; diff --git a/drivers/auth/img_parser_mod.c b/drivers/auth/img_parser_mod.c index 6a010711..63160141 100644 --- a/drivers/auth/img_parser_mod.c +++ b/drivers/auth/img_parser_mod.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,11 +12,10 @@ #include <limits.h> #include <stdint.h> #include <string.h> +#include <utils_def.h> -extern uintptr_t __PARSER_LIB_DESCS_START__; -extern uintptr_t __PARSER_LIB_DESCS_END__; -#define PARSER_LIB_DESCS_START ((uintptr_t) (&__PARSER_LIB_DESCS_START__)) -#define PARSER_LIB_DESCS_END ((uintptr_t) (&__PARSER_LIB_DESCS_END__)) +IMPORT_SYM(uintptr_t, __PARSER_LIB_DESCS_START__, PARSER_LIB_DESCS_START); +IMPORT_SYM(uintptr_t, __PARSER_LIB_DESCS_END__, PARSER_LIB_DESCS_END); static unsigned int parser_lib_indices[IMG_MAX_TYPES]; static img_parser_lib_desc_t *parser_lib_descs; diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 4ef916f5..09a394dd 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -64,33 +64,41 @@ #include <types.h> #include <utils_def.h> /* To retain compatibility */ + /* * Declarations of linker defined symbols to help determine memory layout of * BL images */ #if SEPARATE_CODE_AND_RODATA -extern uintptr_t __TEXT_START__; -extern uintptr_t __TEXT_END__; -extern uintptr_t __RODATA_START__; -extern uintptr_t __RODATA_END__; +IMPORT_SYM(unsigned long, __TEXT_START__, BL_CODE_BASE); +IMPORT_SYM(unsigned long, __TEXT_END__, BL_CODE_END); +IMPORT_SYM(unsigned long, __RODATA_START__, BL_RO_DATA_BASE); +IMPORT_SYM(unsigned long, __RODATA_END__, BL_RO_DATA_END); #else -extern uintptr_t __RO_START__; -extern uintptr_t __RO_END__; +IMPORT_SYM(unsigned long, __RO_START__, BL_CODE_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL_CODE_END); #endif #if defined(IMAGE_BL2) -extern uintptr_t __BL2_END__; +IMPORT_SYM(unsigned long, __BL2_END__, BL2_END); #elif defined(IMAGE_BL2U) -extern uintptr_t __BL2U_END__; +IMPORT_SYM(unsigned long, __BL2U_END__, BL2U_END); #elif defined(IMAGE_BL31) -extern uintptr_t __BL31_END__; +IMPORT_SYM(unsigned long, __BL31_END__, BL31_END); #elif defined(IMAGE_BL32) -extern uintptr_t __BL32_END__; +IMPORT_SYM(unsigned long, __BL32_END__, BL32_END); #endif /* IMAGE_BLX */ +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ #if USE_COHERENT_MEM -extern uintptr_t __COHERENT_RAM_START__; -extern uintptr_t __COHERENT_RAM_END__; +IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE); +IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL_COHERENT_RAM_END); #endif /******************************************************************************* diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h index d12af227..5d9fa390 100644 --- a/include/common/runtime_svc.h +++ b/include/common/runtime_svc.h @@ -122,8 +122,8 @@ CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \ void runtime_svc_init(void); uintptr_t handle_runtime_svc(uint32_t smc_fid, void *cookie, void *handle, unsigned int flags); -extern uintptr_t __RT_SVC_DESCS_START__; -extern uintptr_t __RT_SVC_DESCS_END__; +IMPORT_SYM(uintptr_t, __RT_SVC_DESCS_START__, RT_SVC_DESCS_START); +IMPORT_SYM(uintptr_t, __RT_SVC_DESCS_END__, RT_SVC_DESCS_END); void init_crash_reporting(void); extern uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; diff --git a/include/drivers/console.h b/include/drivers/console.h index f8ec83d2..c8a43a28 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h @@ -66,6 +66,8 @@ int console_flush(void); /* REMOVED on AArch64 -- use console_<driver>_register() instead! */ int console_init(uintptr_t base_addr, unsigned int uart_clk, unsigned int baud_rate); +int console_core_init(uintptr_t base_addr, + unsigned int uart_clk, unsigned int baud_rate); void console_uninit(void); #endif diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 4a5c3e0b..8abc73c0 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -99,4 +99,21 @@ ((ARM_ARCH_MAJOR > _maj) || \ ((ARM_ARCH_MAJOR == _maj) && (ARM_ARCH_MINOR >= _min))) +/* + * Import an assembly or linker symbol as a C expression with the specified + * type + */ +#define IMPORT_SYM(type, sym, name) \ + extern char sym[];\ + static const __attribute__((unused)) type name = (type) sym; + +/* + * When the symbol is used to hold a pointer, its alignment can be asserted + * with this macro. For example, if there is a linker symbol that is going to + * be used as a 64-bit pointer, the value of the linker symbol must also be + * aligned to 64 bit. This macro makes sure this is the case. + */ +#define ASSERT_SYM_PTR_ALIGN(sym) assert(((size_t)(sym) % __alignof__(*(sym))) == 0) + + #endif /* __UTILS_DEF_H__ */ diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h index a841c3db..84923b9a 100644 --- a/include/plat/common/common_def.h +++ b/include/plat/common/common_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,33 +74,13 @@ * page of it with the right memory attributes. */ #if SEPARATE_CODE_AND_RODATA -#define BL_CODE_BASE (unsigned long)(&__TEXT_START__) -#define BL_CODE_END (unsigned long)(&__TEXT_END__) -#define BL_RO_DATA_BASE (unsigned long)(&__RODATA_START__) -#define BL_RO_DATA_END (unsigned long)(&__RODATA_END__) #define BL1_CODE_END BL_CODE_END -#define BL1_RO_DATA_BASE (unsigned long)(&__RODATA_START__) +#define BL1_RO_DATA_BASE BL_RO_DATA_BASE #define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE) #else -#define BL_CODE_BASE (unsigned long)(&__RO_START__) -#define BL_CODE_END (unsigned long)(&__RO_END__) #define BL_RO_DATA_BASE 0 #define BL_RO_DATA_END 0 - #define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE) -#define BL1_RO_DATA_BASE 0 -#define BL1_RO_DATA_END 0 #endif /* SEPARATE_CODE_AND_RODATA */ - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL_COHERENT_RAM_END (unsigned long)(&__COHERENT_RAM_END__) - #endif /* __COMMON_DEF_H__ */ diff --git a/include/services/secure_partition.h b/include/services/secure_partition.h index 93df2a13..f68f711b 100644 --- a/include/services/secure_partition.h +++ b/include/services/secure_partition.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,15 +11,11 @@ #include <types.h> #include <utils_def.h> -/* Linker symbols */ -extern uintptr_t __SP_IMAGE_XLAT_TABLES_START__; -extern uintptr_t __SP_IMAGE_XLAT_TABLES_END__; +/* Import linker symbols */ +IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_START__, SP_IMAGE_XLAT_TABLES_START); +IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_END__, SP_IMAGE_XLAT_TABLES_END); /* Definitions */ -#define SP_IMAGE_XLAT_TABLES_START \ - (uintptr_t)(&__SP_IMAGE_XLAT_TABLES_START__) -#define SP_IMAGE_XLAT_TABLES_END \ - (uintptr_t)(&__SP_IMAGE_XLAT_TABLES_END__) #define SP_IMAGE_XLAT_TABLES_SIZE \ (SP_IMAGE_XLAT_TABLES_END - SP_IMAGE_XLAT_TABLES_START) diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c index 8f59215e..37697f52 100644 --- a/lib/locks/bakery/bakery_lock_normal.c +++ b/lib/locks/bakery/bakery_lock_normal.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <cpu_data.h> #include <platform.h> #include <string.h> +#include <utils_def.h> /* * Functions in this file implement Bakery Algorithm for mutual exclusion with the @@ -49,8 +50,7 @@ CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \ * Use the linker defined symbol which has evaluated the size reqiurement. * This is not as efficient as using a platform defined constant */ -extern void *__PERCPU_BAKERY_LOCK_SIZE__; -#define PERCPU_BAKERY_LOCK_SIZE ((uintptr_t)&__PERCPU_BAKERY_LOCK_SIZE__) +IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE); #endif #define get_bakery_info(cpu_ix, lock) \ diff --git a/lib/pmf/pmf_main.c b/lib/pmf/pmf_main.c index 2cf260ec..0208948f 100644 --- a/lib/pmf/pmf_main.c +++ b/lib/pmf/pmf_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #include <platform.h> #include <pmf.h> #include <string.h> +#include <utils_def.h> /******************************************************************************* * The 'pmf_svc_descs' array holds the PMF service descriptors exported by @@ -21,16 +22,12 @@ * index of the descriptor in the 'pmf_svc_descs' array which contains the * service function pointers. ******************************************************************************/ -extern uintptr_t __PMF_SVC_DESCS_START__; -extern uintptr_t __PMF_SVC_DESCS_END__; -#define PMF_SVC_DESCS_START ((uintptr_t)(&__PMF_SVC_DESCS_START__)) -#define PMF_SVC_DESCS_END ((uintptr_t)(&__PMF_SVC_DESCS_END__)) -extern void *__PERCPU_TIMESTAMP_SIZE__; -#define PMF_PERCPU_TIMESTAMP_SIZE ((uintptr_t)&__PERCPU_TIMESTAMP_SIZE__) -extern uintptr_t __PMF_TIMESTAMP_START__; -#define PMF_TIMESTAMP_ARRAY_START ((uintptr_t)&__PMF_TIMESTAMP_START__) -extern uintptr_t __PMF_TIMESTAMP_END__; -#define PMF_TIMESTAMP_ARRAY_END ((uintptr_t)&__PMF_TIMESTAMP_END__) + +IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_START__, PMF_SVC_DESCS_START); +IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_END__, PMF_SVC_DESCS_END); +IMPORT_SYM(uintptr_t, __PERCPU_TIMESTAMP_SIZE__, PMF_PERCPU_TIMESTAMP_SIZE); +IMPORT_SYM(intptr_t, __PMF_TIMESTAMP_START__, PMF_TIMESTAMP_ARRAY_START); +IMPORT_SYM(uintptr_t, __PMF_TIMESTAMP_END__, PMF_TIMESTAMP_ARRAY_END); #define PMF_SVC_DESCS_MAX 10 diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c index 3e79c5d7..e925d34e 100644 --- a/lib/psci/psci_stat.c +++ b/lib/psci/psci_stat.c @@ -24,7 +24,8 @@ typedef struct psci_stat { * Following is used to keep track of the last cpu * that goes to power down in non cpu power domains. */ -static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {-1}; +static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = { + [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS-1] = -1}; /* * Following are used to store PSCI STAT values for @@ -129,6 +130,10 @@ void psci_stats_update_pwr_up(unsigned int end_pwrlvl, * prior to this CPU powering on. */ parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + /* Return early if this is the first power up. */ + if (last_cpu_in_non_cpu_pd[parent_idx] == -1) + return; + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { local_state = state_info->pwr_domain_state[lvl]; if (is_local_state_run(local_state)) { diff --git a/plat/hisilicon/hikey/aarch64/hikey_common.c b/plat/hisilicon/hikey/aarch64/hikey_common.c index f95af587..658760b5 100644 --- a/plat/hisilicon/hikey/aarch64/hikey_common.c +++ b/plat/hisilicon/hikey/aarch64/hikey_common.c @@ -9,13 +9,12 @@ #include <assert.h> #include <bl_common.h> #include <debug.h> +#include <hikey_def.h> +#include <hikey_layout.h> #include <mmio.h> #include <platform.h> -#include <platform_def.h> #include <xlat_tables.h> -#include "../hikey_def.h" - #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \ DDR_SIZE - DDR_SEC_SIZE, \ MT_DEVICE | MT_RW | MT_NS) diff --git a/plat/hisilicon/hikey/aarch64/hikey_helpers.S b/plat/hisilicon/hikey/aarch64/hikey_helpers.S index 680c0a1d..32ff8b40 100644 --- a/plat/hisilicon/hikey/aarch64/hikey_helpers.S +++ b/plat/hisilicon/hikey/aarch64/hikey_helpers.S @@ -1,12 +1,12 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch.h> #include <asm_macros.S> -#include "../hikey_def.h" +#include <hikey_def.h> .globl plat_my_core_pos .globl platform_mem_init diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c index 69b194a5..28ad9df2 100644 --- a/plat/hisilicon/hikey/hikey_bl1_setup.c +++ b/plat/hisilicon/hikey/hikey_bl1_setup.c @@ -13,33 +13,16 @@ #include <emmc.h> #include <errno.h> #include <hi6220.h> +#include <hikey_def.h> +#include <hikey_layout.h> #include <mmio.h> #include <platform.h> -#include <platform_def.h> #include <string.h> #include <tbbr/tbbr_img_desc.h> #include "../../bl1/bl1_private.h" -#include "hikey_def.h" #include "hikey_private.h" -/* - * Declarations of linker defined symbols which will help us find the layout - * of trusted RAM - */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) - /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -103,8 +86,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } /* diff --git a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c index 7c025c34..23c16ed9 100644 --- a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c +++ b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c @@ -7,7 +7,7 @@ #include <bl_common.h> #include <desc_image_load.h> #include <platform.h> -#include <platform_def.h> +#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ /******************************************************************************* diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index 20bb7527..8bb28248 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -21,10 +21,9 @@ #include <optee_utils.h> #endif #include <platform.h> -#include <platform_def.h> +#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ #include <string.h> -#include "hikey_def.h" #include "hikey_private.h" /* diff --git a/plat/hisilicon/hikey/hikey_bl31_setup.c b/plat/hisilicon/hikey/hikey_bl31_setup.c index e13ecf67..a193b5a7 100644 --- a/plat/hisilicon/hikey/hikey_bl31_setup.c +++ b/plat/hisilicon/hikey/hikey_bl31_setup.c @@ -14,12 +14,12 @@ #include <errno.h> #include <gicv2.h> #include <hi6220.h> +#include <hikey_def.h> #include <hisi_ipc.h> #include <hisi_pwrc.h> #include <mmio.h> #include <platform_def.h> -#include "hikey_def.h" #include "hikey_private.h" /* diff --git a/plat/hisilicon/hikey/hikey_pm.c b/plat/hisilicon/hikey/hikey_pm.c index d4dd683e..3128a3d1 100644 --- a/plat/hisilicon/hikey/hikey_pm.c +++ b/plat/hisilicon/hikey/hikey_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <debug.h> #include <gicv2.h> #include <hi6220.h> +#include <hikey_def.h> #include <hisi_ipc.h> #include <hisi_pwrc.h> #include <hisi_sram_map.h> @@ -17,8 +18,6 @@ #include <psci.h> #include <sp804_delay_timer.h> -#include "hikey_def.h" - #define CORE_PWR_STATE(state) \ ((state)->pwr_domain_state[MPIDR_AFFLVL0]) #define CLUSTER_PWR_STATE(state) \ diff --git a/plat/hisilicon/hikey/hikey_def.h b/plat/hisilicon/hikey/include/hikey_def.h index 668b4592..deb375da 100644 --- a/plat/hisilicon/hikey/hikey_def.h +++ b/plat/hisilicon/hikey/include/hikey_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,9 +7,6 @@ #ifndef __HIKEY_DEF_H__ #define __HIKEY_DEF_H__ -#include <common_def.h> -#include <tbbr_img_def.h> - /* Always assume DDR is 1GB size. */ #define DDR_BASE 0x0 #define DDR_SIZE 0x40000000 @@ -17,9 +14,6 @@ #define DEVICE_BASE 0xF4000000 #define DEVICE_SIZE 0x05800000 -#define XG2RAM0_BASE 0xF9800000 -#define XG2RAM0_SIZE 0x00400000 - /* Memory location options for TSP */ #define HIKEY_SRAM_ID 0 #define HIKEY_DRAM_ID 1 @@ -43,13 +37,6 @@ #define SRAM_SIZE 0x00012000 /* - * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). - */ -#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) -#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) -#define BL1_XG2RAM0_OFFSET 0x1000 - -/* * PL011 related constants */ #define PL011_UART0_BASE 0xF8015000 diff --git a/plat/hisilicon/hikey/include/hikey_layout.h b/plat/hisilicon/hikey/include/hikey_layout.h new file mode 100644 index 00000000..637a1c9b --- /dev/null +++ b/plat/hisilicon/hikey/include/hikey_layout.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HIKEY_LAYOUT_H +#define __HIKEY_LAYOUT_H + +/* + * Platform memory map related constants + */ +#define XG2RAM0_BASE 0xF9800000 +#define XG2RAM0_SIZE 0x00400000 + +/* + * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). + */ +#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) +#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) +#define BL1_XG2RAM0_OFFSET 0x1000 + +/* + * BL1 specific defines. + * + * Both loader and BL1_RO region stay in SRAM since they are used to simulate + * ROM. + * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. + * + * ++++++++++ 0xF980_0000 + * + loader + + * ++++++++++ 0xF980_1000 + * + BL1_RO + + * ++++++++++ 0xF981_0000 + * + BL1_RW + + * ++++++++++ 0xF989_8000 + */ +#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) +#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) +#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ +#define BL1_RW_SIZE (0x00088000) +#define BL1_RW_LIMIT (0xF9898000) + +/* + * Non-Secure BL1U specific defines. + */ +#define NS_BL1U_BASE (0xf9818000) +#define NS_BL1U_SIZE (0x00010000) +#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) + +/* + * BL2 specific defines. + * + * Both loader and BL2 region stay in SRAM. + * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. + * + * ++++++++++ 0xF980_0000 + * + loader + + * ++++++++++ 0xF980_1000 + * + BL2 + + * ++++++++++ 0xF981_8000 + */ +#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ +#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */ + +/* + * SCP_BL2 specific defines. + * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer + * at 0x0100_0000. Then BL2 will parse the sections and loaded them into + * predefined separated buffers. + */ +#define SCP_BL2_BASE (DDR_BASE + 0x01000000) +#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) +#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) + +/* + * BL31 specific defines. + */ +#define BL31_BASE (0xF9858000) /* 0xf985_8000 */ +#define BL31_LIMIT (0xF9898000) + +/* + * BL3-2 specific defines. + */ + +/* + * The TSP currently executes from TZC secured area of DRAM or SRAM. + */ +#define BL32_SRAM_BASE BL31_LIMIT +#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ + +#define BL32_DRAM_BASE DDR_SEC_BASE +#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) + +#ifdef SPD_opteed +/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ +#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ +#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ +#endif + +#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) +#define TSP_SEC_MEM_BASE BL32_DRAM_BASE +#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) +#define BL32_BASE BL32_DRAM_BASE +#define BL32_LIMIT BL32_DRAM_LIMIT +#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) +#define TSP_SEC_MEM_BASE BL32_SRAM_BASE +#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) +#define BL32_BASE BL32_SRAM_BASE +#define BL32_LIMIT BL32_SRAM_LIMIT +#else +#error "Currently unsupported HIKEY_TSP_LOCATION_ID value" +#endif + +/* BL32 is mandatory in AArch32 */ +#ifndef AARCH32 +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ +#endif + +#endif /* !__HIKEY_LAYOUT_H */ diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h index 9b4f4631..8c560047 100644 --- a/plat/hisilicon/hikey/include/platform_def.h +++ b/plat/hisilicon/hikey/include/platform_def.h @@ -8,7 +8,10 @@ #define __PLATFORM_DEF_H__ #include <arch.h> -#include "../hikey_def.h" +#include <common_def.h> +#include <hikey_def.h> +#include <hikey_layout.h> /* BL memory region sizes, etc */ +#include <tbbr_img_def.h> /* Special value used to verify platform parameters from BL2 to BL3-1 */ #define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL @@ -27,7 +30,7 @@ #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_CORE_COUNT_PER_CLUSTER) -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 +#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ PLATFORM_CLUSTER_COUNT + 1) @@ -45,114 +48,6 @@ #define PLAT_ARM_GICH_BASE 0xF6804000 #define PLAT_ARM_GICV_BASE 0xF6806000 - -/* - * Platform memory map related constants - */ - -/* - * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). - */ -#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) -#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) -#define BL1_XG2RAM0_OFFSET 0x1000 - -/* - * BL1 specific defines. - * - * Both loader and BL1_RO region stay in SRAM since they are used to simulate - * ROM. - * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. - * - * ++++++++++ 0xF980_0000 - * + loader + - * ++++++++++ 0xF980_1000 - * + BL1_RO + - * ++++++++++ 0xF981_0000 - * + BL1_RW + - * ++++++++++ 0xF989_8000 - */ -#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) -#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) -#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ -#define BL1_RW_SIZE (0x00088000) -#define BL1_RW_LIMIT (0xF9898000) - -/* - * BL2 specific defines. - * - * Both loader and BL2 region stay in SRAM. - * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. - * - * ++++++++++ 0xF980_0000 - * + loader + - * ++++++++++ 0xF980_1000 - * + BL2 + - * ++++++++++ 0xF981_8000 - */ -#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ -#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */ - -/* - * SCP_BL2 specific defines. - * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer - * at 0x0100_0000. Then BL2 will parse the sections and loaded them into - * predefined separated buffers. - */ -#define SCP_BL2_BASE (DDR_BASE + 0x01000000) -#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) -#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) - -/* - * BL31 specific defines. - */ -#define BL31_BASE (0xF9858000) /* 0xf985_8000 */ -#define BL31_LIMIT (0xF9898000) - -/* - * BL3-2 specific defines. - */ - -/* - * The TSP currently executes from TZC secured area of DRAM or SRAM. - */ -#define BL32_SRAM_BASE BL31_LIMIT -#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ - -#define BL32_DRAM_BASE DDR_SEC_BASE -#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) - -#ifdef SPD_opteed -/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ -#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ -#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ -#endif - -#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) -#define TSP_SEC_MEM_BASE BL32_DRAM_BASE -#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) -#define BL32_BASE BL32_DRAM_BASE -#define BL32_LIMIT BL32_DRAM_LIMIT -#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) -#define TSP_SEC_MEM_BASE BL32_SRAM_BASE -#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) -#define BL32_BASE BL32_SRAM_BASE -#define BL32_LIMIT BL32_SRAM_LIMIT -#else -#error "Currently unsupported HIKEY_TSP_LOCATION_ID value" -#endif - -/* BL32 is mandatory in AArch32 */ -#ifndef AARCH32 -#ifdef SPD_none -#undef BL32_BASE -#endif /* SPD_none */ -#endif - -#define NS_BL1U_BASE (0xf9818000) -#define NS_BL1U_SIZE (0x00010000) -#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) - /* * Platform specific page table and MMU setup constants */ @@ -172,8 +67,6 @@ #define MAX_MMAP_REGIONS 16 -#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000) - /* * Declarations and constants to access the mailboxes safely. Each mailbox is * aligned on the biggest cache line size in the platform. This is known only diff --git a/plat/hisilicon/hikey960/hikey960_bl1_setup.c b/plat/hisilicon/hikey960/hikey960_bl1_setup.c index 9cadba0b..6a07f092 100644 --- a/plat/hisilicon/hikey960/hikey960_bl1_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl1_setup.c @@ -37,18 +37,6 @@ enum { * Declarations of linker defined symbols which will help us find the layout * of trusted RAM */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -131,8 +119,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } static void hikey960_ufs_reset(void) diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c index 39551135..25eed593 100644 --- a/plat/hisilicon/poplar/bl1_plat_setup.c +++ b/plat/hisilicon/poplar/bl1_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,13 +23,6 @@ #include "hi3798cv200.h" #include "plat_private.h" -/* Symbols from link script for conherent section */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) - /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -92,8 +85,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, /* l-loader and BL1 ROM */ BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } void bl1_platform_setup(void) diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c index 803f1ed8..32f01572 100644 --- a/plat/mediatek/mt6795/bl31_plat_setup.c +++ b/plat/mediatek/mt6795/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,22 +21,21 @@ #include <plat_private.h> #include <platform.h> #include <string.h> +#include <utils_def.h> #include <xlat_tables.h> + /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); /* * Placeholder variables for copying the arguments that have been passed to diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index 7b293077..e51bdbb9 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,24 +17,6 @@ #include <platform.h> #include <spm.h> -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted SRAM - ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL31 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) -#define BL31_END (unsigned long)(&__BL31_END__) - static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; @@ -156,10 +138,10 @@ void bl31_plat_arch_setup(void) plat_cci_init(); plat_cci_enable(); - plat_configure_mmu_el3(BL31_RO_BASE, - BL_COHERENT_RAM_END - BL31_RO_BASE, - BL31_RO_BASE, - BL31_RO_LIMIT, + plat_configure_mmu_el3(BL_CODE_BASE, + BL_COHERENT_RAM_END - BL_CODE_BASE, + BL_CODE_BASE, + BL_CODE_END, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); } diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index d89ad7b9..2fe4e7db 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,6 +23,7 @@ #include <string.h> #include <tegra_def.h> #include <tegra_private.h> +#include <utils_def.h> /* length of Trusty's input parameters (in bytes) */ #define TRUSTY_PARAMS_LEN_BYTES (4096*2) @@ -33,29 +34,17 @@ extern void zeromem16(void *mem, unsigned int length); * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ -extern unsigned long __TEXT_START__; -extern unsigned long __TEXT_END__; -extern unsigned long __RW_START__; -extern unsigned long __RW_END__; -extern unsigned long __RODATA_START__; -extern unsigned long __RODATA_END__; -extern unsigned long __BL31_END__; + +IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); +IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); +IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE); +IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END); +IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START); +IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END); extern uint64_t tegra_bl31_phys_base; extern uint64_t tegra_console_base; -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL3-1 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RW_START (unsigned long)(&__RW_START__) -#define BL31_RW_END (unsigned long)(&__RW_END__) -#define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__) -#define BL31_RODATA_END (unsigned long)(&__RODATA_END__) -#define BL31_END (unsigned long)(&__BL31_END__) static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { @@ -311,8 +300,8 @@ void bl31_plat_arch_setup(void) unsigned long rw_size = BL31_RW_END - BL31_RW_START; unsigned long rodata_start = BL31_RODATA_BASE; unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; - unsigned long code_base = (unsigned long)(&__TEXT_START__); - unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base; + unsigned long code_base = TEXT_START; + unsigned long code_size = TEXT_END - TEXT_START; const mmap_region_t *plat_mmio_map = NULL; #if USE_COHERENT_MEM unsigned long coh_start, coh_size; diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk index a9fbcd73..017807b0 100644 --- a/plat/qemu/platform.mk +++ b/plat/qemu/platform.mk @@ -169,7 +169,12 @@ $(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2)) endif SEPARATE_CODE_AND_RODATA := 1 -MULTI_CONSOLE_API := 1 + +# Use MULTI_CONSOLE_API by default only on AArch64 +# as it is not yet supported on AArch32 +ifeq ($(ARCH),aarch64) +MULTI_CONSOLE_API := 1 +endif # Disable the PSCI platform compatibility layer ENABLE_PLAT_COMPAT := 0 diff --git a/plat/qemu/qemu_console.c b/plat/qemu/qemu_console.c index 9c02957e..1cf84aa7 100644 --- a/plat/qemu/qemu_console.c +++ b/plat/qemu/qemu_console.c @@ -7,8 +7,10 @@ #include <pl011.h> #include <platform_def.h> +#if MULTI_CONSOLE_API static console_pl011_t console; static console_pl011_t crash_console; +#endif /* MULTI_CONSOLE_API */ void qemu_console_init(void) { diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 6199edae..e5ee68f1 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,21 +17,14 @@ #include <platform_def.h> #include <uart_16550.h> -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted SRAM - ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index f4893efe..caea7a72 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -1319,10 +1319,14 @@ void wdt_register_restore(void) { int i; - for (i = 0; i < 2; i++) { + for (i = 1; i >= 0; i--) { mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]); mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]); } + + /* write 0x76 to cnt_restart to keep watchdog alive */ + mmio_write_32(WDT0_BASE + 0x0c, 0x76); + mmio_write_32(WDT1_BASE + 0x0c, 0x76); } int rockchip_soc_sys_pwr_dm_suspend(void) @@ -1383,6 +1387,7 @@ int rockchip_soc_sys_pwr_dm_suspend(void) } mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); + wdt_register_save(); secure_watchdog_disable(); /* @@ -1398,7 +1403,6 @@ int rockchip_soc_sys_pwr_dm_suspend(void) suspend_uart(); grf_register_save(); cru_register_save(); - wdt_register_save(); sram_save(); plat_rockchip_save_gpio(); @@ -1411,7 +1415,6 @@ int rockchip_soc_sys_pwr_dm_resume(void) uint32_t status = 0; plat_rockchip_restore_gpio(); - wdt_register_restore(); cru_register_restore(); grf_register_restore(); resume_uart(); @@ -1426,6 +1429,7 @@ int rockchip_soc_sys_pwr_dm_resume(void) secure_watchdog_enable(); secure_sgrf_init(); secure_sgrf_ddr_rgn_init(); + wdt_register_restore(); /* restore clk_ddrc_bpll_src_en gate */ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c index d6e57267..97f202cb 100644 --- a/services/spd/trusty/trusty.c +++ b/services/spd/trusty/trusty.c @@ -451,7 +451,7 @@ static int32_t trusty_setup(void) uint32_t spsr; ns_ep_info = bl31_plat_get_next_image_ep_info(NON_SECURE); - if (!ep_info) { + if (ns_ep_info == NULL) { NOTICE("Trusty: non-secure image missing.\n"); return -1; } diff --git a/services/std_svc/spm/spm_shim_private.h b/services/std_svc/spm/spm_shim_private.h index ad953cde..8408d1e0 100644 --- a/services/std_svc/spm/spm_shim_private.h +++ b/services/std_svc/spm/spm_shim_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,21 +8,17 @@ #define __SPM_SHIM_PRIVATE__ #include <types.h> +#include <utils_def.h> /* Assembly source */ -extern uintptr_t spm_shim_exceptions_ptr; +IMPORT_SYM(uintptr_t, spm_shim_exceptions_ptr, SPM_SHIM_EXCEPTIONS_PTR); /* Linker symbols */ -extern uintptr_t __SPM_SHIM_EXCEPTIONS_START__; -extern uintptr_t __SPM_SHIM_EXCEPTIONS_END__; +IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START); +IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); /* Definitions */ -#define SPM_SHIM_EXCEPTIONS_PTR (uintptr_t)(&spm_shim_exceptions_ptr) -#define SPM_SHIM_EXCEPTIONS_START \ - (uintptr_t)(&__SPM_SHIM_EXCEPTIONS_START__) -#define SPM_SHIM_EXCEPTIONS_END \ - (uintptr_t)(&__SPM_SHIM_EXCEPTIONS_END__) #define SPM_SHIM_EXCEPTIONS_SIZE \ (SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START) |