diff options
57 files changed, 717 insertions, 497 deletions
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index 9f7e2901..64b363c5 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -21,8 +21,8 @@ #include "bl1_private.h" /* BL1 Service UUID */ -DEFINE_SVC_UUID(bl1_svc_uid, - 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75, +DEFINE_SVC_UUID2(bl1_svc_uid, + 0xd46739fd, 0xcb72, 0x9a4d, 0xb5, 0x75, 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); static void bl1_load_bl2(void); diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 0d1077cb..58e8afbd 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -170,15 +170,12 @@ func bl31_warm_entrypoint * enter coherency (as CPUs already are); and there's no reason to have * caches disabled either. */ - mov x0, #DISABLE_DCACHE - bl bl31_plat_enable_mmu - #if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY - mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_C_BIT - msr sctlr_el3, x0 - isb + mov x0, xzr +#else + mov x0, #DISABLE_DCACHE #endif + bl bl31_plat_enable_mmu bl psci_warmboot_entrypoint diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 87ef3f36..d6853cc4 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -298,20 +298,17 @@ func sp_min_warm_entrypoint * enter coherency (as CPUs already are); and there's no reason to have * caches disabled either. */ +#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY + mov r0, #0 +#else mov r0, #DISABLE_DCACHE +#endif bl bl32_plat_enable_mmu #if SP_MIN_WITH_SECURE_FIQ route_fiq_to_sp_min r0 #endif -#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY - ldcopr r0, SCTLR - orr r0, r0, #SCTLR_C_BIT - stcopr r0, SCTLR - isb -#endif - bl sp_min_warm_boot bl smc_get_next_ctx /* r0 points to `smc_ctx_t` */ diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 489183c5..5d9da857 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -247,41 +247,13 @@ func tsp_cpu_on_entry bl plat_set_my_stack /* -------------------------------------------- - * Enable the MMU with the DCache disabled. It - * is safe to use stacks allocated in normal - * memory as a result. All memory accesses are - * marked nGnRnE when the MMU is disabled. So - * all the stack writes will make it to memory. - * All memory accesses are marked Non-cacheable - * when the MMU is enabled but D$ is disabled. - * So used stack memory is guaranteed to be - * visible immediately after the MMU is enabled - * Enabling the DCache at the same time as the - * MMU can lead to speculatively fetched and - * possibly stale stack memory being read from - * other caches. This can lead to coherency - * issues. + * Enable MMU and D-caches together. * -------------------------------------------- */ - mov x0, #DISABLE_DCACHE + mov x0, #0 bl bl32_plat_enable_mmu /* --------------------------------------------- - * Enable the Data cache now that the MMU has - * been enabled. The stack has been unwound. It - * will be written first before being read. This - * will invalidate any stale cache lines resi- - * -dent in other caches. We assume that - * interconnect coherency has been enabled for - * this cluster by EL3 firmware. - * --------------------------------------------- - */ - mrs x0, sctlr_el1 - orr x0, x0, #SCTLR_C_BIT - msr sctlr_el1, x0 - isb - - /* --------------------------------------------- * Enter C runtime to perform any remaining * book keeping * --------------------------------------------- diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst index e3500c27..8aa76227 100644 --- a/docs/firmware-design.rst +++ b/docs/firmware-design.rst @@ -306,6 +306,8 @@ On Arm platforms, BL1 performs the following platform initializations: - If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then load it to the platform defined address and make it available to BL2 via ``arg0``. +- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U + and NS-BL2U firmware update images. Firmware Update detection and execution ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index 03930cff..5462cc1e 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -1661,6 +1661,7 @@ Function : bl2\_plat\_preload\_setup [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: + Argument : void Return : void @@ -1674,6 +1675,7 @@ Function : plat\_try\_next\_boot\_source() [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: + Argument : void Return : int @@ -1704,6 +1706,7 @@ Function : bl2\_el3\_early\_platform\_setup() [mandatory] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: + Argument : u_register_t, u_register_t, u_register_t, u_register_t Return : void @@ -1726,6 +1729,7 @@ Function : bl2\_el3\_plat\_arch\_setup() [mandatory] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: + Argument : void Return : void @@ -1741,6 +1745,7 @@ Function : bl2\_el3\_plat\_prepare\_exit() [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: + Argument : void Return : void @@ -1992,6 +1997,25 @@ state. This function must return a pointer to the ``entry_point_info`` structure (that was copied during ``bl31_early_platform_setup()``) if the image exists. It should return NULL otherwise. +Function : bl31_plat_enable_mmu [optional] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : uint32_t + Return : void + +This function enables the MMU. The boot code calls this function with MMU and +caches disabled. This function should program necessary registers to enable +translation, and upon return, the MMU on the calling PE must be enabled. + +The function must honor flags passed in the first argument. These flags are +defined by the translation library, and can be found in the file +``include/lib/xlat_tables/xlat_mmu_helpers.h``. + +On DynamIQ systems, this function must not use stack while enabling MMU, which +is how the function in xlat table library version 2 is implementated. + Function : plat\_get\_syscnt\_freq2() [mandatory] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/user-guide.rst b/docs/user-guide.rst index c7f7ef86..68a74edd 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -243,10 +243,10 @@ Common build options - ``BL2U``: This is an optional build option which specifies the path to BL2U image. In this case, the BL2U in TF-A will not be built. -- ``BL2_AT_EL3``: This is an optional build option that enables the use of +- ``BL2_AT_EL3``: This is an optional build option that enables the use of BL2 at EL3 execution level. -- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place +- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place (XIP) memory, like BL1. In these use-cases, it is necessary to initialize the RW sections in RAM, while leaving the RO sections in place. This option enable this use-case. For now, this option is only supported when BL2_AT_EL3 @@ -264,10 +264,10 @@ Common build options BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not be built. -- ``BL32_EXTRA1``: This is an optional build option which specifies the path to +- ``BL32_EXTRA1``: This is an optional build option which specifies the path to Trusted OS Extra1 image for the ``fip`` target. -- ``BL32_EXTRA2``: This is an optional build option which specifies the path to +- ``BL32_EXTRA2``: This is an optional build option which specifies the path to Trusted OS Extra2 image for the ``fip`` target. - ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the @@ -323,10 +323,10 @@ Common build options - ``DEBUG``: Chooses between a debug and release build. It can take either 0 (release) or 1 (debug) as values. 0 is the default. -- ``DYN_DISABLE_AUTH``: Enables the capability to disable Trusted Board Boot - authentication. This option is only meant to be enabled for development - platforms. Both TRUSTED_BOARD_BOOT and the LOAD_IMAGE_V2 flags need to be - set if this flag has to be enabled. 0 is the default. +- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted + Board Boot authentication at runtime. This option is meant to be enabled only + for development platforms. Both TRUSTED_BOARD_BOOT and LOAD_IMAGE_V2 flags + must be set if this flag has to be enabled. 0 is the default. - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of the normal boot flow. It must specify the entry point address of the EL3 @@ -454,6 +454,10 @@ Common build options management operations. This option defaults to 0 and if it is enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. + Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of + translation library (xlat tables v2) must be used; version 1 of translation + library is not supported. + - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 runtime software in AArch32 mode, which is required to run AArch32 on Juno. By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in @@ -743,8 +747,8 @@ Arm development platform specific build options - ``tsram`` : Trusted SRAM (default option when TBB is not enabled) - ``tdram`` : Trusted DRAM (if available) - - ``dram`` : Secure region in DRAM (default option when TBB is enabled, - configured by the TrustZone controller) + - ``dram`` : Secure region in DRAM (default option when TBB is enabled, + configured by the TrustZone controller) - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1 of the translation tables library instead of version 2. It is set to 0 by @@ -919,8 +923,7 @@ To check the entire source tree, you must first download copies of ``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available in the `Linux master tree`_ scripts directory, then set the ``CHECKPATCH`` environment variable to point to ``checkpatch.pl`` (with the other 2 files in -the same directory) and build the target -checkcodebase: +the same directory) and build the target checkcodebase: :: diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c index 487f5861..17543390 100644 --- a/drivers/io/io_fip.c +++ b/drivers/io/io_fip.c @@ -32,7 +32,7 @@ typedef struct { fip_toc_entry_t entry; } file_state_t; -static const uuid_t uuid_null = {0}; +static const uuid_t uuid_null = { {0} }; static file_state_t current_file = {0}; static uintptr_t backend_dev_handle; static uintptr_t backend_image_spec; diff --git a/include/common/aarch32/asm_macros.S b/include/common/aarch32/asm_macros.S index 74322228..f7d0595e 100644 --- a/include/common/aarch32/asm_macros.S +++ b/include/common/aarch32/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,20 @@ #include <asm_macros_common.S> #include <spinlock.h> +/* + * TLBI instruction with type specifier that implements the workaround for + * errata 813419 of Cortex-A57. + */ +#if ERRATA_A57_813419 +#define TLB_INVALIDATE(_reg, _coproc) \ + stcopr _reg, _coproc; \ + dsb ish; \ + stcopr _reg, _coproc +#else +#define TLB_INVALIDATE(_reg, _coproc) \ + stcopr _reg, _coproc +#endif + #define WORD_SIZE 4 /* diff --git a/include/common/aarch64/asm_macros.S b/include/common/aarch64/asm_macros.S index 7c8e643d..5b050455 100644 --- a/include/common/aarch64/asm_macros.S +++ b/include/common/aarch64/asm_macros.S @@ -10,6 +10,20 @@ #include <asm_macros_common.S> #include <spinlock.h> +/* + * TLBI instruction with type specifier that implements the workaround for + * errata 813419 of Cortex-A57. + */ +#if ERRATA_A57_813419 +#define TLB_INVALIDATE(_type) \ + tlbi _type; \ + dsb ish; \ + tlbi _type +#else +#define TLB_INVALIDATE(_type) \ + tlbi _type +#endif + .macro func_prologue stp x29, x30, [sp, #-0x10]! diff --git a/include/common/ep_info.h b/include/common/ep_info.h index 3c2fe444..99a03906 100644 --- a/include/common/ep_info.h +++ b/include/common/ep_info.h @@ -29,33 +29,38 @@ /* The following are used to set/get image attributes. */ #define PARAM_EP_SECURITY_MASK U(0x1) +/* Secure or Non-secure image */ #define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) #define SET_SECURITY_STATE(x, security) \ ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) -#define EP_EE_MASK U(0x2) -#define EP_EE_SHIFT 1 -#define EP_EE_LITTLE U(0x0) -#define EP_EE_BIG U(0x2) -#define EP_GET_EE(x) (x & EP_EE_MASK) -#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) - -#define EP_ST_MASK U(0x4) -#define EP_ST_DISABLE U(0x0) -#define EP_ST_ENABLE U(0x4) -#define EP_GET_ST(x) (x & EP_ST_MASK) -#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) - -#define EP_EXE_MASK U(0x8) -#define NON_EXECUTABLE U(0x0) -#define EXECUTABLE U(0x8) -#define EP_GET_EXE(x) (x & EP_EXE_MASK) -#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) - +/* Endianness of the image. */ +#define EP_EE_MASK U(0x2) +#define EP_EE_SHIFT U(1) +#define EP_EE_LITTLE U(0x0) +#define EP_EE_BIG U(0x2) +#define EP_GET_EE(x) ((x) & EP_EE_MASK) +#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) + +/* Enable or disable access to the secure timer from secure images. */ +#define EP_ST_MASK U(0x4) +#define EP_ST_DISABLE U(0x0) +#define EP_ST_ENABLE U(0x4) +#define EP_GET_ST(x) ((x) & EP_ST_MASK) +#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) + +/* Determine if an image is executable or not. */ +#define EP_EXE_MASK U(0x8) +#define NON_EXECUTABLE U(0x0) +#define EXECUTABLE U(0x8) +#define EP_GET_EXE(x) ((x) & EP_EXE_MASK) +#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) + +/* Flag to indicate the first image that is executed. */ #define EP_FIRST_EXE_MASK U(0x10) #define EP_FIRST_EXE U(0x10) -#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) -#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) +#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) +#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) #ifndef __ASSEMBLY__ diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 910341a7..a940b63b 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -340,7 +340,7 @@ /* * TTBR definitions */ -#define TTBR_CNP_BIT 0x1 +#define TTBR_CNP_BIT U(0x1) /* * CTR definitions diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 660c1dbd..cb722b0e 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -57,6 +57,7 @@ * does not equal SMC_UNK. This is to ensure that the caller won't mistake the * returned UUID in x0 for an invalid SMC error return */ +#if !ERROR_DEPRECATED #define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \ _n0, _n1, _n2, _n3, _n4, _n5) \ CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\ @@ -64,6 +65,24 @@ _tl, _tm, _th, _cl, _ch, \ { _n0, _n1, _n2, _n3, _n4, _n5 } \ } +#endif + + +#define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch, \ + _n0, _n1, _n2, _n3, _n4, _n5) \ + CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\ + static const uuid_t _name = { \ + {(_tl >> 24) & 0xFF, \ + (_tl >> 16) & 0xFF, \ + (_tl >> 8) & 0xFF, \ + (_tl & 0xFF)}, \ + {(_tm >> 8) & 0xFF, \ + (_tm & 0xFF)}, \ + {(_th >> 8) & 0xFF, \ + (_th & 0xFF)}, \ + _cl, _ch, \ + { _n0, _n1, _n2, _n3, _n4, _n5 } \ + } #endif /*__ASSEMBLY__*/ #endif /* __SMCCC_H__ */ diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 7335103b..1bdf3c4b 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -127,8 +127,8 @@ * expected. */ #define ARM_ARCH_AT_LEAST(_maj, _min) \ - ((ARM_ARCH_MAJOR > _maj) || \ - ((ARM_ARCH_MAJOR == _maj) && (ARM_ARCH_MINOR >= _min))) + ((ARM_ARCH_MAJOR > (_maj)) || \ + ((ARM_ARCH_MAJOR == (_maj)) && (ARM_ARCH_MINOR >= (_min)))) /* * Import an assembly or linker symbol as a C expression with the specified diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h index 77953177..b6c53e26 100644 --- a/include/lib/xlat_tables/xlat_mmu_helpers.h +++ b/include/lib/xlat_tables/xlat_mmu_helpers.h @@ -48,10 +48,15 @@ #ifdef AARCH32 /* AArch32 specific translation table API */ void enable_mmu_secure(unsigned int flags); + +void enable_mmu_direct(unsigned int flags); #else /* AArch64 specific translation table APIs */ void enable_mmu_el1(unsigned int flags); void enable_mmu_el3(unsigned int flags); + +void enable_mmu_direct_el1(unsigned int flags); +void enable_mmu_direct_el3(unsigned int flags); #endif /* AARCH32 */ int xlat_arch_is_granule_size_supported(size_t size); diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index 98f00d71..4dc2c5ec 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,12 +8,12 @@ #define __XLAT_TABLES_V2_H__ #include <xlat_tables_defs.h> +#include <xlat_tables_v2_helpers.h> #ifndef __ASSEMBLY__ #include <stddef.h> #include <stdint.h> #include <xlat_mmu_helpers.h> -#include <xlat_tables_v2_helpers.h> /* * Default granularity size for an mmap_region_t. diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h index de1c2d4b..e1ea2b64 100644 --- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h +++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,6 +16,13 @@ #error "Do not include this header file directly. Include xlat_tables_v2.h instead." #endif +/* Offsets into mmu_cfg_params array. All parameters are 32 bits wide. */ +#define MMU_CFG_MAIR0 0 +#define MMU_CFG_TCR 1 +#define MMU_CFG_TTBR0_LO 2 +#define MMU_CFG_TTBR0_HI 3 +#define MMU_CFG_PARAM_MAX 4 + #ifndef __ASSEMBLY__ #include <cassert.h> @@ -24,6 +31,9 @@ #include <xlat_tables_arch.h> #include <xlat_tables_defs.h> +/* Parameters of register values required when enabling MMU */ +extern uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; + /* Forward declaration */ struct mmap_region; @@ -162,6 +172,8 @@ struct xlat_ctx { .initialized = 0, \ } +#endif /*__ASSEMBLY__*/ + #if AARCH64 /* @@ -187,6 +199,4 @@ struct xlat_ctx { #endif /* AARCH64 */ -#endif /*__ASSEMBLY__*/ - #endif /* __XLAT_TABLES_V2_HELPERS_H__ */ diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h index 96eefbbe..5e1d680c 100644 --- a/include/plat/arm/board/common/board_arm_def.h +++ b/include/plat/arm/board/common/board_arm_def.h @@ -122,14 +122,6 @@ #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) -/* PSCI memory protect definitions: - * This variable is stored in a non-secure flash because some ARM reference - * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT - * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. - */ -#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ - V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) - /* * Map mem_protect flash region with read and write permissions */ diff --git a/include/plat/arm/css/common/css_pm.h b/include/plat/arm/css/common/css_pm.h index 0f92e60b..e834fffc 100644 --- a/include/plat/arm/css/common/css_pm.h +++ b/include/plat/arm/css/common/css_pm.h @@ -17,9 +17,15 @@ /* Macros to read the CSS power domain state */ #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] -#define CSS_SYSTEM_PWR_STATE(state) \ - ((PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) ?\ - (state)->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] : 0) + +static inline unsigned int css_system_pwr_state(const psci_power_state_t *state) +{ +#if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) + return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL]; +#else + return 0; +#endif +} int css_pwr_domain_on(u_register_t mpidr); void css_pwr_domain_on_finish(const psci_power_state_t *target_state); diff --git a/include/tools_share/firmware_image_package.h b/include/tools_share/firmware_image_package.h index f2585552..b1ce56af 100644 --- a/include/tools_share/firmware_image_package.h +++ b/include/tools_share/firmware_image_package.h @@ -16,64 +16,64 @@ /* ToC Entry UUIDs */ #define UUID_TRUSTED_UPDATE_FIRMWARE_SCP_BL2U \ - {0x03279265, 0x742f, 0x44e6, 0x8d, 0xff, {0x57, 0x9a, 0xc1, 0xff, 0x06, 0x10} } + {{0x65, 0x92, 0x27, 0x03}, {0x2f, 0x74}, {0xe6, 0x44}, 0x8d, 0xff, {0x57, 0x9a, 0xc1, 0xff, 0x06, 0x10} } #define UUID_TRUSTED_UPDATE_FIRMWARE_BL2U \ - {0x37ebb360, 0xe5c1, 0x41ea, 0x9d, 0xf3, {0x19, 0xed, 0xa1, 0x1f, 0x68, 0x01} } + {{0x60, 0xb3, 0xeb, 0x37}, {0xc1, 0xe5}, {0xea, 0x41}, 0x9d, 0xf3, {0x19, 0xed, 0xa1, 0x1f, 0x68, 0x01} } #define UUID_TRUSTED_UPDATE_FIRMWARE_NS_BL2U \ - {0x111d514f, 0xe52b, 0x494e, 0xb4, 0xc5, {0x83, 0xc2, 0xf7, 0x15, 0x84, 0x0a} } + {{0x4f, 0x51, 0x1d, 0x11}, {0x2b, 0xe5}, {0x4e, 0x49}, 0xb4, 0xc5, {0x83, 0xc2, 0xf7, 0x15, 0x84, 0x0a} } #define UUID_TRUSTED_FWU_CERT \ - {0xb28a4071, 0xd618, 0x4c87, 0x8b, 0x2e, {0xc6, 0xdc, 0xcd, 0x50, 0xf0, 0x96} } + {{0x71, 0x40, 0x8a, 0xb2}, {0x18, 0xd6}, {0x87, 0x4c}, 0x8b, 0x2e, {0xc6, 0xdc, 0xcd, 0x50, 0xf0, 0x96} } #define UUID_TRUSTED_BOOT_FIRMWARE_BL2 \ - {0x0becf95f, 0x224d, 0x4d3e, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} } + {{0x5f, 0xf9, 0xec, 0x0b}, {0x4d, 0x22}, {0x3e, 0x4d}, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} } #define UUID_SCP_FIRMWARE_SCP_BL2 \ - {0x3dfd6697, 0xbe89, 0x49e8, 0xae, 0x5d, {0x78, 0xa1, 0x40, 0x60, 0x82, 0x13} } + {{0x97, 0x66, 0xfd, 0x3d}, {0x89, 0xbe}, {0xe8, 0x49}, 0xae, 0x5d, {0x78, 0xa1, 0x40, 0x60, 0x82, 0x13} } #define UUID_EL3_RUNTIME_FIRMWARE_BL31 \ - {0x6d08d447, 0xfe4c, 0x4698, 0x9b, 0x95, {0x29, 0x50, 0xcb, 0xbd, 0x5a, 0x00} } + {{0x47, 0xd4, 0x08, 0x6d}, {0x4c, 0xfe}, {0x98, 0x46}, 0x9b, 0x95, {0x29, 0x50, 0xcb, 0xbd, 0x5a, 0x00} } #define UUID_SECURE_PAYLOAD_BL32 \ - {0x89e1d005, 0xdc53, 0x4713, 0x8d, 0x2b, {0x50, 0x0a, 0x4b, 0x7a, 0x3e, 0x38} } + {{0x05, 0xd0, 0xe1, 0x89}, {0x53, 0xdc}, {0x13, 0x47}, 0x8d, 0x2b, {0x50, 0x0a, 0x4b, 0x7a, 0x3e, 0x38} } #define UUID_SECURE_PAYLOAD_BL32_EXTRA1 \ - {0x9bc2700b, 0x5a2a, 0x4078, 0x9f, 0x65, {0x0a, 0x56, 0x82, 0x73, 0x82, 0x88} } + {{0x0b, 0x70, 0xc2, 0x9b}, {0x2a, 0x5a}, {0x78, 0x40}, 0x9f, 0x65, {0x0a, 0x56, 0x82, 0x73, 0x82, 0x88} } #define UUID_SECURE_PAYLOAD_BL32_EXTRA2 \ - {0xb17ba88e, 0xa2cf, 0x4d3f, 0x85, 0xfd, {0xe7, 0xbb, 0xa5, 0x02, 0x20, 0xd9} } + {{0x8e, 0xa8, 0x7b, 0xb1}, {0xcf, 0xa2}, {0x3f, 0x4d}, 0x85, 0xfd, {0xe7, 0xbb, 0xa5, 0x02, 0x20, 0xd9} } #define UUID_NON_TRUSTED_FIRMWARE_BL33 \ - {0xa7eed0d6, 0xeafc, 0x4bd5, 0x97, 0x82, {0x99, 0x34, 0xf2, 0x34, 0xb6, 0xe4} } + {{0xd6, 0xd0, 0xee, 0xa7}, {0xfc, 0xea}, {0xd5, 0x4b}, 0x97, 0x82, {0x99, 0x34, 0xf2, 0x34, 0xb6, 0xe4} } /* Key certificates */ #define UUID_ROT_KEY_CERT \ - {0x721d2d86, 0x60f8, 0x11e4, 0x92, 0x0b, {0x8b, 0xe7, 0x62, 0x16, 0x0f, 0x24} } + {{0x86, 0x2d, 0x1d, 0x72}, {0xf8, 0x60}, {0xe4, 0x11}, 0x92, 0x0b, {0x8b, 0xe7, 0x62, 0x16, 0x0f, 0x24} } #define UUID_TRUSTED_KEY_CERT \ - {0x90e87e82, 0x60f8, 0x11e4, 0xa1, 0xb4, {0x77, 0x7a, 0x21, 0xb4, 0xf9, 0x4c} } + {{0x82, 0x7e, 0xe8, 0x90}, {0xf8, 0x60}, {0xe4, 0x11}, 0xa1, 0xb4, {0x77, 0x7a, 0x21, 0xb4, 0xf9, 0x4c} } #define UUID_NON_TRUSTED_WORLD_KEY_CERT \ - {0x3d87671c, 0x635f, 0x11e4, 0x97, 0x8d, {0x27, 0xc0, 0xc7, 0x14, 0x8a, 0xbd} } + {{0x1c, 0x67, 0x87, 0x3d}, {0x5f, 0x63}, {0xe4, 0x11}, 0x97, 0x8d, {0x27, 0xc0, 0xc7, 0x14, 0x8a, 0xbd} } #define UUID_SCP_FW_KEY_CERT \ - {0xa1214202, 0x60f8, 0x11e4, 0x8d, 0x9b, {0xf3, 0x3c, 0x0e, 0x15, 0xa0, 0x14} } + {{0x02, 0x42, 0x21, 0xa1}, {0xf8, 0x60}, {0xe4, 0x11}, 0x8d, 0x9b, {0xf3, 0x3c, 0x0e, 0x15, 0xa0, 0x14} } #define UUID_SOC_FW_KEY_CERT \ - {0xccbeb88a, 0x60f9, 0x11e4, 0x9a, 0xd0, {0xeb, 0x48, 0x22, 0xd8, 0xdc, 0xf8} } + {{0x8a, 0xb8, 0xbe, 0xcc}, {0xf9, 0x60}, {0xe4, 0x11}, 0x9a, 0xd0, {0xeb, 0x48, 0x22, 0xd8, 0xdc, 0xf8} } #define UUID_TRUSTED_OS_FW_KEY_CERT \ - {0x03d67794, 0x60fb, 0x11e4, 0x85, 0xdd, {0xb7, 0x10, 0x5b, 0x8c, 0xee, 0x04} } + {{0x94, 0x77, 0xd6, 0x03}, {0xfb, 0x60}, {0xe4, 0x11}, 0x85, 0xdd, {0xb7, 0x10, 0x5b, 0x8c, 0xee, 0x04} } #define UUID_NON_TRUSTED_FW_KEY_CERT \ - {0x2a83d58a, 0x60fb, 0x11e4, 0x8a, 0xaf, {0xdf, 0x30, 0xbb, 0xc4, 0x98, 0x59} } + {{0x8a, 0xd5, 0x83, 0x2a}, {0xfb, 0x60}, {0xe4, 0x11}, 0x8a, 0xaf, {0xdf, 0x30, 0xbb, 0xc4, 0x98, 0x59} } /* Content certificates */ #define UUID_TRUSTED_BOOT_FW_CERT \ - {0xea69e2d6, 0x635d, 0x11e4, 0x8d, 0x8c, {0x9f, 0xba, 0xbe, 0x99, 0x56, 0xa5} } + {{0xd6, 0xe2, 0x69, 0xea}, {0x5d, 0x63}, {0xe4, 0x11}, 0x8d, 0x8c, {0x9f, 0xba, 0xbe, 0x99, 0x56, 0xa5} } #define UUID_SCP_FW_CONTENT_CERT \ - {0x046fbe44, 0x635e, 0x11e4, 0xb2, 0x8b, {0x73, 0xd8, 0xea, 0xae, 0x96, 0x56} } + {{0x44, 0xbe, 0x6f, 0x04}, {0x5e, 0x63}, {0xe4, 0x11}, 0xb2, 0x8b, {0x73, 0xd8, 0xea, 0xae, 0x96, 0x56} } #define UUID_SOC_FW_CONTENT_CERT \ - {0x200cb2e2, 0x635e, 0x11e4, 0x9c, 0xe8, {0xab, 0xcc, 0xf9, 0x2b, 0xb6, 0x66} } + {{0xe2, 0xb2, 0x0c, 0x20}, {0x5e, 0x63}, {0xe4, 0x11}, 0x9c, 0xe8, {0xab, 0xcc, 0xf9, 0x2b, 0xb6, 0x66} } #define UUID_TRUSTED_OS_FW_CONTENT_CERT \ - {0x11449fa4, 0x635e, 0x11e4, 0x87, 0x28, {0x3f, 0x05, 0x72, 0x2a, 0xf3, 0x3d} } + {{0xa4, 0x9f, 0x44, 0x11}, {0x5e, 0x63}, {0xe4, 0x11}, 0x87, 0x28, {0x3f, 0x05, 0x72, 0x2a, 0xf3, 0x3d} } #define UUID_NON_TRUSTED_FW_CONTENT_CERT \ - {0xf3c1c48e, 0x635d, 0x11e4, 0xa7, 0xa9, {0x87, 0xee, 0x40, 0xb2, 0x3f, 0xa7} } + {{0x8e, 0xc4, 0xc1, 0xf3}, {0x5d, 0x63}, {0xe4, 0x11}, 0xa7, 0xa9, {0x87, 0xee, 0x40, 0xb2, 0x3f, 0xa7} } /* Dynamic configs */ #define UUID_HW_CONFIG \ - {0xd9f1b808, 0xcfc9, 0x4993, 0xa9, 0x62, {0x6f, 0xbc, 0x6b, 0x72, 0x65, 0xcc} } + {{0x08, 0xb8, 0xf1, 0xd9}, {0xc9, 0xcf}, {0x93, 0x49}, 0xa9, 0x62, {0x6f, 0xbc, 0x6b, 0x72, 0x65, 0xcc} } #define UUID_TB_FW_CONFIG \ - {0xff58046c, 0x6baf, 0x4f7d, 0x82, 0xed, {0xaa, 0x27, 0xbc, 0x69, 0xbf, 0xd2} } + {{0x6c, 0x04, 0x58, 0xff}, {0xaf, 0x6b}, {0x7d, 0x4f}, 0x82, 0xed, {0xaa, 0x27, 0xbc, 0x69, 0xbf, 0xd2} } #define UUID_SOC_FW_CONFIG \ - {0x4b817999, 0x7603, 0x46fb, 0x8c, 0x8e, {0x8d, 0x26, 0x7f, 0x78, 0x59, 0xe0} } + {{0x99, 0x79, 0x81, 0x4b}, {0x03, 0x76}, {0xfb, 0x46}, 0x8c, 0x8e, {0x8d, 0x26, 0x7f, 0x78, 0x59, 0xe0} } #define UUID_TOS_FW_CONFIG \ - {0x1a7c2526, 0xc6bd, 0x477f, 0x8d, 0x96, {0xc4, 0xc4, 0xb0, 0x24, 0x80, 0x21} } + {{0x26, 0x25, 0x7c, 0x1a}, {0xdb, 0xc6}, {0x7f, 0x47}, 0x8d, 0x96, {0xc4, 0xc4, 0xb0, 0x24, 0x80, 0x21} } #define UUID_NT_FW_CONFIG \ - {0x1598da28, 0xe893, 0x447e, 0xac, 0x66, {0x1a, 0xaf, 0x80, 0x15, 0x50, 0xf9} } + {{0x28, 0xda, 0x98, 0x15}, {0x93, 0xe8}, {0x7e, 0x44}, 0xac, 0x66, {0x1a, 0xaf, 0x80, 0x15, 0x50, 0xf9} } typedef struct fip_toc_header { uint32_t name; diff --git a/include/tools_share/uuid.h b/include/tools_share/uuid.h index 6d935bd6..f3ac4af5 100644 --- a/include/tools_share/uuid.h +++ b/include/tools_share/uuid.h @@ -48,9 +48,9 @@ * A DCE 1.1 compatible source representation of UUIDs. */ struct uuid { - uint32_t time_low; - uint16_t time_mid; - uint16_t time_hi_and_version; + uint8_t time_low[4]; + uint8_t time_mid[2]; + uint8_t time_hi_and_version[2]; uint8_t clock_seq_hi_and_reserved; uint8_t clock_seq_low; uint8_t node[_UUID_NODE_LEN]; diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c index 720d4461..dd639397 100644 --- a/lib/xlat_tables/aarch32/xlat_tables.c +++ b/lib/xlat_tables/aarch32/xlat_tables.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -130,3 +130,8 @@ void enable_mmu_secure(unsigned int flags) /* Ensure the MMU enable takes effect immediately */ isb(); } + +void enable_mmu_direct(unsigned int flags) +{ + enable_mmu_secure(flags); +} diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c index a72c6454..5717516a 100644 --- a/lib/xlat_tables/aarch64/xlat_tables.c +++ b/lib/xlat_tables/aarch64/xlat_tables.c @@ -181,6 +181,11 @@ void init_xlat_tables(void) \ /* Ensure the MMU enable takes effect immediately */ \ isb(); \ + } \ + \ + void enable_mmu_direct_el##_el(unsigned int flags) \ + { \ + enable_mmu_el##_el(flags); \ } /* Define EL1 and EL3 variants of the function enabling the MMU */ diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h index 50d6bd59..810c48e1 100644 --- a/lib/xlat_tables/xlat_tables_private.h +++ b/lib/xlat_tables/xlat_tables_private.h @@ -11,6 +11,10 @@ #include <platform_def.h> #include <xlat_tables_arch.h> +#if HW_ASSISTED_COHERENCY +#error xlat tables v2 must be used with HW_ASSISTED_COHERENCY +#endif + /* * If the platform hasn't defined a physical and a virtual address space size * default to ADDR_SPACE_SIZE. diff --git a/lib/xlat_tables_v2/aarch32/enable_mmu.S b/lib/xlat_tables_v2/aarch32/enable_mmu.S new file mode 100644 index 00000000..97cdde75 --- /dev/null +++ b/lib/xlat_tables_v2/aarch32/enable_mmu.S @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <assert_macros.S> +#include <xlat_tables_v2.h> + + .global enable_mmu_direct + +func enable_mmu_direct + /* Assert that MMU is turned off */ +#if ENABLE_ASSERTIONS + ldcopr r1, SCTLR + tst r1, #SCTLR_M_BIT + ASM_ASSERT(eq) +#endif + + /* Invalidate TLB entries */ + TLB_INVALIDATE(r0, TLBIALL) + + mov r3, r0 + ldr r0, =mmu_cfg_params + + /* MAIR0 */ + ldr r1, [r0, #(MMU_CFG_MAIR0 << 2)] + stcopr r1, MAIR0 + + /* TTBCR */ + ldr r2, [r0, #(MMU_CFG_TCR << 2)] + stcopr r2, TTBCR + + /* TTBR0 */ + ldr r1, [r0, #(MMU_CFG_TTBR0_LO << 2)] + ldr r2, [r0, #(MMU_CFG_TTBR0_HI << 2)] + stcopr16 r1, r2, TTBR0_64 + + /* TTBR1 is unused right now; set it to 0. */ + mov r1, #0 + mov r2, #0 + stcopr16 r1, r2, TTBR1_64 + + /* + * Ensure all translation table writes have drained into memory, the TLB + * invalidation is complete, and translation register writes are + * committed before enabling the MMU + */ + dsb ish + isb + + /* Enable enable MMU by honoring flags */ + ldcopr r1, SCTLR + ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT) + orr r1, r1, r2 + + /* Clear C bit if requested */ + tst r3, #DISABLE_DCACHE + bicne r1, r1, #SCTLR_C_BIT + + stcopr r1, SCTLR + isb + + bx lr +endfunc enable_mmu_direct diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c index f66f802f..94dcf578 100644 --- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,6 +18,8 @@ #error ARMv7 target does not support LPAE MMU descriptors #endif +uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; + /* * Returns 1 if the provided granule size is supported, 0 otherwise. */ @@ -109,22 +111,16 @@ int xlat_arch_current_el(void) * Function for enabling the MMU in Secure PL1, assuming that the page tables * have already been created. ******************************************************************************/ -void enable_mmu_arch(unsigned int flags, - uint64_t *base_table, +void setup_mmu_cfg(unsigned int flags, + const uint64_t *base_table, unsigned long long max_pa, uintptr_t max_va) { - u_register_t mair0, ttbcr, sctlr; + u_register_t mair0, ttbcr; uint64_t ttbr0; assert(IS_IN_SECURE()); - sctlr = read_sctlr(); - assert((sctlr & SCTLR_M_BIT) == 0); - - /* Invalidate TLBs at the current exception level */ - tlbiall(); - /* Set attributes in the right indices of the MAIR */ mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, @@ -185,30 +181,9 @@ void enable_mmu_arch(unsigned int flags, ttbr0 |= TTBR_CNP_BIT; #endif - /* Now program the relevant system registers */ - write_mair0(mair0); - write_ttbcr(ttbcr); - write64_ttbr0(ttbr0); - write64_ttbr1(0); - - /* - * Ensure all translation table writes have drained - * into memory, the TLB invalidation is complete, - * and translation register writes are committed - * before enabling the MMU - */ - dsbish(); - isb(); - - sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; - - if (flags & DISABLE_DCACHE) - sctlr &= ~SCTLR_C_BIT; - else - sctlr |= SCTLR_C_BIT; - - write_sctlr(sctlr); - - /* Ensure the MMU enable takes effect immediately */ - isb(); + /* Now populate MMU configuration */ + mmu_cfg_params[MMU_CFG_MAIR0] = mair0; + mmu_cfg_params[MMU_CFG_TCR] = ttbcr; + mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr0; + mmu_cfg_params[MMU_CFG_TTBR0_HI] = ttbr0 >> 32; } diff --git a/lib/xlat_tables_v2/aarch64/enable_mmu.S b/lib/xlat_tables_v2/aarch64/enable_mmu.S new file mode 100644 index 00000000..a72c7fae --- /dev/null +++ b/lib/xlat_tables_v2/aarch64/enable_mmu.S @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <assert_macros.S> +#include <xlat_tables_v2.h> + + .global enable_mmu_direct_el1 + .global enable_mmu_direct_el3 + + /* Macros to read and write to system register for a given EL. */ + .macro _msr reg_name, el, gp_reg + msr \reg_name\()_el\()\el, \gp_reg + .endm + + .macro _mrs gp_reg, reg_name, el + mrs \gp_reg, \reg_name\()_el\()\el + .endm + + .macro define_mmu_enable_func el + func enable_mmu_direct_\()el\el +#if ENABLE_ASSERTIONS + _mrs x1, sctlr, \el + tst x1, #SCTLR_M_BIT + ASM_ASSERT(eq) +#endif + + /* Invalidate TLB entries */ + .if \el == 1 + TLB_INVALIDATE(vmalle1) + .else + .if \el == 3 + TLB_INVALIDATE(alle3) + .else + .error "EL must be 1 or 3" + .endif + .endif + + mov x7, x0 + ldr x0, =mmu_cfg_params + + /* MAIR */ + ldr w1, [x0, #(MMU_CFG_MAIR0 << 2)] + _msr mair, \el, x1 + + /* TCR */ + ldr w2, [x0, #(MMU_CFG_TCR << 2)] + _msr tcr, \el, x2 + + /* TTBR */ + ldr w3, [x0, #(MMU_CFG_TTBR0_LO << 2)] + ldr w4, [x0, #(MMU_CFG_TTBR0_HI << 2)] + orr x3, x3, x4, lsl #32 + _msr ttbr0, \el, x3 + + /* + * Ensure all translation table writes have drained into memory, the TLB + * invalidation is complete, and translation register writes are + * committed before enabling the MMU + */ + dsb ish + isb + + /* Set and clear required fields of SCTLR */ + _mrs x4, sctlr, \el + mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT + orr x4, x4, x5 + + /* Additionally, amend SCTLR fields based on flags */ + bic x5, x4, #SCTLR_C_BIT + tst x7, #DISABLE_DCACHE + csel x4, x5, x4, ne + + _msr sctlr, \el, x4 + isb + + ret + endfunc enable_mmu_direct_\()el\el + .endm + + /* + * Define MMU-enabling functions for EL1 and EL3: + * + * enable_mmu_direct_el1 + * enable_mmu_direct_el3 + */ + define_mmu_enable_func 1 + define_mmu_enable_func 3 diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index c501e707..71b9c8fa 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c @@ -16,6 +16,8 @@ #include <xlat_tables_v2.h> #include "../xlat_tables_private.h" +uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; + /* * Returns 1 if the provided granule size is supported, 0 otherwise. */ @@ -183,70 +185,13 @@ int xlat_arch_current_el(void) return el; } -/******************************************************************************* - * Macro generating the code for the function enabling the MMU in the given - * exception level, assuming that the pagetables have already been created. - * - * _el: Exception level at which the function will run - * _tlbi_fct: Function to invalidate the TLBs at the current - * exception level - ******************************************************************************/ -#define DEFINE_ENABLE_MMU_EL(_el, _tlbi_fct) \ - static void enable_mmu_internal_el##_el(int flags, \ - uint64_t mair, \ - uint64_t tcr, \ - uint64_t ttbr) \ - { \ - uint32_t sctlr = read_sctlr_el##_el(); \ - assert((sctlr & SCTLR_M_BIT) == 0); \ - \ - /* Invalidate TLBs at the current exception level */ \ - _tlbi_fct(); \ - \ - write_mair_el##_el(mair); \ - write_tcr_el##_el(tcr); \ - \ - /* Set TTBR bits as well */ \ - if (ARM_ARCH_AT_LEAST(8, 2)) { \ - /* Enable CnP bit so as to share page tables */ \ - /* with all PEs. This is mandatory for */ \ - /* ARMv8.2 implementations. */ \ - ttbr |= TTBR_CNP_BIT; \ - } \ - write_ttbr0_el##_el(ttbr); \ - \ - /* Ensure all translation table writes have drained */ \ - /* into memory, the TLB invalidation is complete, */ \ - /* and translation register writes are committed */ \ - /* before enabling the MMU */ \ - dsbish(); \ - isb(); \ - \ - sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ - if (flags & DISABLE_DCACHE) \ - sctlr &= ~SCTLR_C_BIT; \ - else \ - sctlr |= SCTLR_C_BIT; \ - \ - write_sctlr_el##_el(sctlr); \ - \ - /* Ensure the MMU enable takes effect immediately */ \ - isb(); \ - } - -/* Define EL1 and EL3 variants of the function enabling the MMU */ -#if IMAGE_EL == 1 -DEFINE_ENABLE_MMU_EL(1, tlbivmalle1) -#elif IMAGE_EL == 3 -DEFINE_ENABLE_MMU_EL(3, tlbialle3) -#endif - -void enable_mmu_arch(unsigned int flags, - uint64_t *base_table, +void setup_mmu_cfg(unsigned int flags, + const uint64_t *base_table, unsigned long long max_pa, uintptr_t max_va) { uint64_t mair, ttbr, tcr; + uintptr_t virtual_addr_space_size; /* Set attributes in the right indices of the MAIR. */ mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); @@ -256,27 +201,25 @@ void enable_mmu_arch(unsigned int flags, ttbr = (uint64_t) base_table; /* - * Set TCR bits as well. - */ - - /* * Limit the input address ranges and memory region sizes translated * using TTBR0 to the given virtual address space size. */ - assert(max_va < UINTPTR_MAX); - uintptr_t virtual_addr_space_size = max_va + 1; + assert(max_va < ((uint64_t) UINTPTR_MAX)); + + virtual_addr_space_size = max_va + 1; assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); + /* * __builtin_ctzll(0) is undefined but here we are guaranteed that * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. */ - tcr = 64 - __builtin_ctzll(virtual_addr_space_size); + tcr = (uint64_t) 64 - __builtin_ctzll(virtual_addr_space_size); /* * Set the cacheability and shareability attributes for memory * associated with translation table walks. */ - if (flags & XLAT_TABLE_NC) { + if ((flags & XLAT_TABLE_NC) != 0) { /* Inner & outer non-cacheable non-shareable. */ tcr |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; @@ -299,10 +242,23 @@ void enable_mmu_arch(unsigned int flags, * translated using TTBR1_EL1. */ tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); - enable_mmu_internal_el1(flags, mair, tcr, ttbr); #elif IMAGE_EL == 3 assert(IS_IN_EL(3)); tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); - enable_mmu_internal_el3(flags, mair, tcr, ttbr); #endif + + mmu_cfg_params[MMU_CFG_MAIR0] = (uint32_t) mair; + mmu_cfg_params[MMU_CFG_TCR] = (uint32_t) tcr; + + /* Set TTBR bits as well */ + if (ARM_ARCH_AT_LEAST(8, 2)) { + /* + * Enable CnP bit so as to share page tables with all PEs. This + * is mandatory for ARMv8.2 implementations. + */ + ttbr |= TTBR_CNP_BIT; + } + + mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr; + mmu_cfg_params[MMU_CFG_TTBR0_HI] = (uint32_t) (ttbr >> 32); } diff --git a/lib/xlat_tables_v2/xlat_tables.mk b/lib/xlat_tables_v2/xlat_tables.mk index 06dd844a..1e70f37f 100644 --- a/lib/xlat_tables_v2/xlat_tables.mk +++ b/lib/xlat_tables_v2/xlat_tables.mk @@ -1,10 +1,11 @@ # -# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # XLAT_TABLES_LIB_SRCS := $(addprefix lib/xlat_tables_v2/, \ + ${ARCH}/enable_mmu.S \ ${ARCH}/xlat_tables_arch.c \ xlat_tables_internal.c) diff --git a/lib/xlat_tables_v2/xlat_tables_internal.c b/lib/xlat_tables_v2/xlat_tables_internal.c index 5beb51e9..7f1d3958 100644 --- a/lib/xlat_tables_v2/xlat_tables_internal.c +++ b/lib/xlat_tables_v2/xlat_tables_internal.c @@ -802,7 +802,7 @@ void mmap_add_region_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm) * that there is free space. */ assert(mm_last->size == 0U); - + /* Make room for new region by moving other regions up by one place */ mm_destination = mm_cursor + 1; memmove(mm_destination, mm_cursor, @@ -1313,22 +1313,25 @@ void init_xlat_tables(void) void enable_mmu_secure(unsigned int flags) { - enable_mmu_arch(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, + setup_mmu_cfg(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, tf_xlat_ctx.va_max_address); + enable_mmu_direct(flags); } #else void enable_mmu_el1(unsigned int flags) { - enable_mmu_arch(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, + setup_mmu_cfg(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, tf_xlat_ctx.va_max_address); + enable_mmu_direct_el1(flags); } void enable_mmu_el3(unsigned int flags) { - enable_mmu_arch(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, + setup_mmu_cfg(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, tf_xlat_ctx.va_max_address); + enable_mmu_direct_el3(flags); } #endif /* AARCH32 */ diff --git a/lib/xlat_tables_v2/xlat_tables_private.h b/lib/xlat_tables_v2/xlat_tables_private.h index 157dd039..777189fb 100644 --- a/lib/xlat_tables_v2/xlat_tables_private.h +++ b/lib/xlat_tables_v2/xlat_tables_private.h @@ -81,7 +81,7 @@ int xlat_arch_current_el(void); unsigned long long xlat_arch_get_max_supported_pa(void); /* Enable MMU and configure it to use the specified translation tables. */ -void enable_mmu_arch(unsigned int flags, uint64_t *base_table, +void setup_mmu_cfg(unsigned int flags, const uint64_t *base_table, unsigned long long max_pa, uintptr_t max_va); /* diff --git a/maintainers.rst b/maintainers.rst index 4466a56e..94bb5d31 100644 --- a/maintainers.rst +++ b/maintainers.rst @@ -7,190 +7,168 @@ parts of the codebase is delegated to the sub-maintainers listed below. An acknowledgement from these sub-maintainers may be required before the maintainers merge a contribution. -Maintainers ------------ - -Dan Handley (dan.handley@arm.com, `danh-arm`_) - -David Cunado (david.cunado@arm.com, `davidcunado-arm`_) - -OPTEE and QEMU platform sub-maintainer --------------------------------------- - -Jens Wiklander (jens.wiklander@linaro.org, `jenswi-linaro`_) - -Files: - -- docs/plat/qemu.rst -- docs/spd/optee-dispatcher.rst -- services/spd/opteed/\* -- plat/qemu/\* - -TLK/Trusty SPDs and NVidia platforms sub-maintainer ---------------------------------------------------- - -Varun Wadekar (vwadekar@nvidia.com, `vwadekar`_) - -Files: - -- docs/plat/nvidia-tegra.rst -- docs/spd/tlk-dispatcher.rst -- docs/spd/trusty-dispatcher.rst -- include/bl32/payloads/tlk.h -- include/lib/cpus/aarch64/denver.h -- lib/cpus/aarch64/denver.S -- services/spd/tlkd/\* -- services/spd/trusty/\* -- plat/nvidia/\* - -eMMC/UFS drivers and HiSilicon HiKey and HiKey960 platform sub-maintainer -------------------------------------------------------------------------- - -Haojian Zhuang (haojian.zhuang@linaro.org, `hzhuang1`_) - -Files: - -- docs/plat/hikey.rst -- docs/plat/hikey960.rst -- drivers/emmc/\* -- drivers/partition/\* -- drivers/synopsys/emmc/\* -- drivers/synopsys/ufs/\* -- drivers/ufs/\* -- include/drivers/dw\_ufs.h -- include/drivers/emmc.h -- include/drivers/ufs.h -- include/drivers/synopsys/dw\_mmc.h -- plat/hisilicon/hikey/\* -- plat/hisilicon/hikey960/\* - -Allwinner ARMv8 platform sub-maintainer ---------------------------------------- - -Andre Przywara (andre.przywara@arm.com, `Andre-ARM`_) - -Files: - -- docs/plat/allwinner.rst -- plat/allwinner/\* - -HiSilicon Poplar platform sub-maintainer ----------------------------------------- - -Shawn Guo (shawn.guo@linaro.org, `shawnguo2`_) - -Files: - -- docs/plat/poplar.rst -- plat/hisilicon/poplar/\* - -MediaTek platform sub-maintainer --------------------------------- - -Yidi Lin (林以廸 yidi.lin@mediatek.com, `mtk09422`_) - -Files: - -- plat/mediatek/\* - -NXP QorIQ Layerscape platform sub-maintainer --------------------------------------- -Jiafei Pan (jiafei.pan@nxp.com, `qoriq-open-source`_) - -Files: - -- docs/plat/ls1043a.rst -- plat/layerscape/\* - -NXP i.MX 8 platform sub-maintainer --------------------------------------- - -Anson Huang (Anson.Huang@nxp.com, `Anson-Huang`_) - -Files: - -- docs/plat/imx8.rst -- plat/imx/\* - -Raspberry Pi 3 platform sub-maintainer --------------------------------------- - -Antonio Niño Díaz (antonio.ninodiaz@arm.com, `antonio-nino-diaz-arm`_) - -Files: - -- docs/plat/rpi3.rst -- plat/rpi3/\* - -RockChip platform sub-maintainer --------------------------------- - -Tony Xie (tony.xie@rock-chips.com, `TonyXie06`_ -or `rockchip-linux`_) - -Files: - -- plat/rockchip/\* - -Synquacer platform sub-maintainer ---------------------------------- - -Sumit Garg (sumit.garg@linaro.org, `b49020`_) - -Files: - -- docs/plat/synquacer.rst -- plat/socionext/synquacer/\* - -Texas Instruments platform sub-maintainer ------------------------------------------ - -Andrew F. Davis (afd@ti.com, `glneo`_) - -Files: - -- docs/plat/ti-k3.rst -- plat/ti/\* - -UniPhier platform sub-maintainer --------------------------------- - -Masahiro Yamada (yamada.masahiro@socionext.com, `masahir0y`_) - -Files: - -- docs/plat/socionext-uniphier.rst -- plat/socionext/\* - -Xilinx platform sub-maintainer +Main maintainers +---------------- +:M: Dan Handley <dan.handley@arm.com> +:G: `danh-arm`_ +:M: Dimitris Papastamos <dimitrs.papastamos@arm.com> +:G: `dp-arm`_ +:M: Soby Mathew <soby.mathew@arm.com> +:G: `soby-mathew`_ + +Allwinner ARMv8 platform port +----------------------------- +:M: Andre Przywara <andre.przywara@arm.com> +:G: `Andre-ARM`_ +:F: docs/plat/allwinner.rst +:F: plat/allwinner/ + +Armv7-A architecture port +------------------------- +:M: Etienne Carriere <etienne.carriere@linaro.org> +:G: `etienne-lms`_ + +eMMC/UFS drivers +---------------- +:M: Haojian Zhuang <haojian.zhuang@linaro.org> +:G: `hzhuang1`_ +:F: drivers/emmc/ +:F: drivers/partition/ +:F: drivers/synopsys/emmc/ +:F: drivers/synopsys/ufs/ +:F: drivers/ufs/ +:F: include/drivers/dw_ufs.h +:F: include/drivers/emmc.h +:F: include/drivers/ufs.h +:F: include/drivers/synopsys/dw_mmc.h + +HiSilicon HiKey and HiKey960 platform ports +------------------------------------------- +:M: Haojian Zhuang <haojian.zhuang@linaro.org> +:G: `hzhuang1`_ +:F: docs/plat/hikey.rst +:F: docs/plat/hikey960.rst +:F: plat/hisilicon/hikey/ +:F: plat/hisilicon/hikey960/ + +HiSilicon Poplar platform port ------------------------------ - -Siva Durga Prasad Paladugu (siva.durga.paladugu@xilinx.com, `sivadur`_) - -Files: - -- docs/plat/xilinx-zynqmp.rst -- plat/xilinx/\* - -Armv7-A architecture sub-maintainer +:M: Shawn Guo <shawn.guo@linaro.org> +:G: `shawnguo2`_ +:F: docs/plat/poplar.rst +:F: plat/hisilicon/poplar/ + +MediaTek platform ports +----------------------- +:M: Yidi Lin (林以廸) <yidi.lin@mediatek.com> +:G: `mtk09422`_ +:F: plat/mediatek/ + +NVidia platform ports +--------------------- +:M: Varun Wadekar <vwadekar@nvidia.com> +:G: `vwadekar`_ +:F: docs/plat/nvidia-tegra.rst +:F: include/lib/cpus/aarch64/denver.h +:F: lib/cpus/aarch64/denver.S +:F: plat/nvidia/ + +NXP QorIQ Layerscape platform ports ----------------------------------- +:M: Jiafei Pan <jiafei.pan@nxp.com> +:G: `qoriq-open-source`_ +:F: docs/plat/ls1043a.rst +:F: plat/layerscape/ + +NXP i.MX 8 platform port +------------------------ +:M: Anson Huang <Anson.Huang@nxp.com> +:G: `Anson-Huang`_ +:F: docs/plat/imx8.rst +:F: plat/imx/ + +OP-TEE dispatcher +----------------- +:M: Jens Wiklander <jens.wiklander@linaro.org> +:G: `jenswi-linaro`_ +:F: docs/spd/optee-dispatcher.rst +:F: services/spd/opteed/ + +QEMU platform port +------------------ +:M: Jens Wiklander <jens.wiklander@linaro.org> +:G: `jenswi-linaro`_ +:F: docs/plat/qemu.rst +:F: plat/qemu/ + +Raspberry Pi 3 platform port +---------------------------- +:M: Antonio Niño Díaz <antonio.ninodiaz@arm.com> +:G: `antonio-nino-diaz-arm`_ +:F: docs/plat/rpi3.rst +:F: plat/rpi3/ + +RockChip platform port +---------------------- +:M: Tony Xie <tony.xie@rock-chips.com> +:G: `TonyXie06`_ +:G: `rockchip-linux`_ +:F: plat/rockchip/ + +Synquacer platform port +----------------------- +:M: Sumit Garg <sumit.garg@linaro.org> +:G: `b49020`_ +:F: docs/plat/synquacer.rst +:F: plat/socionext/synquacer/ + +Texas Instruments platform port +------------------------------- +:M: Andrew F. Davis <afd@ti.com> +:G: `glneo`_ +:F: docs/plat/ti-k3.rst +:F: plat/ti/ + +TLK/Trusty secure payloads +-------------------------- +:M: Varun Wadekar <vwadekar@nvidia.com> +:G: `vwadekar`_ +:F: docs/spd/tlk-dispatcher.rst +:F: docs/spd/trusty-dispatcher.rst +:F: include/bl32/payloads/tlk.h +:F: services/spd/tlkd/ +:F: services/spd/trusty/ + +UniPhier platform port +---------------------- +:M: Masahiro Yamada <yamada.masahiro@socionext.com> +:G: `masahir0y`_ +:F: docs/plat/socionext-uniphier.rst +:F: plat/socionext/uniphier/ + +Xilinx platform port +-------------------- +:M: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> +:G: `sivadur`_ +:F: docs/plat/xilinx-zynqmp.rst +:F: plat/xilinx/ -Etienne Carriere (etienne.carriere@linaro.org, `etienne-lms`_) - +.. _Andre-ARM: https://github.com/Andre-ARM +.. _Anson-Huang: https://github.com/Anson-Huang .. _antonio-nino-diaz-arm: https://github.com/antonio-nino-diaz-arm +.. _b49020: https://github.com/b49020 .. _danh-arm: https://github.com/danh-arm -.. _davidcunado-arm: https://github.com/davidcunado-arm -.. _jenswi-linaro: https://github.com/jenswi-linaro -.. _vwadekar: https://github.com/vwadekar +.. _dp-arm: https://github.com/dp-arm +.. _etienne-lms: https://github.com/etienne-lms +.. _glneo: https://github.com/glneo .. _hzhuang1: https://github.com/hzhuang1 -.. _shawnguo2: https://github.com/shawnguo2 +.. _jenswi-linaro: https://github.com/jenswi-linaro .. _masahir0y: https://github.com/masahir0y .. _mtk09422: https://github.com/mtk09422 -.. _TonyXie06: https://github.com/TonyXie06 -.. _glneo: https://github.com/glneo -.. _sivadur: https://github.com/sivadur -.. _rockchip-linux: https://github.com/rockchip-linux -.. _etienne-lms: https://github.com/etienne-lms .. _qoriq-open-source: https://github.com/qoriq-open-source -.. _Andre-ARM: https://github.com/Andre-ARM -.. _b49020: https://github.com/b49020 +.. _rockchip-linux: https://github.com/rockchip-linux +.. _shawnguo2: https://github.com/shawnguo2 +.. _sivadur: https://github.com/sivadur +.. _soby-mathew: https://github.com/soby-mathew +.. _TonyXie06: https://github.com/TonyXie06 +.. _vwadekar: https://github.com/vwadekar diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts index 716b0237..28299f65 100644 --- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts +++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts @@ -13,7 +13,7 @@ hw_config_addr = <0x0 0x82000000>; hw_config_max_size = <0x01000000>; /* Disable authentication for development */ - disable_auth = <0x1>; + disable_auth = <0x0>; /* * Load SoC and TOS firmware configs at the base of * non shared SRAM. The runtime checks ensure we don't diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h index 5ac5d3cd..acf3cf46 100644 --- a/plat/arm/board/fvp/fvp_def.h +++ b/plat/arm/board/fvp/fvp_def.h @@ -142,4 +142,15 @@ #define FVP_NSAID_HDLCD0 2 #define FVP_NSAID_CLCD 7 +/******************************************************************************* + * Memprotect definitions + ******************************************************************************/ +/* PSCI memory protect definitions: + * This variable is stored in a non-secure flash because some ARM reference + * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT + * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. + */ +#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ + V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + #endif /* __FVP_DEF_H__ */ diff --git a/plat/arm/board/juno/juno_def.h b/plat/arm/board/juno/juno_def.h index d2834e1b..63e24569 100644 --- a/plat/arm/board/juno/juno_def.h +++ b/plat/arm/board/juno/juno_def.h @@ -79,4 +79,15 @@ #define JUNO_IRQ_GPU_SMMU_1 73 #define JUNO_IRQ_ETR_SMMU 75 +/******************************************************************************* + * Memprotect definitions + ******************************************************************************/ +/* PSCI memory protect definitions: + * This variable is stored in a non-secure flash because some ARM reference + * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT + * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. + */ +#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ + V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + #endif /* __JUNO_DEF_H__ */ diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index e5e73041..d141f647 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -118,6 +118,12 @@ void arm_bl1_platform_setup(void) #if LOAD_IMAGE_V2 arm_load_tb_fw_config(); #endif + /* + * Allow access to the System counter timer module and program + * counter frequency for non secure images during FWU + */ + arm_configure_sys_timer(); + write_cntfrq_el0(plat_get_syscnt_freq2()); } void bl1_platform_setup(void) diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c index 7fe61019..bb5b5c6b 100644 --- a/plat/arm/common/arm_sip_svc.c +++ b/plat/arm/common/arm_sip_svc.c @@ -14,9 +14,9 @@ /* ARM SiP Service UUID */ -DEFINE_SVC_UUID(arm_sip_svc_uid, - 0xe2756d55, 0x3360, 0x4bb5, 0xbf, 0xf3, - 0x62, 0x79, 0xfd, 0x11, 0x37, 0xff); +DEFINE_SVC_UUID2(arm_sip_svc_uid, + 0x556d75e2, 0x6033, 0xb54b, 0xb5, 0x75, + 0x62, 0x79, 0xfd, 0x11, 0x37, 0xff); static int arm_sip_setup(void) { diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index 3df5b781..4735a9dc 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c @@ -96,7 +96,7 @@ static void css_pwr_domain_on_finisher_common( void css_pwr_domain_on_finish(const psci_power_state_t *target_state) { /* Assert that the system power domain need not be initialized */ - assert(CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_RUN); + assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); /* Program the gic per-cpu distributor or re-distributor interface */ plat_arm_gic_pcpu_init(); @@ -149,7 +149,7 @@ void css_pwr_domain_suspend(const psci_power_state_t *target_state) css_power_down_common(target_state); /* Perform system domain state saving if issuing system suspend */ - if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) { + if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { arm_system_pwr_domain_save(); /* Power off the Redistributor after having saved its context */ @@ -174,7 +174,7 @@ void css_pwr_domain_suspend_finish( return; /* Perform system domain restore if woken up from system suspend */ - if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) + if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) /* * At this point, the Distributor must be powered on to be ready * to have its state restored. The Redistributor will be powered @@ -264,11 +264,23 @@ static int css_validate_power_state(unsigned int power_state, rc = arm_validate_power_state(power_state, req_state); /* + * Ensure that we don't overrun the pwr_domain_state array in the case + * where the platform supported max power level is less than the system + * power level + */ + +#if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) + + /* * Ensure that the system power domain level is never suspended * via PSCI CPU SUSPEND API. Currently system suspend is only * supported via PSCI SYSTEM SUSPEND API. */ - req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = ARM_LOCAL_STATE_RUN; + + req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = + ARM_LOCAL_STATE_RUN; +#endif + return rc; } diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c index 3a255096..91ea63a4 100644 --- a/plat/arm/css/drivers/scp/css_pm_scmi.c +++ b/plat/arm/css/drivers/scp/css_pm_scmi.c @@ -87,7 +87,7 @@ void css_scp_suspend(const struct psci_power_state *target_state) ARM_LOCAL_STATE_OFF); /* Check if power down at system power domain level is requested */ - if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) { + if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { /* Issue SCMI command for SYSTEM_SUSPEND */ ret = scmi_sys_pwr_state_set(scmi_handle, SCMI_SYS_PWR_FORCEFUL_REQ, diff --git a/plat/arm/css/drivers/scp/css_pm_scpi.c b/plat/arm/css/drivers/scp/css_pm_scpi.c index 23fd80ee..18e71f6e 100644 --- a/plat/arm/css/drivers/scp/css_pm_scpi.c +++ b/plat/arm/css/drivers/scp/css_pm_scpi.c @@ -25,7 +25,7 @@ void css_scp_suspend(const struct psci_power_state *target_state) uint32_t system_state = scpi_power_on; /* Check if power down at system power domain level is requested */ - if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) + if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) system_state = scpi_power_retention; /* Cluster is to be turned off, so disable coherency */ diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h index 0f024076..84ef2c42 100644 --- a/plat/arm/css/sgi/include/platform_def.h +++ b/plat/arm/css/sgi/include/platform_def.h @@ -96,4 +96,16 @@ GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) #endif /* __ASSEMBLY__ */ +/******************************************************************************* + * Memprotect definitions + ******************************************************************************/ +/* PSCI memory protect definitions: + * This variable is stored in a non-secure flash because some ARM reference + * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT + * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. + */ +#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ + V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index 409ae55a..5f2972cc 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c @@ -18,8 +18,6 @@ * provide typical implementations that may be re-used by multiple * platforms but may also be overridden by a platform if required. */ -#pragma weak bl31_plat_enable_mmu -#pragma weak bl32_plat_enable_mmu #pragma weak bl31_plat_runtime_setup #if !ERROR_DEPRECATED #pragma weak plat_get_syscnt_freq2 @@ -33,16 +31,6 @@ #pragma weak plat_ea_handler -void bl31_plat_enable_mmu(uint32_t flags) -{ - enable_mmu_el3(flags); -} - -void bl32_plat_enable_mmu(uint32_t flags) -{ - enable_mmu_el1(flags); -} - void bl31_plat_runtime_setup(void) { #if MULTI_CONSOLE_API diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S index 033a12f8..a413f5fd 100644 --- a/plat/common/aarch64/platform_helpers.S +++ b/plat/common/aarch64/platform_helpers.S @@ -17,6 +17,8 @@ .weak plat_disable_acp .weak bl1_plat_prepare_exit .weak plat_panic_handler + .weak bl31_plat_enable_mmu + .weak bl32_plat_enable_mmu #if !ENABLE_PLAT_COMPAT .globl platform_get_core_pos @@ -164,3 +166,23 @@ func plat_panic_handler wfi b plat_panic_handler endfunc plat_panic_handler + + /* ----------------------------------------------------- + * void bl31_plat_enable_mmu(uint32_t flags); + * + * Enable MMU in BL31. + * ----------------------------------------------------- + */ +func bl31_plat_enable_mmu + b enable_mmu_direct_el3 +endfunc bl31_plat_enable_mmu + + /* ----------------------------------------------------- + * void bl32_plat_enable_mmu(uint32_t flags); + * + * Enable MMU in BL32. + * ----------------------------------------------------- + */ +func bl32_plat_enable_mmu + b enable_mmu_direct_el1 +endfunc bl32_plat_enable_mmu diff --git a/plat/hisilicon/hikey/hisi_sip_svc.c b/plat/hisilicon/hikey/hisi_sip_svc.c index b3109d61..ffa49037 100644 --- a/plat/hisilicon/hikey/hisi_sip_svc.c +++ b/plat/hisilicon/hikey/hisi_sip_svc.c @@ -13,9 +13,9 @@ /* Hisi SiP Service UUID */ -DEFINE_SVC_UUID(hisi_sip_svc_uid, - 0xe599df74, 0x7682, 0x40aa, 0x9f, 0xf8, - 0xc0, 0x85, 0x52, 0xbc, 0x39, 0x3f); +DEFINE_SVC_UUID2(hisi_sip_svc_uid, + 0x74df99e5, 0x8276, 0xaa40, 0x9f, 0xf8, + 0xc0, 0x85, 0x52, 0xbc, 0x39, 0x3f); static int hisi_sip_setup(void) { diff --git a/plat/mediatek/common/custom/oem_svc.c b/plat/mediatek/common/custom/oem_svc.c index c396e2d9..18bda515 100644 --- a/plat/mediatek/common/custom/oem_svc.c +++ b/plat/mediatek/common/custom/oem_svc.c @@ -14,10 +14,9 @@ #include <uuid.h> /* OEM Service UUID */ -DEFINE_SVC_UUID(oem_svc_uid, - 0xb943add0, 0x069d, 0x11e4, 0x91, 0x91, - 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66); - +DEFINE_SVC_UUID2(oem_svc_uid, + 0xd0ad43b9, 0x9b06, 0xe411, 0x91, 0x91, + 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66); /* Setup OEM Services */ static int32_t oem_svc_setup(void) diff --git a/plat/mediatek/common/mtk_sip_svc.c b/plat/mediatek/common/mtk_sip_svc.c index ea8cea00..71eddca3 100644 --- a/plat/mediatek/common/mtk_sip_svc.c +++ b/plat/mediatek/common/mtk_sip_svc.c @@ -14,9 +14,9 @@ #include <uuid.h> /* Mediatek SiP Service UUID */ -DEFINE_SVC_UUID(mtk_sip_svc_uid, - 0xf7582ba4, 0x4262, 0x4d7d, 0x80, 0xe5, - 0x8f, 0x95, 0x05, 0x00, 0x0f, 0x3d); +DEFINE_SVC_UUID2(mtk_sip_svc_uid, + 0xa42b58f7, 0x6242, 0x7d4d, 0x80, 0xe5, + 0x8f, 0x95, 0x05, 0x00, 0x0f, 0x3d); #pragma weak mediatek_plat_sip_handler uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, diff --git a/plat/rockchip/common/rockchip_sip_svc.c b/plat/rockchip/common/rockchip_sip_svc.c index 24805994..d690e92f 100644 --- a/plat/rockchip/common/rockchip_sip_svc.c +++ b/plat/rockchip/common/rockchip_sip_svc.c @@ -13,9 +13,9 @@ #include <uuid.h> /* Rockchip SiP Service UUID */ -DEFINE_SVC_UUID(rk_sip_svc_uid, - 0xe86fc7e2, 0x313e, 0x11e6, 0xb7, 0x0d, - 0x8f, 0x88, 0xee, 0x74, 0x7b, 0x72); +DEFINE_SVC_UUID2(rk_sip_svc_uid, + 0xe2c76fe8, 0x3e31, 0xe611, 0xb7, 0x0d, + 0x8f, 0x88, 0xee, 0x74, 0x7b, 0x72); #pragma weak rockchip_plat_sip_handler uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid, diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index 91602c8c..4d6428b5 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -17,12 +17,18 @@ uintptr_t k3_sec_entrypoint; static void k3_cpu_standby(plat_local_state_t cpu_state) { - /* - * Enter standby state - * dsb is good practice before using wfi to enter low power states - */ + unsigned int scr; + + scr = read_scr_el3(); + /* Enable the Non secure interrupt to wake the CPU */ + write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); + isb(); + /* dsb is good practice before using wfi to enter low power states */ dsb(); + /* Enter standby state */ wfi(); + /* Restore SCR */ + write_scr_el3(scr); } static int k3_pwr_domain_on(u_register_t mpidr) diff --git a/plat/ti/k3/common/k3_topology.c b/plat/ti/k3/common/k3_topology.c index a77c8f34..d7ac0a58 100644 --- a/plat/ti/k3/common/k3_topology.c +++ b/plat/ti/k3/common/k3_topology.c @@ -9,6 +9,7 @@ /* The power domain tree descriptor */ static unsigned char power_domain_tree_desc[] = { + PLATFORM_SYSTEM_COUNT, PLATFORM_CLUSTER_COUNT, K3_CLUSTER0_CORE_COUNT, #if K3_CLUSTER1_MSMC_PORT != UNUSED diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h index 8856af2c..ebc9c477 100644 --- a/plat/ti/k3/include/platform_def.h +++ b/plat/ti/k3/include/platform_def.h @@ -62,9 +62,10 @@ #define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 /******************************************************************************* * Memory layout constants diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c index c7996ce7..9fe709db 100644 --- a/plat/xilinx/zynqmp/sip_svc_setup.c +++ b/plat/xilinx/zynqmp/sip_svc_setup.c @@ -29,9 +29,9 @@ #define is_ipi_fid(_fid) (((_fid) & PM_FID_MASK) == IPI_FID_VALUE) /* SiP Service UUID */ -DEFINE_SVC_UUID(zynqmp_sip_uuid, - 0x2a1d9b5c, 0x8605, 0x4023, 0xa6, 0x1b, - 0xb9, 0x25, 0x82, 0x2d, 0xe3, 0xa5); +DEFINE_SVC_UUID2(zynqmp_sip_uuid, + 0x5c9b1b2a, 0x0586, 0x2340, 0xa6, 0x1b, + 0xb9, 0x25, 0x82, 0x2d, 0xe3, 0xa5); /** * sip_svc_setup() - Setup SiP Service diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c index 5090f063..cee7ef86 100644 --- a/services/spd/tlkd/tlkd_main.c +++ b/services/spd/tlkd/tlkd_main.c @@ -40,9 +40,9 @@ tlk_context_t tlk_ctx; static uint32_t boot_cpu; /* TLK UID: RFC-4122 compliant UUID (version-5, sha-1) */ -DEFINE_SVC_UUID(tlk_uuid, - 0xbd11e9c9, 0x2bba, 0x52ee, 0xb1, 0x72, - 0x46, 0x1f, 0xba, 0x97, 0x7f, 0x63); +DEFINE_SVC_UUID2(tlk_uuid, + 0xc9e911bd, 0xba2b, 0xee52, 0xb1, 0x72, + 0x46, 0x1f, 0xba, 0x97, 0x7f, 0x63); static int32_t tlkd_init(void); diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c index 8cb23b96..3ec98d68 100644 --- a/services/spd/tspd/tspd_main.c +++ b/services/spd/tspd/tspd_main.c @@ -43,9 +43,9 @@ tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; /* TSP UID */ -DEFINE_SVC_UUID(tsp_uuid, - 0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11, - 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); +DEFINE_SVC_UUID2(tsp_uuid, + 0xa056305b, 0x9132, 0x7b42, 0x98, 0x11, + 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); int32_t tspd_init(void); diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c index 41befe5b..1a81a0a3 100644 --- a/services/std_svc/std_svc_setup.c +++ b/services/std_svc/std_svc_setup.c @@ -19,9 +19,13 @@ #include <uuid.h> /* Standard Service UUID */ -DEFINE_SVC_UUID(arm_svc_uid, - 0x108d905b, 0xf863, 0x47e8, 0xae, 0x2d, - 0xc0, 0xfb, 0x56, 0x41, 0xf6, 0xe2); +static uuid_t arm_svc_uid = { + {0x5b, 0x90, 0x8d, 0x10}, + {0x63, 0xf8}, + {0xe8, 0x47}, + 0xae, 0x2d, + {0xc0, 0xfb, 0x56, 0x41, 0xf6, 0xe2} +}; /* Setup Standard Services */ static int32_t std_svc_setup(void) diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c index 4abfe6dd..ed566207 100644 --- a/tools/cert_create/src/main.c +++ b/tools/cert_create/src/main.c @@ -140,8 +140,6 @@ static void print_help(const char *cmd, const struct option *long_opt) i++; } printf("\n"); - - exit(0); } static int get_key_alg(const char *key_alg_str) @@ -334,7 +332,7 @@ int main(int argc, char *argv[]) break; case 'h': print_help(argv[0], cmd_opt); - break; + exit(0); case 'k': save_keys = 1; break; diff --git a/tools/fiptool/fiptool.c b/tools/fiptool/fiptool.c index e4348ee8..0d4f929b 100644 --- a/tools/fiptool/fiptool.c +++ b/tools/fiptool/fiptool.c @@ -51,7 +51,7 @@ static cmd_t cmds[] = { static image_desc_t *image_desc_head; static size_t nr_image_descs; -static uuid_t uuid_null = { 0 }; +static const uuid_t uuid_null; static int verbose; static void vlog(int prio, const char *msg, va_list ap) @@ -241,14 +241,15 @@ static void uuid_to_str(char *s, size_t len, const uuid_t *u) { assert(len >= (_UUID_STR_LEN + 1)); - snprintf(s, len, "%08X-%04X-%04X-%04X-%04X%04X%04X", - u->time_low, - u->time_mid, - u->time_hi_and_version, - ((uint16_t)u->clock_seq_hi_and_reserved << 8) | u->clock_seq_low, - ((uint16_t)u->node[0] << 8) | u->node[1], - ((uint16_t)u->node[2] << 8) | u->node[3], - ((uint16_t)u->node[4] << 8) | u->node[5]); + snprintf(s, len, + "%02X%02X%02X%02X-%02X%02X-%02X%02X-%04X-%04X%04X%04X", + u->time_low[0], u->time_low[1], u->time_low[2], u->time_low[3], + u->time_mid[0], u->time_mid[1], + u->time_hi_and_version[0], u->time_hi_and_version[1], + (u->clock_seq_hi_and_reserved << 8) | u->clock_seq_low, + (u->node[0] << 8) | u->node[1], + (u->node[2] << 8) | u->node[3], + (u->node[4] << 8) | u->node[5]); } static void uuid_from_str(uuid_t *u, const char *s) @@ -261,10 +262,14 @@ static void uuid_from_str(uuid_t *u, const char *s) log_errx("Invalid UUID: %s", s); n = sscanf(s, - "%8x-%4hx-%4hx-%2hhx%2hhx-%2hhx%2hhx%2hhx%2hhx%2hhx%2hhx", - &u->time_low, &u->time_mid, &u->time_hi_and_version, - &u->clock_seq_hi_and_reserved, &u->clock_seq_low, &u->node[0], - &u->node[1], &u->node[2], &u->node[3], &u->node[4], &u->node[5]); + "%2hhx%2hhx%2hhx%2hhx-%2hhx%2hhx-%2hhx%2hhx-%2hhx%2hhx-%2hhx%2hhx%2hhx%2hhx%2hhx%2hhx", + &u->time_low[0], &u->time_low[1], &u->time_low[2], &u->time_low[3], + &u->time_mid[0], &u->time_mid[1], + &u->time_hi_and_version[0], &u->time_hi_and_version[1], + &u->clock_seq_hi_and_reserved, &u->clock_seq_low, + &u->node[0], &u->node[1], + &u->node[2], &u->node[3], + &u->node[4], &u->node[5]); /* * Given the format specifier above, we expect 11 items to be scanned * for a properly formatted UUID. @@ -697,7 +702,7 @@ static int create_cmd(int argc, char *argv[]) case 'b': { char name[_UUID_STR_LEN + 1]; char filename[PATH_MAX] = { 0 }; - uuid_t uuid = { 0 }; + uuid_t uuid = uuid_null; image_desc_t *desc; parse_blob_opt(optarg, &uuid, @@ -794,7 +799,7 @@ static int update_cmd(int argc, char *argv[]) case 'b': { char name[_UUID_STR_LEN + 1]; char filename[PATH_MAX] = { 0 }; - uuid_t uuid = { 0 }; + uuid_t uuid = uuid_null; image_desc_t *desc; parse_blob_opt(optarg, &uuid, @@ -902,7 +907,7 @@ static int unpack_cmd(int argc, char *argv[]) case 'b': { char name[_UUID_STR_LEN + 1]; char filename[PATH_MAX] = { 0 }; - uuid_t uuid = { 0 }; + uuid_t uuid = uuid_null; image_desc_t *desc; parse_blob_opt(optarg, &uuid, @@ -1041,7 +1046,7 @@ static int remove_cmd(int argc, char *argv[]) break; case 'b': { char name[_UUID_STR_LEN + 1], filename[PATH_MAX]; - uuid_t uuid = { 0 }; + uuid_t uuid = uuid_null; image_desc_t *desc; parse_blob_opt(optarg, &uuid, diff --git a/tools/fiptool/tbbr_config.c b/tools/fiptool/tbbr_config.c index c7df243a..86b8581f 100644 --- a/tools/fiptool/tbbr_config.c +++ b/tools/fiptool/tbbr_config.c @@ -153,7 +153,7 @@ toc_entry_t toc_entries[] = { }, { .name = NULL, - .uuid = { 0 }, + .uuid = { {0} }, .cmdline_name = NULL, } }; |