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-rw-r--r--Makefile4
-rw-r--r--bl31/aarch64/runtime_exceptions.S23
-rw-r--r--bl32/tsp/aarch64/tsp_entrypoint.S5
-rw-r--r--bl32/tsp/aarch64/tsp_exceptions.S28
-rw-r--r--common/aarch32/debug.S2
-rw-r--r--common/aarch64/debug.S4
-rw-r--r--docs/firmware-design.rst2
-rw-r--r--include/common/asm_macros_common.S12
-rw-r--r--lib/psci/psci_common.c7
-rw-r--r--plat/hisilicon/hikey/hisi_pwrc_sram.S3
-rw-r--r--plat/nvidia/tegra/common/aarch64/tegra_helpers.S3
-rw-r--r--plat/nvidia/tegra/soc/t186/plat_trampoline.S3
-rw-r--r--plat/qemu/include/platform_def.h8
-rw-r--r--plat/qemu/platform.mk16
-rw-r--r--plat/qemu/qemu_bl2_mem_params_desc.c37
-rw-r--r--plat/qemu/qemu_bl2_setup.c27
-rw-r--r--plat/qemu/qemu_io_storage.c28
-rw-r--r--plat/rockchip/common/aarch64/plat_helpers.S3
-rw-r--r--services/spd/opteed/opteed_common.c3
-rw-r--r--services/spd/opteed/opteed_main.c7
-rw-r--r--services/spd/opteed/opteed_pm.c2
-rw-r--r--services/spd/opteed/opteed_private.h1
22 files changed, 174 insertions, 54 deletions
diff --git a/Makefile b/Makefile
index b57b2129..0a645146 100644
--- a/Makefile
+++ b/Makefile
@@ -571,10 +571,10 @@ endif
locate-checkpatch:
ifndef CHECKPATCH
- $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl")
+ $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/scripts/checkpatch.pl")
else
ifeq (,$(wildcard ${CHECKPATCH}))
- $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl")
+ $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/scripts/checkpatch.pl")
endif
endif
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 45b0213d..d8fbb9b2 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -49,7 +49,8 @@
b.eq smc_handler64
/* Other kinds of synchronous exceptions are not handled */
- no_ret report_unhandled_exception
+ ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
+ b report_unhandled_exception
.endm
@@ -152,7 +153,7 @@ vector_base runtime_exceptions
*/
vector_entry sync_exception_sp_el0
/* We don't expect any synchronous exceptions from EL3 */
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size sync_exception_sp_el0
vector_entry irq_sp_el0
@@ -160,17 +161,17 @@ vector_entry irq_sp_el0
* EL3 code is non-reentrant. Any asynchronous exception is a serious
* error. Loop infinitely.
*/
- no_ret report_unhandled_interrupt
+ b report_unhandled_interrupt
check_vector_size irq_sp_el0
vector_entry fiq_sp_el0
- no_ret report_unhandled_interrupt
+ b report_unhandled_interrupt
check_vector_size fiq_sp_el0
vector_entry serror_sp_el0
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size serror_sp_el0
/* ---------------------------------------------------------------------
@@ -184,19 +185,19 @@ vector_entry sync_exception_sp_elx
* synchronous exception. There is a high probability that SP_EL3 is
* corrupted.
*/
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size sync_exception_sp_elx
vector_entry irq_sp_elx
- no_ret report_unhandled_interrupt
+ b report_unhandled_interrupt
check_vector_size irq_sp_elx
vector_entry fiq_sp_elx
- no_ret report_unhandled_interrupt
+ b report_unhandled_interrupt
check_vector_size fiq_sp_elx
vector_entry serror_sp_elx
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size serror_sp_elx
/* ---------------------------------------------------------------------
@@ -226,7 +227,7 @@ vector_entry serror_aarch64
* SError exceptions from lower ELs are not currently supported.
* Report their occurrence.
*/
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size serror_aarch64
/* ---------------------------------------------------------------------
@@ -256,7 +257,7 @@ vector_entry serror_aarch32
* SError exceptions from lower ELs are not currently supported.
* Report their occurrence.
*/
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size serror_aarch32
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index 2c325785..489183c5 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -43,10 +43,7 @@
msr spsr_el1, \reg2
.endm
- .section .text, "ax"
- .align 3
-
-func tsp_entrypoint
+func tsp_entrypoint _align=3
/* ---------------------------------------------
* Set the exception vector to something sane.
diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S
index 96d958eb..4b2ad75e 100644
--- a/bl32/tsp/aarch64/tsp_exceptions.S
+++ b/bl32/tsp/aarch64/tsp_exceptions.S
@@ -81,19 +81,19 @@ vector_base tsp_exceptions
* -----------------------------------------------------
*/
vector_entry sync_exception_sp_el0
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size sync_exception_sp_el0
vector_entry irq_sp_el0
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size irq_sp_el0
vector_entry fiq_sp_el0
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size fiq_sp_el0
vector_entry serror_sp_el0
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size serror_sp_el0
@@ -103,7 +103,7 @@ vector_entry serror_sp_el0
* -----------------------------------------------------
*/
vector_entry sync_exception_sp_elx
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size sync_exception_sp_elx
vector_entry irq_sp_elx
@@ -115,7 +115,7 @@ vector_entry fiq_sp_elx
check_vector_size fiq_sp_elx
vector_entry serror_sp_elx
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size serror_sp_elx
@@ -125,19 +125,19 @@ vector_entry serror_sp_elx
* -----------------------------------------------------
*/
vector_entry sync_exception_aarch64
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size sync_exception_aarch64
vector_entry irq_aarch64
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size irq_aarch64
vector_entry fiq_aarch64
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size fiq_aarch64
vector_entry serror_aarch64
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size serror_aarch64
@@ -147,17 +147,17 @@ vector_entry serror_aarch64
* -----------------------------------------------------
*/
vector_entry sync_exception_aarch32
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size sync_exception_aarch32
vector_entry irq_aarch32
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size irq_aarch32
vector_entry fiq_aarch32
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size fiq_aarch32
vector_entry serror_aarch32
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size serror_aarch32
diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S
index 2e60bd52..583ee4a5 100644
--- a/common/aarch32/debug.S
+++ b/common/aarch32/debug.S
@@ -51,7 +51,7 @@ func do_panic
1:
mov lr, r6
- no_ret plat_panic_handler
+ b plat_panic_handler
endfunc do_panic
/***********************************************************
diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S
index fe6a9a2d..d794d12e 100644
--- a/common/aarch64/debug.S
+++ b/common/aarch64/debug.S
@@ -175,6 +175,6 @@ el3_panic:
_panic_handler:
/* Pass to plat_panic_handler the address from where el3_panic was
* called, not the address of the call from el3_panic. */
- mov x30,x6
- no_ret plat_panic_handler
+ mov x30, x6
+ b plat_panic_handler
endfunc do_panic
diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst
index 4c3c4204..3bca7643 100644
--- a/docs/firmware-design.rst
+++ b/docs/firmware-design.rst
@@ -1864,7 +1864,7 @@ A ToC entry has the following fields:
`offset_address`: The offset address at which the corresponding payload data
can be found. The offset is calculated from the ToC base address.
`size`: The size of the corresponding payload data in bytes.
- `flags`: Flags associated with this entry. Non are yet defined.
+ `flags`: Flags associated with this entry. None are yet defined.
Firmware Image Package creation tool
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/include/common/asm_macros_common.S b/include/common/asm_macros_common.S
index b529246d..dbc9e2d3 100644
--- a/include/common/asm_macros_common.S
+++ b/include/common/asm_macros_common.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,9 +11,12 @@
* code into a separate text section based on the function name
* to enable elimination of unused code during linking. It also adds
* basic debug information to enable call stack printing most of the
- * time.
+ * time. The optional _align parameter can be used to force a
+ * non-standard alignment (indicated in powers of 2). Do *not* try to
+ * use a raw .align directive. Since func switches to a new section,
+ * this would not have the desired effect.
*/
- .macro func _name
+ .macro func _name, _align=-1
/*
* Add Call Frame Information entry in the .debug_frame section for
* debugger consumption. This enables callstack printing in debuggers.
@@ -33,6 +36,9 @@
* .debug_frame
*/
.cfi_startproc
+ .if (\_align) != -1
+ .align \_align
+ .endif
\_name:
.endm
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index f31b3238..4502c24b 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -194,8 +194,15 @@ static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
unsigned int cpu_idx,
plat_local_state_t req_pwr_state)
{
+ /*
+ * This should never happen, we have this here to avoid
+ * "array subscript is above array bounds" errors in GCC.
+ */
assert(pwrlvl > PSCI_CPU_PWR_LVL);
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
+#pragma GCC diagnostic pop
}
/******************************************************************************
diff --git a/plat/hisilicon/hikey/hisi_pwrc_sram.S b/plat/hisilicon/hikey/hisi_pwrc_sram.S
index 1fb63eaf..f9e1de41 100644
--- a/plat/hisilicon/hikey/hisi_pwrc_sram.S
+++ b/plat/hisilicon/hikey/hisi_pwrc_sram.S
@@ -15,8 +15,7 @@
.global v7_asm
.global v7_asm_end
- .align 3
-func pm_asm_code
+func pm_asm_code _align=3
mov x0, 0
msr oslar_el1, x0
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index e5e51268..691b90af 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -307,8 +307,7 @@ endfunc plat_reset_handler
* Secure entrypoint function for CPU boot
* ----------------------------------------
*/
- .align 6
-func tegra_secure_entrypoint
+func tegra_secure_entrypoint _align=6
#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT
diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index 4841aa20..6a17c332 100644
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -12,11 +12,10 @@
#define TEGRA186_SMMU_CTX_SIZE 0x420
- .align 4
.globl tegra186_cpu_reset_handler
/* CPU reset handler routine */
-func tegra186_cpu_reset_handler
+func tegra186_cpu_reset_handler _align=4
/*
* The TZRAM loses state during System Suspend. We use this
* information to decide if the reset handler is running after a
diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h
index ceb0539b..e91a7db9 100644
--- a/plat/qemu/include/platform_def.h
+++ b/plat/qemu/include/platform_def.h
@@ -73,6 +73,11 @@
#define SEC_DRAM_BASE 0x0e100000
#define SEC_DRAM_SIZE 0x00f00000
+/* Load pageable part of OP-TEE at end of secure DRAM */
+#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
+ QEMU_OPTEE_PAGEABLE_LOAD_SIZE)
+#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000
+
/*
* ARM-TF lives in SRAM, partition it here
*/
@@ -154,7 +159,8 @@
#define NS_IMAGE_OFFSET 0x60000000
-#define ADDR_SPACE_SIZE (1ull << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
#define MAX_MMAP_REGIONS 8
#define MAX_XLAT_TABLES 6
#define MAX_IO_DEVICES 3
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index dc3b5d93..ed197a1d 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -65,6 +65,10 @@ BL2_SOURCES += plat/qemu/qemu_bl2_mem_params_desc.c \
plat/qemu/qemu_image_load.c \
common/desc_image_load.c
endif
+ifeq (${SPD},opteed)
+BL2_SOURCES += lib/optee/optee_utils.c
+endif
+
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
@@ -72,13 +76,23 @@ BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/common/gic_common.c \
- plat/common/aarch64/plat_psci_common.c \
+ plat/common/plat_psci_common.c \
plat/qemu/qemu_pm.c \
plat/qemu/topology.c \
plat/qemu/aarch64/plat_helpers.S \
plat/qemu/qemu_bl31_setup.c \
plat/qemu/qemu_gic.c
+
+# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
+# in the FIP if the platform requires.
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call FIP_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call FIP_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
+endif
+
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
diff --git a/plat/qemu/qemu_bl2_mem_params_desc.c b/plat/qemu/qemu_bl2_mem_params_desc.c
index 3396140a..47f88acb 100644
--- a/plat/qemu/qemu_bl2_mem_params_desc.c
+++ b/plat/qemu/qemu_bl2_mem_params_desc.c
@@ -72,6 +72,43 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
.next_handoff_image_id = BL33_IMAGE_ID,
},
+
+ /*
+ * Fill BL32 external 1 related information.
+ * A typical use for extra1 image is with OP-TEE where it is the
+ * pager image.
+ */
+ { .image_id = BL32_EXTRA1_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t, SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+ .image_info.image_base = BL32_BASE,
+ .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+ /*
+ * Fill BL32 external 2 related information.
+ * A typical use for extra2 image is with OP-TEE where it is the
+ * paged image.
+ */
+ { .image_id = BL32_EXTRA2_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t, SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+#ifdef SPD_opteed
+ .image_info.image_base = QEMU_OPTEE_PAGEABLE_LOAD_BASE,
+ .image_info.image_max_size = QEMU_OPTEE_PAGEABLE_LOAD_SIZE,
+#endif
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
# endif /* QEMU_LOAD_BL32 */
/* Fill BL33 related information */
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index 1306f34b..60d96233 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -9,6 +9,9 @@
#include <console.h>
#include <debug.h>
#include <desc_image_load.h>
+#ifdef SPD_opteed
+#include <optee_utils.h>
+#endif
#include <libfdt.h>
#include <platform_def.h>
#include <string.h>
@@ -225,12 +228,36 @@ static int qemu_bl2_handle_post_image_load(unsigned int image_id)
{
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+#ifdef SPD_opteed
+ bl_mem_params_node_t *pager_mem_params = NULL;
+ bl_mem_params_node_t *paged_mem_params = NULL;
+#endif
assert(bl_mem_params);
switch (image_id) {
# ifdef AARCH64
case BL32_IMAGE_ID:
+#ifdef SPD_opteed
+ pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ assert(pager_mem_params);
+
+ paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+ assert(paged_mem_params);
+
+ err = parse_optee_header(&bl_mem_params->ep_info,
+ &pager_mem_params->image_info,
+ &paged_mem_params->image_info);
+ if (err != 0) {
+ WARN("OPTEE header parse error.\n");
+ }
+
+ /*
+ * OP-TEE expect to receive DTB address in x2.
+ * This will be copied into x2 by dispatcher.
+ */
+ bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
+#endif
bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
break;
# endif
diff --git a/plat/qemu/qemu_io_storage.c b/plat/qemu/qemu_io_storage.c
index 19baf21d..e0f7e8ab 100644
--- a/plat/qemu/qemu_io_storage.c
+++ b/plat/qemu/qemu_io_storage.c
@@ -21,6 +21,8 @@
#define BL2_IMAGE_NAME "bl2.bin"
#define BL31_IMAGE_NAME "bl31.bin"
#define BL32_IMAGE_NAME "bl32.bin"
+#define BL32_EXTRA1_IMAGE_NAME "bl32_extra1.bin"
+#define BL32_EXTRA2_IMAGE_NAME "bl32_extra2.bin"
#define BL33_IMAGE_NAME "bl33.bin"
#if TRUSTED_BOARD_BOOT
@@ -61,6 +63,14 @@ static const io_uuid_spec_t bl32_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32,
};
+static const io_uuid_spec_t bl32_extra1_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
+};
+
+static const io_uuid_spec_t bl32_extra2_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
+};
+
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
@@ -112,6 +122,14 @@ static const io_file_spec_t sh_file_spec[] = {
.path = BL32_IMAGE_NAME,
.mode = FOPEN_MODE_RB
},
+ [BL32_EXTRA1_IMAGE_ID] = {
+ .path = BL32_EXTRA1_IMAGE_NAME,
+ .mode = FOPEN_MODE_RB
+ },
+ [BL32_EXTRA2_IMAGE_ID] = {
+ .path = BL32_EXTRA2_IMAGE_NAME,
+ .mode = FOPEN_MODE_RB
+ },
[BL33_IMAGE_ID] = {
.path = BL33_IMAGE_NAME,
.mode = FOPEN_MODE_RB
@@ -185,6 +203,16 @@ static const struct plat_io_policy policies[] = {
(uintptr_t)&bl32_uuid_spec,
open_fip
},
+ [BL32_EXTRA1_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_extra1_uuid_spec,
+ open_fip
+ },
+ [BL32_EXTRA2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_extra2_uuid_spec,
+ open_fip
+ },
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl33_uuid_spec,
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index 1c8aefcb..abfb5a79 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -112,8 +112,7 @@ endfunc plat_crash_console_putc
* cpus online or resume enterpoint
* --------------------------------------------------------------------
*/
- .align 16
-func platform_cpu_warmboot
+func platform_cpu_warmboot _align=16
mrs x0, MPIDR_EL1
and x19, x0, #MPIDR_CPU_MASK
and x20, x0, #MPIDR_CLUSTER_MASK
diff --git a/services/spd/opteed/opteed_common.c b/services/spd/opteed/opteed_common.c
index a0cd86cb..2693e7d1 100644
--- a/services/spd/opteed/opteed_common.c
+++ b/services/spd/opteed/opteed_common.c
@@ -20,7 +20,7 @@
void opteed_init_optee_ep_state(struct entry_point_info *optee_entry_point,
uint32_t rw, uint64_t pc,
uint64_t pageable_part, uint64_t mem_limit,
- optee_context_t *optee_ctx)
+ uint64_t dt_addr, optee_context_t *optee_ctx)
{
uint32_t ep_attr;
@@ -54,6 +54,7 @@ void opteed_init_optee_ep_state(struct entry_point_info *optee_entry_point,
zeromem(&optee_entry_point->args, sizeof(optee_entry_point->args));
optee_entry_point->args.arg0 = pageable_part;
optee_entry_point->args.arg1 = mem_limit;
+ optee_entry_point->args.arg2 = dt_addr;
}
/*******************************************************************************
diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c
index b3031e40..13a307a2 100644
--- a/services/spd/opteed/opteed_main.c
+++ b/services/spd/opteed/opteed_main.c
@@ -96,6 +96,7 @@ int32_t opteed_setup(void)
uint32_t linear_id;
uint64_t opteed_pageable_part;
uint64_t opteed_mem_limit;
+ uint64_t dt_addr;
linear_id = plat_my_core_pos();
@@ -120,19 +121,17 @@ int32_t opteed_setup(void)
if (!optee_ep_info->pc)
return 1;
- /*
- * We could inspect the SP image and determine it's execution
- * state i.e whether AArch32 or AArch64.
- */
opteed_rw = optee_ep_info->args.arg0;
opteed_pageable_part = optee_ep_info->args.arg1;
opteed_mem_limit = optee_ep_info->args.arg2;
+ dt_addr = optee_ep_info->args.arg3;
opteed_init_optee_ep_state(optee_ep_info,
opteed_rw,
optee_ep_info->pc,
opteed_pageable_part,
opteed_mem_limit,
+ dt_addr,
&opteed_sp_context[linear_id]);
/*
diff --git a/services/spd/opteed/opteed_pm.c b/services/spd/opteed/opteed_pm.c
index 5a1dd4fd..2420b1e8 100644
--- a/services/spd/opteed/opteed_pm.c
+++ b/services/spd/opteed/opteed_pm.c
@@ -99,7 +99,7 @@ static void opteed_cpu_on_finish_handler(uint64_t unused)
opteed_init_optee_ep_state(&optee_on_entrypoint, opteed_rw,
(uint64_t)&optee_vectors->cpu_on_entry,
- 0, 0, optee_ctx);
+ 0, 0, 0, optee_ctx);
/* Initialise this cpu's secure context */
cm_init_my_context(&optee_on_entrypoint);
diff --git a/services/spd/opteed/opteed_private.h b/services/spd/opteed/opteed_private.h
index 11c1a1fa..6cda2c8e 100644
--- a/services/spd/opteed/opteed_private.h
+++ b/services/spd/opteed/opteed_private.h
@@ -149,6 +149,7 @@ void opteed_init_optee_ep_state(struct entry_point_info *optee_ep,
uint64_t pc,
uint64_t pageable_part,
uint64_t mem_limit,
+ uint64_t dt_addr,
optee_context_t *optee_ctx);
extern optee_context_t opteed_sp_context[OPTEED_CORE_COUNT];
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-18 03:31:03 +0000