diff options
55 files changed, 269 insertions, 224 deletions
@@ -74,11 +74,19 @@ CHECK_PATHS := ${ROOT_DIRS_TO_CHECK} \ # Verbose flag ifeq (${V},0) Q:=@ + ECHO:=@echo CHECKCODE_ARGS += --no-summary --terse else Q:= + ECHO:=@\# endif -export Q + +ifneq ($(findstring s,$(filter-out --%,$(MAKEFLAGS))),) + Q:=@ + ECHO:=@\# +endif + +export Q ECHO # Process Debug flag $(eval $(call add_define,DEBUG)) diff --git a/docs/change-log.rst b/docs/change-log.rst index 95361e95..d329e836 100644 --- a/docs/change-log.rst +++ b/docs/change-log.rst @@ -61,11 +61,11 @@ New Features - Introduce RAS handling on AArch64 - - Some RAS extensions are mandatory for ARMv8.2 CPUs, with others - mandatory for ARMv8.4 CPUs however, all extensions are also optional - extensions to the base ARMv8.0 architecture. + - Some RAS extensions are mandatory for Armv8.2 CPUs, with others + mandatory for Armv8.4 CPUs however, all extensions are also optional + extensions to the base Armv8.0 architecture. - - The ARMv8 RAS Extensions introduced Standard Error Records which are a + - The Armv8 RAS Extensions introduced Standard Error Records which are a set of standard registers to configure RAS node policy and allow RAS Nodes to record and expose error information for error handling agents. @@ -126,7 +126,7 @@ New Features - Various changes to support Clang linker and assembler - - The clang assembler/preprocessor is used when Clang is selected however, + - The clang assembler/preprocessor is used when Clang is selected. However, the clang linker is not used because it is unable to link TF-A objects due to immaturity of clang linker functionality at this time. @@ -213,12 +213,14 @@ New Features - Allwinner sun50i_h6 - - NXP ls1043 + - NXP QorIQ LS1043A - NXP i.MX8QX - NXP i.MX8QM + - NXP i.MX7Solo WaRP7 + - TI K3 - Socionext Synquacer SC2A11 diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 2632329a..f4ef85d2 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -521,8 +521,8 @@ Common build options 40 (LOG_LEVEL_INFO) 50 (LOG_LEVEL_VERBOSE) - All log output up to and including the log level is compiled into the build. - The default value is 40 in debug builds and 20 in release builds. + All log output up to and including the selected log level is compiled into + the build. The default value is 40 in debug builds and 20 in release builds. - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the Non-Trusted World private key in PEM diff --git a/plat/arm/board/common/drivers/norflash/norflash.c b/drivers/cfi/v2m/v2m_flash.c index 722cf33e..9b80e2f2 100644 --- a/plat/arm/board/common/drivers/norflash/norflash.c +++ b/drivers/cfi/v2m/v2m_flash.c @@ -6,8 +6,15 @@ #include <errno.h> #include <mmio.h> -#include <norflash.h> +#include <v2m_flash.h> +/* + * This file supplies a low level interface to the vexpress NOR flash + * memory of juno and fvp. This memory is organized as an interleaved + * memory of two chips with a 16 bit word. It means that every 32 bit + * access is going to access to two different chips. This is very + * important when we send commands or read status of the chips. + */ /* * DWS ready poll retries. The number of retries in this driver have been @@ -21,14 +28,6 @@ /* Helper macro to detect end of command */ #define NOR_CMD_END (NOR_DWS | NOR_DWS << 16l) -/* - * This file supplies a low level interface to the vexpress NOR flash - * memory of juno and fvp. This memory is organized as an interleaved - * memory of two chips with a 16 bit word. It means that every 32 bit - * access is going to access to two different chips. This is very - * important when we send commands or read status of the chips - */ - /* Helper macros to access two flash banks in parallel */ #define NOR_2X16(d) ((d << 16) | (d & 0xffff)) diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c index ea96833f..1f9550e1 100644 --- a/drivers/imx/usdhc/imx_usdhc.c +++ b/drivers/imx/usdhc/imx_usdhc.c @@ -160,7 +160,7 @@ static int imx_usdhc_send_cmd(struct mmc_cmd *cmd) mixctl |= MIXCTRL_DMAEN; } - if (cmd->resp_type & MMC_RSP_48) + if (cmd->resp_type & MMC_RSP_48 && cmd->resp_type != MMC_RESPONSE_R2) xfertype |= XFERTYPE_RSPTYP_48; else if (cmd->resp_type & MMC_RSP_136) xfertype |= XFERTYPE_RSPTYP_136; diff --git a/include/common/debug.h b/include/common/debug.h index 8ee55b88..a14a66e8 100644 --- a/include/common/debug.h +++ b/include/common/debug.h @@ -57,18 +57,18 @@ } \ } while (false) -#if LOG_LEVEL >= LOG_LEVEL_NOTICE -# define NOTICE(...) tf_log(LOG_MARKER_NOTICE __VA_ARGS__) -#else -# define NOTICE(...) no_tf_log(LOG_MARKER_NOTICE __VA_ARGS__) -#endif - #if LOG_LEVEL >= LOG_LEVEL_ERROR # define ERROR(...) tf_log(LOG_MARKER_ERROR __VA_ARGS__) #else # define ERROR(...) no_tf_log(LOG_MARKER_ERROR __VA_ARGS__) #endif +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +# define NOTICE(...) tf_log(LOG_MARKER_NOTICE __VA_ARGS__) +#else +# define NOTICE(...) no_tf_log(LOG_MARKER_NOTICE __VA_ARGS__) +#endif + #if LOG_LEVEL >= LOG_LEVEL_WARNING # define WARN(...) tf_log(LOG_MARKER_WARNING __VA_ARGS__) #else diff --git a/include/common/interrupt_props.h b/include/common/interrupt_props.h index 9786b40c..4ac698df 100644 --- a/include/common/interrupt_props.h +++ b/include/common/interrupt_props.h @@ -12,10 +12,10 @@ /* Create an interrupt property descriptor from various interrupt properties */ #define INTR_PROP_DESC(num, pri, grp, cfg) \ { \ - .intr_num = num, \ - .intr_pri = pri, \ - .intr_grp = grp, \ - .intr_cfg = cfg, \ + .intr_num = (num), \ + .intr_pri = (pri), \ + .intr_grp = (grp), \ + .intr_cfg = (cfg), \ } typedef struct interrupt_prop { diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h index 6fe0a941..e32c2870 100644 --- a/include/common/runtime_svc.h +++ b/include/common/runtime_svc.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __RUNTIME_SVC_H__ -#define __RUNTIME_SVC_H__ +#ifndef RUNTIME_SVC_H +#define RUNTIME_SVC_H #include <bl_common.h> /* to include exception types */ #include <cassert.h> @@ -88,12 +88,12 @@ typedef struct rt_svc_desc { #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ static const rt_svc_desc_t __svc_desc_ ## _name \ __section("rt_svc_descs") __used = { \ - .start_oen = _start, \ - .end_oen = _end, \ - .call_type = _type, \ + .start_oen = (_start), \ + .end_oen = (_end), \ + .call_type = (_type), \ .name = #_name, \ - .init = _setup, \ - .handle = _smch \ + .init = (_setup), \ + .handle = (_smch) \ } #elif SMCCC_MAJOR_VERSION == 2 @@ -101,12 +101,12 @@ typedef struct rt_svc_desc { #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ static const rt_svc_desc_t __svc_desc_ ## _name \ __section("rt_svc_descs") __used = { \ - .start_oen = _start, \ - .end_oen = _end, \ + .start_oen = (_start), \ + .end_oen = (_end), \ .is_vendor = 0, \ .name = #_name, \ - .init = _setup, \ - .handle = _smch, \ + .init = (_setup), \ + .handle = (_smch), \ }; \ CASSERT((_type) == SMC_TYPE_FAST, rt_svc_type_check_ ## _name) @@ -198,4 +198,4 @@ void init_crash_reporting(void); extern uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; #endif /*__ASSEMBLY__*/ -#endif /* __RUNTIME_SVC_H__ */ +#endif /* RUNTIME_SVC_H */ diff --git a/include/drivers/arm/tzc_common.h b/include/drivers/arm/tzc_common.h index 9411b731..bb64b008 100644 --- a/include/drivers/arm/tzc_common.h +++ b/include/drivers/arm/tzc_common.h @@ -46,10 +46,10 @@ /* Macros for allowing Non-Secure access to a region based on NSAID */ #define TZC_REGION_ACCESS_RD(nsaid) \ - ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \ + ((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \ TZC_REGION_ACCESS_RD_EN_SHIFT) #define TZC_REGION_ACCESS_WR(nsaid) \ - ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \ + ((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \ TZC_REGION_ACCESS_WR_EN_SHIFT) #define TZC_REGION_ACCESS_RDWR(nsaid) \ (TZC_REGION_ACCESS_RD(nsaid) | \ diff --git a/include/plat/arm/board/common/drivers/norflash.h b/include/drivers/cfi/v2m_flash.h index 5763b36d..5763b36d 100644 --- a/include/plat/arm/board/common/drivers/norflash.h +++ b/include/drivers/cfi/v2m_flash.h diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h index ce436d2c..02c34941 100644 --- a/include/plat/arm/board/common/v2m_def.h +++ b/include/plat/arm/board/common/v2m_def.h @@ -1,36 +1,36 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __V2M_DEF_H__ -#define __V2M_DEF_H__ +#ifndef V2M_DEF_H +#define V2M_DEF_H #include <arm_xlat_tables.h> /* V2M motherboard system registers & offsets */ -#define V2M_SYSREGS_BASE 0x1c010000 -#define V2M_SYS_ID 0x0 -#define V2M_SYS_SWITCH 0x4 -#define V2M_SYS_LED 0x8 -#define V2M_SYS_NVFLAGS 0x38 -#define V2M_SYS_NVFLAGSSET 0x38 -#define V2M_SYS_NVFLAGSCLR 0x3c -#define V2M_SYS_CFGDATA 0xa0 -#define V2M_SYS_CFGCTRL 0xa4 -#define V2M_SYS_CFGSTATUS 0xa8 - -#define V2M_CFGCTRL_START (1 << 31) -#define V2M_CFGCTRL_RW (1 << 30) +#define V2M_SYSREGS_BASE UL(0x1c010000) +#define V2M_SYS_ID UL(0x0) +#define V2M_SYS_SWITCH UL(0x4) +#define V2M_SYS_LED UL(0x8) +#define V2M_SYS_NVFLAGS UL(0x38) +#define V2M_SYS_NVFLAGSSET UL(0x38) +#define V2M_SYS_NVFLAGSCLR UL(0x3c) +#define V2M_SYS_CFGDATA UL(0xa0) +#define V2M_SYS_CFGCTRL UL(0xa4) +#define V2M_SYS_CFGSTATUS UL(0xa8) + +#define V2M_CFGCTRL_START BIT_32(31) +#define V2M_CFGCTRL_RW BIT_32(30) #define V2M_CFGCTRL_FUNC_SHIFT 20 -#define V2M_CFGCTRL_FUNC(fn) (fn << V2M_CFGCTRL_FUNC_SHIFT) -#define V2M_FUNC_CLK_GEN 0x01 -#define V2M_FUNC_TEMP 0x04 -#define V2M_FUNC_DB_RESET 0x05 -#define V2M_FUNC_SCC_CFG 0x06 -#define V2M_FUNC_SHUTDOWN 0x08 -#define V2M_FUNC_REBOOT 0x09 +#define V2M_CFGCTRL_FUNC(fn) ((fn) << V2M_CFGCTRL_FUNC_SHIFT) +#define V2M_FUNC_CLK_GEN U(0x01) +#define V2M_FUNC_TEMP U(0x04) +#define V2M_FUNC_DB_RESET U(0x05) +#define V2M_FUNC_SCC_CFG U(0x06) +#define V2M_FUNC_SHUTDOWN U(0x08) +#define V2M_FUNC_REBOOT U(0x09) /* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */ #define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS) @@ -131,4 +131,4 @@ MT_DEVICE | MT_RW | MT_SECURE | MT_USER) -#endif /* __V2M_DEF_H__ */ +#endif /* V2M_DEF_H */ diff --git a/include/plat/marvell/a8k/common/plat_marvell.h b/include/plat/marvell/a8k/common/plat_marvell.h index a62a7cb0..2aecd3f5 100644 --- a/include/plat/marvell/a8k/common/plat_marvell.h +++ b/include/plat/marvell/a8k/common/plat_marvell.h @@ -125,4 +125,6 @@ void marvell_ble_prepare_exit(void); void marvell_exit_bootrom(uintptr_t base); int plat_marvell_early_cpu_powerdown(void); +int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info); + #endif /* __PLAT_MARVELL_H__ */ diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index adce843a..97aeb832 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -267,7 +267,7 @@ static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, static plat_local_state_t get_non_cpu_pd_node_local_state( unsigned int parent_idx) { -#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY) +#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) flush_dcache_range( (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], sizeof(psci_non_cpu_pd_nodes[parent_idx])); @@ -283,7 +283,7 @@ static void set_non_cpu_pd_node_local_state(unsigned int parent_idx, plat_local_state_t state) { psci_non_cpu_pd_nodes[parent_idx].local_state = state; -#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY) +#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) flush_dcache_range( (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], sizeof(psci_non_cpu_pd_nodes[parent_idx])); @@ -948,21 +948,18 @@ void psci_do_pwrdown_sequence(unsigned int power_level) /* * With hardware-assisted coherency, the CPU drivers only initiate the * power down sequence, without performing cache-maintenance operations - * in software. Data caches and MMU remain enabled both before and after - * this call. + * in software. Data caches enabled both before and after this call. */ prepare_cpu_pwr_dwn(power_level); #else /* * Without hardware-assisted coherency, the CPU drivers disable data - * caches and MMU, then perform cache-maintenance operations in - * software. + * caches, then perform cache-maintenance operations in software. * - * We ought to call prepare_cpu_pwr_dwn() to initiate power down - * sequence. We currently have data caches and MMU enabled, but the - * function will return with data caches and MMU disabled. We must - * ensure that the stack memory is flushed out to memory before we start - * popping from it again. + * This also calls prepare_cpu_pwr_dwn() to initiate power down + * sequence, but that function will return with data caches disabled. + * We must ensure that the stack memory is flushed out to memory before + * we start popping from it again. */ psci_do_pwrdown_cache_maintenance(power_level); #endif diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index fd822bcf..b4a25fb0 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c @@ -167,8 +167,14 @@ int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) /* Query the psci_power_state for system suspend */ psci_query_sys_suspend_pwrstate(&state_info); + /* + * Check if platform allows suspend to Highest power level + * (System level) + */ + if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) + return PSCI_E_DENIED; + /* Ensure that the psci_power_state makes sense */ - assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL); assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) == PSCI_E_SUCCESS); assert(is_local_state_off( diff --git a/maintainers.rst b/maintainers.rst index 383e47b1..cb4f4204 100644 --- a/maintainers.rst +++ b/maintainers.rst @@ -81,6 +81,7 @@ Marvell platform ports and SoC drivers :F: docs/plat/marvell/ :F: plat/marvell/ :F: drivers/marvell/ +:F: tools/doimage/ NVidia platform ports --------------------- diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 28ce2a4b..e186fc10 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -177,7 +177,7 @@ endef # GZIP define GZIP_RULE $(1): $(2) - @echo " GZIP $$@" + $(ECHO) " GZIP $$@" $(Q)gzip -n -f -9 $$< --stdout > $$@ endef @@ -199,7 +199,7 @@ $(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) $(eval DEP := $(patsubst %.o,%.d,$(OBJ))) $(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | lib$(3)_dirs - @echo " CC $$<" + $$(ECHO) " CC $$<" $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) $(MAKE_DEP) -c $$< -o $$@ -include $(DEP) @@ -218,7 +218,7 @@ $(eval DEP := $(patsubst %.o,%.d,$(OBJ))) $(eval IMAGE := IMAGE_BL$(call uppercase,$(3))) $(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs - @echo " CC $$<" + $$(ECHO) " CC $$<" $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@ -include $(DEP) @@ -237,7 +237,7 @@ $(eval DEP := $(patsubst %.o,%.d,$(OBJ))) $(eval IMAGE := IMAGE_BL$(call uppercase,$(3))) $(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs - @echo " AS $$<" + $$(ECHO) " AS $$<" $$(Q)$$(AS) $$(ASFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@ -include $(DEP) @@ -255,7 +255,7 @@ $(eval DEP := $(1).d) $(eval IMAGE := IMAGE_BL$(call uppercase,$(3))) $(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs - @echo " PP $$<" + $$(ECHO) " PP $$<" $$(Q)$$(CPP) $$(CPPFLAGS) -P -D__ASSEMBLY__ -D__LINKER__ $(MAKE_DEP) -D$(IMAGE) -o $$@ $$< -include $(DEP) @@ -344,7 +344,7 @@ endif all: ${LIB_DIR}/lib$(1).a ${LIB_DIR}/lib$(1).a: $(OBJS) - @echo " AR $$@" + $$(ECHO) " AR $$@" $$(Q)$$(AR) cr $$@ $$? endef @@ -392,7 +392,7 @@ $(ELF): romlib.bin endif $(ELF): $(OBJS) $(LINKERFILE) | bl$(1)_dirs libraries $(BL_LIBS) - @echo " LD $$@" + $$(ECHO) " LD $$@" ifdef MAKE_BUILD_STRINGS $(call MAKE_BUILD_STRINGS, $(BUILD_DIR)/build_message.o) else @@ -405,11 +405,11 @@ endif $(OBJS) $(LDPATHS) $(LDLIBS) $(BL_LIBS) $(DUMP): $(ELF) - @echo " OD $$@" + $${ECHO} " OD $$@" $${Q}$${OD} -dx $$< > $$@ $(BIN): $(ELF) - @echo " BIN $$@" + $${ECHO} " BIN $$@" $$(Q)$$(OC) -O binary $$< $$@ @${ECHO_BLANK_LINE} @echo "Built $$@ successfully" @@ -461,10 +461,10 @@ $(eval DTSDEP := $(patsubst %.dtb,%.o.d,$(DOBJ))) $(eval DTBDEP := $(patsubst %.dtb,%.d,$(DOBJ))) $(DOBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | fdt_dirs - @echo " CPP $$<" + $${ECHO} " CPP $$<" $(eval DTBS := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2)))) $$(Q)$$(CPP) $$(CPPFLAGS) -x assembler-with-cpp -MT $(DTBS) -MMD -MF $(DTSDEP) -o $(DPRE) $$< - @echo " DTC $$<" + $${ECHO} " DTC $$<" $$(Q)$$(DTC) $$(DTC_FLAGS) -i fdts -d $(DTBDEP) -o $$@ $(DPRE) -include $(DTBDEP) diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk index 8b46c4be..2556fc04 100644 --- a/plat/arm/board/common/board_common.mk +++ b/plat/arm/board/common/board_common.mk @@ -4,15 +4,15 @@ # SPDX-License-Identifier: BSD-3-Clause # -PLAT_INCLUDES += -Iinclude/plat/arm/board/common/ \ - -Iinclude/plat/arm/board/common/drivers +PLAT_INCLUDES += -Iinclude/drivers/cfi/ \ + -Iinclude/plat/arm/board/common/ -PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/${ARCH}/pl011_console.S \ +PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/${ARCH}/pl011_console.S \ plat/arm/board/common/${ARCH}/board_arm_helpers.S -BL1_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c +BL1_SOURCES += drivers/cfi/v2m/v2m_flash.c -BL2_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c +BL2_SOURCES += drivers/cfi/v2m/v2m_flash.c ifneq (${TRUSTED_BOARD_BOOT},0) ifneq (${ARM_CRYPTOCELL_INTEG}, 1) diff --git a/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h index 9ad32d7e..324f3e25 100644 --- a/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h +++ b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h @@ -4,36 +4,36 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __FVP_PWRC_H__ -#define __FVP_PWRC_H__ +#ifndef FVP_PWRC_H +#define FVP_PWRC_H /* FVP Power controller register offset etc */ -#define PPOFFR_OFF 0x0 -#define PPONR_OFF 0x4 -#define PCOFFR_OFF 0x8 -#define PWKUPR_OFF 0xc -#define PSYSR_OFF 0x10 +#define PPOFFR_OFF U(0x0) +#define PPONR_OFF U(0x4) +#define PCOFFR_OFF U(0x8) +#define PWKUPR_OFF U(0xc) +#define PSYSR_OFF U(0x10) -#define PWKUPR_WEN (1ULL << 31) +#define PWKUPR_WEN BIT_32(31) -#define PSYSR_AFF_L2 (1 << 31) -#define PSYSR_AFF_L1 (1 << 30) -#define PSYSR_AFF_L0 (1 << 29) -#define PSYSR_WEN (1 << 28) -#define PSYSR_PC (1 << 27) -#define PSYSR_PP (1 << 26) +#define PSYSR_AFF_L2 BIT_32(31) +#define PSYSR_AFF_L1 BIT_32(30) +#define PSYSR_AFF_L0 BIT_32(29) +#define PSYSR_WEN BIT_32(28) +#define PSYSR_PC BIT_32(27) +#define PSYSR_PP BIT_32(26) #define PSYSR_WK_SHIFT 24 #define PSYSR_WK_WIDTH 0x2 -#define PSYSR_WK_MASK ((1 << PSYSR_WK_WIDTH) - 1) -#define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK +#define PSYSR_WK_MASK ((1U << PSYSR_WK_WIDTH) - 1U) +#define PSYSR_WK(x) ((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK -#define WKUP_COLD 0x0 -#define WKUP_RESET 0x1 -#define WKUP_PPONR 0x2 -#define WKUP_GICREQ 0x3 +#define WKUP_COLD U(0x0) +#define WKUP_RESET U(0x1) +#define WKUP_PPONR U(0x2) +#define WKUP_GICREQ U(0x3) -#define PSYSR_INVALID 0xffffffff +#define PSYSR_INVALID U(0xffffffff) #ifndef __ASSEMBLY__ @@ -50,4 +50,4 @@ unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr); #endif /*__ASSEMBLY__*/ -#endif /* __FVP_PWRC_H__ */ +#endif /* FVP_PWRC_H */ diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h index 4e20c310..eb6f77f3 100644 --- a/plat/arm/board/fvp/fvp_def.h +++ b/plat/arm/board/fvp/fvp_def.h @@ -97,7 +97,7 @@ #define ARCH_MODEL 0x1 /* FVP Power controller base address*/ -#define PWRC_BASE 0x1c100000 +#define PWRC_BASE UL(0x1c100000) /* FVP SP804 timer frequency is 35 MHz*/ #define SP804_TIMER_CLKMULT 1 diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index 065ecc11..7b85043b 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c @@ -153,7 +153,7 @@ static int fvp_pwr_domain_on(u_register_t mpidr) */ do { psysr = fvp_pwrc_read_psysr(mpidr); - } while (psysr & PSYSR_AFF_L0); + } while ((psysr & PSYSR_AFF_L0) != 0U); fvp_pwrc_write_pponr(mpidr); return rc; @@ -312,7 +312,7 @@ static int fvp_node_hw_state(u_register_t target_cpu, * The format of 'power_level' is implementation-defined, but 0 must * mean a CPU. We also allow 1 to denote the cluster */ - if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) + if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1)) return PSCI_E_INVALID_PARAMS; /* @@ -325,10 +325,10 @@ static int fvp_node_hw_state(u_register_t target_cpu, return PSCI_E_INVALID_PARAMS; if (power_level == ARM_PWR_LVL0) { - ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF; + ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF; } else { /* power_level == ARM_PWR_LVL1 */ - ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF; + ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF; } return ret; diff --git a/plat/arm/board/fvp/fvp_security.c b/plat/arm/board/fvp/fvp_security.c index a6c92278..028522cf 100644 --- a/plat/arm/board/fvp/fvp_security.c +++ b/plat/arm/board/fvp/fvp_security.c @@ -21,6 +21,6 @@ void plat_arm_security_setup(void) * configurations, those would be configured here. */ - if (get_arm_config()->flags & ARM_CONFIG_HAS_TZC) + if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U) arm_tzc400_setup(NULL); } diff --git a/plat/arm/board/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c index a1e3f7f4..e21b9d28 100644 --- a/plat/arm/board/fvp/fvp_topology.c +++ b/plat/arm/board/fvp/fvp_topology.c @@ -16,7 +16,8 @@ static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2]; -CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count); +CASSERT(((FVP_CLUSTER_COUNT > 0) && (FVP_CLUSTER_COUNT <= 256)), + assert_invalid_fvp_cluster_count); /******************************************************************************* * This function dynamically constructs the topology according to @@ -24,7 +25,7 @@ CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluste ******************************************************************************/ const unsigned char *plat_get_power_domain_tree_desc(void) { - unsigned int i; + int i; /* * The highest level is the system level. The next level is constituted @@ -60,7 +61,7 @@ int plat_core_pos_by_mpidr(u_register_t mpidr) unsigned int clus_id, cpu_id, thread_id; /* Validate affinity fields */ - if (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) { + if ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) { thread_id = MPIDR_AFFLVL0_VAL(mpidr); cpu_id = MPIDR_AFFLVL1_VAL(mpidr); clus_id = MPIDR_AFFLVL2_VAL(mpidr); @@ -90,5 +91,5 @@ int plat_core_pos_by_mpidr(u_register_t mpidr) * bit set. */ mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); - return plat_arm_calc_core_pos(mpidr); + return (int) plat_arm_calc_core_pos(mpidr); } diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index e4df227d..8f1a0cda 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -52,7 +52,7 @@ #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ /* virtual address used by dynamic mem_protect for chunk_base */ -#define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000 +#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) /* No SCP in FVP */ #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) @@ -215,9 +215,9 @@ */ #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ ARM_G1S_IRQ_PROPS(grp), \ - INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ + INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ GIC_INTR_CFG_LEVEL) #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 9bd3bde6..332df4d4 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -147,13 +147,13 @@ BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ ${FVP_SECURITY_SOURCES} BL31_SOURCES += drivers/arm/smmu/smmu_v3.c \ + drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/board/fvp/fvp_bl31_setup.c \ plat/arm/board/fvp/fvp_pm.c \ plat/arm/board/fvp/fvp_topology.c \ plat/arm/board/fvp/aarch64/fvp_helpers.S \ plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \ - plat/arm/board/common/drivers/norflash/norflash.c \ plat/arm/common/arm_nor_psci_mem_protect.c \ ${FVP_CPU_LIBS} \ ${FVP_GIC_SOURCES} \ diff --git a/plat/arm/board/fvp/sp_min/sp_min-fvp.mk b/plat/arm/board/fvp/sp_min/sp_min-fvp.mk index b370fd55..8b17c9b7 100644 --- a/plat/arm/board/fvp/sp_min/sp_min-fvp.mk +++ b/plat/arm/board/fvp/sp_min/sp_min-fvp.mk @@ -1,17 +1,17 @@ # -# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # # SP_MIN source files specific to FVP platform -BL32_SOURCES += lib/utils/mem_region.c \ +BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \ + lib/utils/mem_region.c \ plat/arm/board/fvp/aarch32/fvp_helpers.S \ plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \ plat/arm/board/fvp/fvp_pm.c \ plat/arm/board/fvp/fvp_topology.c \ plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c \ - plat/arm/board/common/drivers/norflash/norflash.c \ plat/arm/common/arm_nor_psci_mem_protect.c \ ${FVP_CPU_LIBS} \ ${FVP_GIC_SOURCES} \ diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index d130bebe..ed78b461 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -60,7 +60,7 @@ #define NSRAM_SIZE 0x00008000 /* 32KB */ /* virtual address used by dynamic mem_protect for chunk_base */ -#define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000 +#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) /* * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB @@ -236,21 +236,21 @@ CSS_G1S_IRQ_PROPS(grp), \ ARM_G1S_IRQ_PROPS(grp), \ INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ + (grp), GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ + (grp), GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ + (grp), GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ + (grp), GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ + (grp), GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ + (grp), GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ + (grp), GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL) + (grp), GIC_INTR_CFG_LEVEL) #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) diff --git a/plat/arm/board/juno/juno_topology.c b/plat/arm/board/juno/juno_topology.c index 5f031c84..72bb92e0 100644 --- a/plat/arm/board/juno/juno_topology.c +++ b/plat/arm/board/juno/juno_topology.c @@ -50,8 +50,8 @@ const unsigned char *plat_get_power_domain_tree_desc(void) ******************************************************************************/ unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) { - return (((mpidr) & 0x100) ? JUNO_CLUSTER1_CORE_COUNT :\ - JUNO_CLUSTER0_CORE_COUNT); + return (((mpidr & (u_register_t) 0x100) != 0U) ? + JUNO_CLUSTER1_CORE_COUNT : JUNO_CLUSTER0_CORE_COUNT); } /* diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index 90fa938a..e2ec3c1c 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -73,12 +73,12 @@ BL2_SOURCES += lib/utils/mem_region.c \ BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} -BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ +BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ + lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ lib/utils/mem_region.c \ plat/arm/board/juno/juno_topology.c \ - plat/arm/board/common/drivers/norflash/norflash.c \ plat/arm/common/arm_nor_psci_mem_protect.c \ ${JUNO_GIC_SOURCES} \ ${JUNO_INTERCONNECT_SOURCES} \ @@ -90,6 +90,11 @@ endif endif +ifneq (${RESET_TO_BL31},0) + $(error "Using BL31 as the reset vector is not supported on ${PLATFORM} platform. \ + Please set RESET_TO_BL31 to 0.") +endif + # Errata workarounds for Cortex-A53: ERRATA_A53_826319 := 1 ERRATA_A53_835769 := 1 diff --git a/plat/arm/board/juno/sp_min/sp_min-juno.mk b/plat/arm/board/juno/sp_min/sp_min-juno.mk index cd1f4976..52781093 100644 --- a/plat/arm/board/juno/sp_min/sp_min-juno.mk +++ b/plat/arm/board/juno/sp_min/sp_min-juno.mk @@ -1,15 +1,15 @@ # -# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # # SP_MIN source files specific to JUNO platform -BL32_SOURCES += lib/cpus/aarch32/cortex_a53.S \ +BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \ + lib/cpus/aarch32/cortex_a53.S \ lib/cpus/aarch32/cortex_a57.S \ lib/cpus/aarch32/cortex_a72.S \ lib/utils/mem_region.c \ - plat/arm/board/common/drivers/norflash/norflash.c \ plat/arm/board/juno/juno_topology.c \ plat/arm/common/arm_nor_psci_mem_protect.c \ plat/arm/soc/common/soc_css_security.c \ diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk index 284bae8a..078f393c 100644 --- a/plat/arm/board/sgi575/platform.mk +++ b/plat/arm/board/sgi575/platform.mk @@ -9,6 +9,6 @@ include plat/arm/css/sgi/sgi-common.mk BL2_SOURCES += lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c -BL31_SOURCES += lib/utils/mem_region.c \ - plat/arm/board/common/drivers/norflash/norflash.c \ +BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ + lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk index 633cee66..c8337554 100644 --- a/plat/arm/board/sgm775/platform.mk +++ b/plat/arm/board/sgm775/platform.mk @@ -15,6 +15,6 @@ PLAT_INCLUDES +=-I${SGM775_BASE}/include/ BL2_SOURCES += lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c -BL31_SOURCES += lib/utils/mem_region.c \ - plat/arm/board/common/drivers/norflash/norflash.c \ +BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ + lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index ed2c3fbc..e218c2f0 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -78,7 +78,7 @@ struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) /******************************************************************************* * Perform any BL31 early platform setup common to ARM standard platforms. * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 - * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be + * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be * done before the MMU is initialized so that the memory layout can be used * while creating page tables. BL2 has flushed this information to memory, so * we are guaranteed to pick up good data. diff --git a/plat/arm/common/arm_err.c b/plat/arm/common/arm_err.c index e13e51f7..519d44d7 100644 --- a/plat/arm/common/arm_err.c +++ b/plat/arm/common/arm_err.c @@ -8,10 +8,10 @@ #include <console.h> #include <debug.h> #include <errno.h> -#include <norflash.h> #include <platform.h> #include <platform_def.h> #include <stdint.h> +#include <v2m_flash.h> #pragma weak plat_arm_error_handler diff --git a/plat/arm/common/arm_nor_psci_mem_protect.c b/plat/arm/common/arm_nor_psci_mem_protect.c index 1b0b1da6..2a46b95d 100644 --- a/plat/arm/common/arm_nor_psci_mem_protect.c +++ b/plat/arm/common/arm_nor_psci_mem_protect.c @@ -6,12 +6,11 @@ #include <debug.h> #include <mmio.h> -#include <norflash.h> #include <plat_arm.h> #include <platform_def.h> #include <psci.h> #include <utils.h> - +#include <v2m_flash.h> /* * DRAM1 is used also to load the NS boot loader. For this reason we @@ -51,14 +50,14 @@ int arm_psci_read_mem_protect(int *enabled) ******************************************************************************/ int arm_nor_psci_write_mem_protect(int val) { - int enable = (val != 0) ? 1 : 0; + unsigned long enable = (val != 0) ? 1UL : 0UL; if (nor_unlock(PLAT_ARM_MEM_PROT_ADDR) != 0) { ERROR("unlocking memory protect variable\n"); return -1; } - if (enable == 1) { + if (enable == 1UL) { /* * If we want to write a value different than 0 * then we have to erase the full block because diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index 85efc7dd..6394bfb5 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -29,7 +29,7 @@ int arm_validate_power_state(unsigned int power_state, unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state); unsigned int i; - assert(req_state > 0U); + assert(req_state != NULL); if (pwr_lvl > PLAT_MAX_PWR_LVL) return PSCI_E_INVALID_PARAMS; @@ -72,7 +72,7 @@ int arm_validate_power_state(unsigned int power_state, unsigned int state_id; int i; - assert(req_state); + assert(req_state != NULL); /* * Currently we are using a linear search for finding the matching @@ -128,7 +128,7 @@ int arm_validate_ns_entrypoint(uintptr_t entrypoint) int arm_validate_psci_entrypoint(uintptr_t entrypoint) { - return arm_validate_ns_entrypoint(entrypoint) == 0 ? PSCI_E_SUCCESS : + return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS : PSCI_E_INVALID_ADDRESS; } diff --git a/plat/arm/common/arm_topology.c b/plat/arm/common/arm_topology.c index c6d12dad..b0ad4d1c 100644 --- a/plat/arm/common/arm_topology.c +++ b/plat/arm/common/arm_topology.c @@ -29,12 +29,14 @@ int arm_check_mpidr(u_register_t mpidr) pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; #else valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK); - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) & + MPIDR_AFFLVL_MASK); + cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) & + MPIDR_AFFLVL_MASK); #endif /* ARM_PLAT_MT */ mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & valid_mask) + if ((mpidr & valid_mask) != 0U) return -1; if (cluster_id >= PLAT_ARM_CLUSTER_COUNT) diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk index 984c1da0..ca1edab1 100644 --- a/plat/arm/css/common/css_common.mk +++ b/plat/arm/css/common/css_common.mk @@ -39,11 +39,6 @@ BL31_SOURCES += plat/arm/css/drivers/scp/css_pm_scmi.c \ plat/arm/css/drivers/mhu/css_mhu_doorbell.c endif -ifneq (${RESET_TO_BL31},0) - $(error "Using BL31 as the reset vector is not supported on CSS platforms. \ - Please set RESET_TO_BL31 to 0.") -endif - # Process CSS_LOAD_SCP_IMAGES flag $(eval $(call assert_boolean,CSS_LOAD_SCP_IMAGES)) $(eval $(call add_define,CSS_LOAD_SCP_IMAGES)) diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk index 28f97b1f..24f03dd4 100644 --- a/plat/arm/css/sgi/sgi-common.mk +++ b/plat/arm/css/sgi/sgi-common.mk @@ -67,6 +67,11 @@ HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb # Add the HW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config)) +ifneq (${RESET_TO_BL31},0) + $(error "Using BL31 as the reset vector is not supported on ${PLATFORM} platform. \ + Please set RESET_TO_BL31 to 0.") +endif + $(eval $(call add_define,SGI_PLAT)) override CSS_LOAD_SCP_IMAGES := 0 diff --git a/plat/arm/css/sgm/sgm-common.mk b/plat/arm/css/sgm/sgm-common.mk index b10e14cb..3eb48403 100644 --- a/plat/arm/css/sgm/sgm-common.mk +++ b/plat/arm/css/sgm/sgm-common.mk @@ -45,6 +45,11 @@ BL31_SOURCES += $(SGM_CPU_SOURCES) \ ${CSS_SGM_BASE}/sgm_bl31_setup.c \ ${CSS_SGM_BASE}/sgm_plat_config.c +ifneq (${RESET_TO_BL31},0) + $(error "Using BL31 as the reset vector is not supported on ${PLATFORM} platform. \ + Please set RESET_TO_BL31 to 0.") +endif + # sgm uses CCI-500 as Cache Coherent Interconnect ARM_CCI_PRODUCT_ID := 500 diff --git a/plat/arm/css/sgm/sgm_bl1_setup.c b/plat/arm/css/sgm/sgm_bl1_setup.c index 51e3e533..dc3d71dd 100644 --- a/plat/arm/css/sgm/sgm_bl1_setup.c +++ b/plat/arm/css/sgm/sgm_bl1_setup.c @@ -12,11 +12,13 @@ void bl1_early_platform_setup(void) { - /* Initialize the platform configuration structure */ - plat_config_init(); + /* Initialize the console before anything else */ arm_bl1_early_platform_setup(); + /* Initialize the platform configuration structure */ + plat_config_init(); + #if !HW_ASSISTED_COHERENCY /* * Initialize Interconnect for this cluster during cold boot. diff --git a/plat/hisilicon/poplar/bl31_plat_setup.c b/plat/hisilicon/poplar/bl31_plat_setup.c index b45693f5..83803a66 100644 --- a/plat/hisilicon/poplar/bl31_plat_setup.c +++ b/plat/hisilicon/poplar/bl31_plat_setup.c @@ -61,7 +61,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) /******************************************************************************* * Perform any BL31 early platform setup common to ARM standard platforms. * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 - * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be + * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be * done before the MMU is initialized so that the memory layout can be used * while creating page tables. BL2 has flushed this information to memory, so * we are guaranteed to pick up good data. diff --git a/plat/layerscape/common/ls_bl31_setup.c b/plat/layerscape/common/ls_bl31_setup.c index 1114a51e..2067b902 100644 --- a/plat/layerscape/common/ls_bl31_setup.c +++ b/plat/layerscape/common/ls_bl31_setup.c @@ -58,7 +58,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) /******************************************************************************* * Perform any BL31 early platform setup common to Layerscape platforms. * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 - * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be + * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be * done before the MMU is initialized so that the memory layout can be used * while creating page tables. BL2 has flushed this information to memory, so * we are guaranteed to pick up good data. diff --git a/plat/marvell/common/marvell_bl2_setup.c b/plat/marvell/common/marvell_bl2_setup.c index f7149c39..d33aba47 100644 --- a/plat/marvell/common/marvell_bl2_setup.c +++ b/plat/marvell/common/marvell_bl2_setup.c @@ -105,7 +105,15 @@ int marvell_bl2_handle_post_image_load(unsigned int image_id) bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); bl_mem_params->ep_info.spsr = marvell_get_spsr_for_bl33_entry(); break; - +#ifdef SCP_BL2_BASE + case SCP_BL2_IMAGE_ID: + /* The subsequent handling of SCP_BL2 is platform specific */ + err = bl2_plat_handle_scp_bl2(&bl_mem_params->image_info); + if (err) { + WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); + } + break; +#endif default: /* Do nothing in default case */ break; diff --git a/plat/marvell/common/marvell_bl31_setup.c b/plat/marvell/common/marvell_bl31_setup.c index 0bbb940f..da91b560 100644 --- a/plat/marvell/common/marvell_bl31_setup.c +++ b/plat/marvell/common/marvell_bl31_setup.c @@ -62,7 +62,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) /***************************************************************************** * Perform any BL31 early platform setup common to ARM standard platforms. * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 - * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be + * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be * done before the MMU is initialized so that the memory layout can be used * while creating page tables. BL2 has flushed this information to memory, so * we are guaranteed to pick up good data. diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c index d9577a6f..96a0bd83 100644 --- a/plat/mediatek/mt6795/bl31_plat_setup.c +++ b/plat/mediatek/mt6795/bl31_plat_setup.c @@ -165,7 +165,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) /******************************************************************************* * Perform any BL3-1 early platform setup. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they * are lost (potentially). This needs to be done before the MMU is initialized * so that the memory layout can be used while creating page tables. * BL2 has flushed this information to memory, so we are guaranteed to pick up diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index ce523096..c27de829 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -86,7 +86,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) /******************************************************************************* * Perform any BL3-1 early platform setup. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they * are lost (potentially). This needs to be done before the MMU is initialized * so that the memory layout can be used while creating page tables. * BL2 has flushed this information to memory, so we are guaranteed to pick up diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c index 8b4312cf..7542674e 100644 --- a/plat/qemu/qemu_bl31_setup.c +++ b/plat/qemu/qemu_bl31_setup.c @@ -30,7 +30,7 @@ static entry_point_info_t bl33_image_ep_info; /******************************************************************************* * Perform any BL3-1 early platform setup. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before * they are lost (potentially). This needs to be done before the MMU is * initialized so that the memory layout can be used while creating page * tables. BL2 has flushed this information to memory, so we are guaranteed diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index b8ec8c1c..7a9f7a9d 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -54,7 +54,7 @@ void params_early_setup(void *plat_param_from_bl2) /******************************************************************************* * Perform any BL3-1 early platform setup. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they * are lost (potentially). This needs to be done before the MMU is initialized * so that the memory layout can be used while creating page tables. * BL2 has flushed this information to memory, so we are guaranteed to pick up diff --git a/plat/rpi3/rpi3_bl31_setup.c b/plat/rpi3/rpi3_bl31_setup.c index 306f26b3..0ae783e1 100644 --- a/plat/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi3/rpi3_bl31_setup.c @@ -47,7 +47,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) /******************************************************************************* * Perform any BL31 early platform setup. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before * they are lost (potentially). This needs to be done before the MMU is * initialized so that the memory layout can be used while creating page * tables. BL2 has flushed this information to memory, so we are guaranteed diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 02f1811f..a14388f5 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -50,7 +50,7 @@ static inline void bl31_set_default_config(void) /* * Perform any BL31 specific platform actions. Here is an opportunity to copy - * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they * are lost (potentially). This needs to be done before the MMU is initialized * so that the memory layout can be used while creating page tables. */ diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile index 7b10e3e3..c03629a0 100644 --- a/tools/cert_create/Makefile +++ b/tools/cert_create/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -22,7 +22,7 @@ OBJECTS := src/cert.o \ src/tbbr/tbb_ext.o \ src/tbbr/tbb_key.o -CFLAGS := -Wall -std=c99 +HOSTCCFLAGS := -Wall -std=c99 MAKE_HELPERS_DIRECTORY := ../../make_helpers/ include ${MAKE_HELPERS_DIRECTORY}build_macros.mk @@ -46,9 +46,9 @@ endif endif ifeq (${DEBUG},1) - CFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40 + HOSTCCFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40 else - CFLAGS += -O2 -DLOG_LEVEL=20 + HOSTCCFLAGS += -O2 -DLOG_LEVEL=20 endif ifeq (${V},0) Q := @ @@ -57,7 +57,7 @@ else endif $(eval $(call add_define,USE_TBBR_DEFS)) -CFLAGS += ${DEFINES} +HOSTCCFLAGS += ${DEFINES} # Make soft links and include from local directory otherwise wrong headers # could get pulled in from firmware tree. @@ -72,15 +72,15 @@ HOSTCC ?= gcc all: clean ${BINARY} ${BINARY}: ${OBJECTS} Makefile - @echo " LD $@" + @echo " HOSTLD $@" @echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__; \ const char platform_msg[] = "${PLAT_MSG}";' | \ - ${HOSTCC} -c ${CFLAGS} -xc - -o src/build_msg.o + ${HOSTCC} -c ${HOSTCCFLAGS} -xc - -o src/build_msg.o ${Q}${HOSTCC} src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@ %.o: %.c - @echo " CC $<" - ${Q}${HOSTCC} -c ${CFLAGS} ${INC_DIR} $< -o $@ + @echo " HOSTCC $<" + ${Q}${HOSTCC} -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@ clean: $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS}) diff --git a/tools/doimage/Makefile b/tools/doimage/Makefile index 9cec681a..9f0d89d3 100644 --- a/tools/doimage/Makefile +++ b/tools/doimage/Makefile @@ -7,11 +7,11 @@ PROJECT = doimage OBJECTS = doimage.o -CFLAGS = -Wall -Werror +HOSTCCFLAGS = -Wall -Werror ifeq (${DEBUG},1) - CFLAGS += -g -O0 -DDEBUG + HOSTCCFLAGS += -g -O0 -DDEBUG else - CFLAGS += -O2 + HOSTCCFLAGS += -O2 endif ifeq (${MARVELL_SECURE_BOOT},1) @@ -19,13 +19,13 @@ DOIMAGE_CC_FLAGS := -DCONFIG_MVEBU_SECURE_BOOT DOIMAGE_LD_FLAGS := -lconfig -lmbedtls -lmbedcrypto -lmbedx509 endif -CFLAGS += ${DOIMAGE_CC_FLAGS} +HOSTCCFLAGS += ${DOIMAGE_CC_FLAGS} # Make soft links and include from local directory otherwise wrong headers # could get pulled in from firmware tree. INCLUDE_PATHS = -I. -CC := gcc +HOSTCC ?= gcc RM := rm -rf .PHONY: all clean @@ -33,15 +33,15 @@ RM := rm -rf all: ${PROJECT} ${PROJECT}: ${OBJECTS} Makefile - @echo " LD $@" - ${Q}${CC} ${OBJECTS} ${DOIMAGE_LD_FLAGS} -o $@ + @echo " HOSTLD $@" + ${Q}${HOSTCC} ${OBJECTS} ${DOIMAGE_LD_FLAGS} -o $@ @echo @echo "Built $@ successfully" @echo %.o: %.c Makefile - @echo " CC $<" - ${Q}${CC} -c ${CFLAGS} ${INCLUDE_PATHS} $< -o $@ + @echo " HOSTCC $<" + ${Q}${HOSTCC} -c ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@ clean: ${Q}${RM} ${PROJECT} diff --git a/tools/doimage/doimage.c b/tools/doimage/doimage.c index 6fc23d50..82fd375f 100644 --- a/tools/doimage/doimage.c +++ b/tools/doimage/doimage.c @@ -216,7 +216,7 @@ void usage(void) } /* globals */ -options_t opts = { +static options_t opts = { .bin_ext_file = "NA", .sec_cfg_file = "NA", .sec_opts = 0, @@ -1578,9 +1578,9 @@ error: int main(int argc, char *argv[]) { - char in_file[MAX_FILENAME+1]; - char out_file[MAX_FILENAME+1]; - char ext_file[MAX_FILENAME+1]; + char in_file[MAX_FILENAME+1] = { 0 }; + char out_file[MAX_FILENAME+1] = { 0 }; + char ext_file[MAX_FILENAME+1] = { 0 }; FILE *in_fd = NULL; FILE *out_fd = NULL; int parse = 0; @@ -1590,6 +1590,7 @@ int main(int argc, char *argv[]) int image_size; uint8_t *image_buf = NULL; int read; + size_t len; uint32_t nand_block_size_kb, mlc_nand; /* Create temporary file for building extensions @@ -1660,13 +1661,19 @@ int main(int argc, char *argv[]) if (optind >= argc) usage_err("missing input file name"); - strncpy(in_file, argv[optind], MAX_FILENAME); + len = strlen(argv[optind]); + if (len > MAX_FILENAME) + usage_err("file name too long"); + memcpy(in_file, argv[optind], len); optind++; /* Output file must exist in non parse mode */ - if (optind < argc) - strncpy(out_file, argv[optind], MAX_FILENAME); - else if (!parse) + if (optind < argc) { + len = strlen(argv[optind]); + if (len > MAX_FILENAME) + usage_err("file name too long"); + memcpy(out_file, argv[optind], len); + } else if (!parse) usage_err("missing output file name"); /* open the input file */ diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile index 9bdafe00..ef350143 100644 --- a/tools/fiptool/Makefile +++ b/tools/fiptool/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -13,11 +13,11 @@ OBJECTS := fiptool.o tbbr_config.o V ?= 0 override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700 -CFLAGS := -Wall -Werror -pedantic -std=c99 +HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 ifeq (${DEBUG},1) - CFLAGS += -g -O0 -DDEBUG + HOSTCCFLAGS += -g -O0 -DDEBUG else - CFLAGS += -O2 + HOSTCCFLAGS += -O2 endif LDLIBS := -lcrypto @@ -36,15 +36,15 @@ HOSTCC ?= gcc all: ${PROJECT} ${PROJECT}: ${OBJECTS} Makefile - @echo " LD $@" + @echo " HOSTLD $@" ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} @${ECHO_BLANK_LINE} @echo "Built $@ successfully" @${ECHO_BLANK_LINE} %.o: %.c %.h Makefile - @echo " CC $<" - ${Q}${HOSTCC} -c ${CPPFLAGS} ${CFLAGS} ${INCLUDE_PATHS} $< -o $@ + @echo " HOSTCC $<" + ${Q}${HOSTCC} -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@ clean: $(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS}) diff --git a/tools/stm32image/Makefile b/tools/stm32image/Makefile index a593d316..9c9b7b5f 100644 --- a/tools/stm32image/Makefile +++ b/tools/stm32image/Makefile @@ -12,11 +12,12 @@ PROJECT := stm32image${BIN_EXT} OBJECTS := stm32image.o V := 0 -CFLAGS := -Wall -Werror -pedantic -std=c99 -D_GNU_SOURCE +HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 -D_GNU_SOURCE + ifeq (${DEBUG},1) - CFLAGS += -g -O0 -DDEBUG + HOSTCCFLAGS += -g -O0 -DDEBUG else - CFLAGS += -O2 + HOSTCCFLAGS += -O2 endif ifeq (${V},0) @@ -25,22 +26,22 @@ else Q := endif -CC := gcc +HOSTCC := gcc .PHONY: all clean distclean all: ${PROJECT} ${PROJECT}: ${OBJECTS} Makefile - @echo " LD $@" - ${Q}${CC} ${OBJECTS} -o $@ + @echo " HOSTLD $@" + ${Q}${HOSTCC} ${OBJECTS} -o $@ @${ECHO_BLANK_LINE} @echo "Built $@ successfully" @${ECHO_BLANK_LINE} %.o: %.c Makefile - @echo " CC $<" - ${Q}${CC} -c ${CFLAGS} $< -o $@ + @echo " HOSTCC $<" + ${Q}${HOSTCC} -c ${HOSTCCFLAGS} $< -o $@ clean: $(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS}) |