diff options
85 files changed, 1145 insertions, 1030 deletions
@@ -8,7 +8,7 @@ # Trusted Firmware Version # VERSION_MAJOR := 1 -VERSION_MINOR := 4 +VERSION_MINOR := 5 # Default goal is build all images .DEFAULT_GOAL := all @@ -275,13 +275,6 @@ endif endif ################################################################################ -# Include libraries' Makefile that are used in all BL -################################################################################ - -include lib/stack_protector/stack_protector.mk - - -################################################################################ # Include the platform specific Makefile after the SPD Makefile (the platform # makefile may use all previous definitions in this file) ################################################################################ @@ -441,6 +434,12 @@ FIP_ARGS += --align ${FIP_ALIGN} endif ################################################################################ +# Include libraries' Makefile that are used in all BL +################################################################################ + +include lib/stack_protector/stack_protector.mk + +################################################################################ # Auxiliary tools (fiptool, cert_create, etc) ################################################################################ diff --git a/bl1/aarch32/bl1_context_mgmt.c b/bl1/aarch32/bl1_context_mgmt.c index 6623dfc4..d1fd3ca0 100644 --- a/bl1/aarch32/bl1_context_mgmt.c +++ b/bl1/aarch32/bl1_context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ #include <context_mgmt.h> #include <debug.h> #include <platform.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> #include "../bl1_private.h" /* diff --git a/bl1/aarch32/bl1_entrypoint.S b/bl1/aarch32/bl1_entrypoint.S index 77806269..16b26b9f 100644 --- a/bl1/aarch32/bl1_entrypoint.S +++ b/bl1/aarch32/bl1_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,8 @@ #include <bl_common.h> #include <context.h> #include <el3_common_macros.S> -#include <smcc_helpers.h> -#include <smcc_macros.S> +#include <smccc_helpers.h> +#include <smccc_macros.S> .globl bl1_vector_table .globl bl1_entrypoint diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S index a1e32f06..15405424 100644 --- a/bl1/aarch32/bl1_exceptions.S +++ b/bl1/aarch32/bl1_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,8 @@ #include <bl1.h> #include <bl_common.h> #include <context.h> -#include <smcc_helpers.h> -#include <smcc_macros.S> +#include <smccc_helpers.h> +#include <smccc_macros.S> #include <xlat_tables.h> .globl bl1_aarch32_smc_handler @@ -93,7 +93,7 @@ func smc_handler * Save the GP registers. * ----------------------------------------------------- */ - smcc_save_gp_mode_regs + smccc_save_gp_mode_regs /* * `sp` still points to `smc_ctx_t`. Save it to a register diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 92313fa3..7ac028a5 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -218,7 +218,7 @@ unexpected_sync_exception: smc_handler: /* ----------------------------------------------------- * Save the GP registers x0-x29. - * TODO: Revisit to store only SMCC specified registers. + * TODO: Revisit to store only SMCCC specified registers. * ----------------------------------------------------- */ bl save_gp_registers diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index 38780833..ed027abc 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -15,7 +15,7 @@ #include <errno.h> #include <platform.h> #include <platform_def.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> #include <string.h> #include <utils.h> #include "bl1_private.h" diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index c3332853..9f7e2901 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -15,7 +15,7 @@ #include <errata_report.h> #include <platform.h> #include <platform_def.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> #include <utils.h> #include <uuid.h> #include "bl1_private.h" diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h index 6ac3b8c6..42a74d22 100644 --- a/bl1/bl1_private.h +++ b/bl1/bl1_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,18 +8,16 @@ #define __BL1_PRIVATE_H__ #include <types.h> +#include <utils_def.h> /******************************************************************************* * Declarations of linker defined symbols which will tell us where BL1 lives * in Trusted ROM and RAM ******************************************************************************/ -extern uintptr_t __BL1_ROM_END__; -#define BL1_ROM_END (uintptr_t)(&__BL1_ROM_END__) +IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END); -extern uintptr_t __BL1_RAM_START__; -extern uintptr_t __BL1_RAM_END__; -#define BL1_RAM_BASE (uintptr_t)(&__BL1_RAM_START__) -#define BL1_RAM_LIMIT (uintptr_t)(&__BL1_RAM_END__) +IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE); +IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT); /****************************************** * Function prototypes diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 3dd23696..87ef3f36 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -10,8 +10,8 @@ #include <context.h> #include <el3_common_macros.S> #include <runtime_svc.h> -#include <smcc_helpers.h> -#include <smcc_macros.S> +#include <smccc_helpers.h> +#include <smccc_macros.S> #include <xlat_tables_defs.h> .globl sp_min_vector_table @@ -164,7 +164,7 @@ func sp_min_handle_smc /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */ str lr, [sp, #SMC_CTX_LR_MON] - smcc_save_gp_mode_regs + smccc_save_gp_mode_regs clrex_on_monitor_entry @@ -222,7 +222,7 @@ func sp_min_handle_fiq /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */ str lr, [sp, #SMC_CTX_LR_MON] - smcc_save_gp_mode_regs + smccc_save_gp_mode_regs clrex_on_monitor_entry diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c index 4e8e685e..8e891b75 100644 --- a/bl32/sp_min/sp_min_main.c +++ b/bl32/sp_min/sp_min_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ #include <platform_sp_min.h> #include <psci.h> #include <runtime_svc.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> #include <stddef.h> #include <stdint.h> #include <string.h> @@ -32,7 +32,7 @@ static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT]; static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT]; /****************************************************************************** - * Define the smcc helper library API's + * Define the smccc helper library API's *****************************************************************************/ void *smc_get_ctx(unsigned int security_state) { diff --git a/common/runtime_svc.c b/common/runtime_svc.c index 0ea4cd09..de80f30c 100644 --- a/common/runtime_svc.c +++ b/common/runtime_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,8 +19,6 @@ * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the * 'rt_svc_descs' array which contains the SMC handler. ******************************************************************************/ -#define RT_SVC_DESCS_START ((uintptr_t) (&__RT_SVC_DESCS_START__)) -#define RT_SVC_DESCS_END ((uintptr_t) (&__RT_SVC_DESCS_END__)) uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; static rt_svc_desc_t *rt_svc_descs; diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst index c30110ed..b7879a85 100644 --- a/docs/plat/rpi3.rst +++ b/docs/plat/rpi3.rst @@ -247,6 +247,11 @@ The following is not currently supported: - ``LOAD_IMAGE_V2=0``: Only version 2 is supported. +- ``MULTI_CONSOLE_API=0``: The multi console API must be enabled. Note that the + crash console uses the internal 16550 driver functions directly in order to be + able to print error messages during early crashes before setting up the + multi console API. + AArch64 kernel build instructions --------------------------------- @@ -300,7 +305,7 @@ Setup SD card The instructions assume that you have an SD card with a fresh install of `Raspbian`_ (or that, at least, the ``boot`` partition is untouched, or nearly -untouched). They have been tested with the image available in 2017-09-07. +untouched). They have been tested with the image available in 2018-03-13. 1. Insert the SD card and open the ``boot`` partition. diff --git a/docs/psci-lib-integration-guide.rst b/docs/psci-lib-integration-guide.rst index 6e72f0e7..47cbfcc8 100644 --- a/docs/psci-lib-integration-guide.rst +++ b/docs/psci-lib-integration-guide.rst @@ -261,7 +261,7 @@ argument) determines the PSCI API to be called. The ``x1`` to ``x4`` (2nd to 5th arguments), are the values of the registers r1 - r4 (in AArch32) or x1 - x4 (in AArch64) when the SMC is received. These are the arguments to PSCI API as described in `PSCI spec`_. The 'flags' (8th argument) is a bit field parameter -and is detailed in 'smcc.h' header. It includes whether the call is from the +and is detailed in 'smccc.h' header. It includes whether the call is from the secure or non-secure world. The ``cookie`` (6th argument) and the ``handle`` (7th argument) are not used and are reserved for future use. diff --git a/docs/rt-svc-writers-guide.rst b/docs/rt-svc-writers-guide.rst index 4d0016b8..cec2ae70 100644 --- a/docs/rt-svc-writers-guide.rst +++ b/docs/rt-svc-writers-guide.rst @@ -108,7 +108,7 @@ initialization and call handler functions. is also used for diagnostic purposes - ``_start`` and ``_end`` values must be based on the ``OEN_*`` values defined in - `smcc.h`_ + `smccc.h`_ - ``_type`` must be one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD`` @@ -311,5 +311,5 @@ provide this information.... .. _services: ../services .. _lib/psci: ../lib/psci .. _runtime\_svc.h: ../include/common/runtime_svc.h -.. _smcc.h: ../include/lib/smcc.h +.. _smccc.h: ../include/lib/smccc.h .. _std\_svc\_setup.c: ../services/std_svc/std_svc_setup.c diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 33f124a7..57948554 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -38,7 +38,7 @@ running the FVP models is a dual-core processor running at 2GHz with 12GB of RAM. For best performance, use a machine with a quad-core processor running at 2.6GHz with 16GB of RAM. -The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for +The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for building the software were installed from that distribution unless otherwise specified. @@ -867,9 +867,12 @@ must be in compliance with the Linux style guide, and to assist with this check the project Makefile contains two targets, which both utilise the ``checkpatch.pl`` script that ships with the Linux source tree. -To check the entire source tree, you must first download a copy of -``checkpatch.pl`` (or the full Linux source), set the ``CHECKPATCH`` environment -variable to point to the script and build the target checkcodebase: +To check the entire source tree, you must first download copies of +``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available +in the `Linux master tree`_ scripts directory, then set the ``CHECKPATCH`` +environment variable to point to ``checkpatch.pl`` (with the other 2 files in +the same directory) and build the target +checkcodebase: :: @@ -1149,10 +1152,15 @@ a single FIP binary. It assumes that a `Linaro Release`_ has been installed. Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12 onwards. Before that release, pre-built binaries are only available for AArch64. -Note: follow the full instructions for one platform before switching to a +Note: Follow the full instructions for one platform before switching to a different one. Mixing instructions for different platforms may result in corrupted binaries. +Note: The uboot image downloaded by the Linaro workspace script does not always +match the uboot image packaged as BL33 in the corresponding fip file. It is +recommended to use the version that is packaged in the fip file using the +instructions below. + #. Clean the working directory :: @@ -1177,11 +1185,11 @@ corrupted binaries. current working directory. The SCP\_BL2 image corresponds to ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``. - Note: the fiptool will complain if the images to be unpacked already + Note: The fiptool will complain if the images to be unpacked already exist in the current directory. If that is the case, either delete those files or use the ``--force`` option to overwrite. - Note for AArch32, the instructions below assume that nt-fw.bin is a custom + Note: For AArch32, the instructions below assume that nt-fw.bin is a custom Normal world boot loader that supports AArch32. #. Build TF-A images and create a new FIP for FVP @@ -1924,6 +1932,7 @@ wakeup interrupt from RTC. .. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/ .. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php +.. _Linux master tree: <https://github.com/torvalds/linux/tree/master/> .. _Dia: https://wiki.gnome.org/Apps/Dia/Download .. _here: psci-lib-integration-guide.rst .. _Trusted Board Boot: trusted-board-boot.rst diff --git a/drivers/arm/pl011/aarch64/pl011_console.S b/drivers/arm/pl011/aarch64/pl011_console.S index 6f2510ad..448501a2 100644 --- a/drivers/arm/pl011/aarch64/pl011_console.S +++ b/drivers/arm/pl011/aarch64/pl011_console.S @@ -6,6 +6,7 @@ #include <arch.h> #include <asm_macros.S> #include <assert_macros.S> +#include <console_macros.S> #include <pl011.h> /* diff --git a/drivers/auth/img_parser_mod.c b/drivers/auth/img_parser_mod.c index 6a010711..63160141 100644 --- a/drivers/auth/img_parser_mod.c +++ b/drivers/auth/img_parser_mod.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,11 +12,10 @@ #include <limits.h> #include <stdint.h> #include <string.h> +#include <utils_def.h> -extern uintptr_t __PARSER_LIB_DESCS_START__; -extern uintptr_t __PARSER_LIB_DESCS_END__; -#define PARSER_LIB_DESCS_START ((uintptr_t) (&__PARSER_LIB_DESCS_START__)) -#define PARSER_LIB_DESCS_END ((uintptr_t) (&__PARSER_LIB_DESCS_END__)) +IMPORT_SYM(uintptr_t, __PARSER_LIB_DESCS_START__, PARSER_LIB_DESCS_START); +IMPORT_SYM(uintptr_t, __PARSER_LIB_DESCS_END__, PARSER_LIB_DESCS_END); static unsigned int parser_lib_indices[IMG_MAX_TYPES]; static img_parser_lib_desc_t *parser_lib_descs; diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S index b02209df..56e7e5c1 100644 --- a/drivers/ti/uart/aarch64/16550_console.S +++ b/drivers/ti/uart/aarch64/16550_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,10 +17,11 @@ .globl console_16550_core_init .globl console_16550_core_putc .globl console_16550_core_getc + .globl console_16550_core_flush .globl console_16550_putc .globl console_16550_getc - + .globl console_16550_flush /* ----------------------------------------------- * int console_16550_core_init(uintptr_t base_addr, @@ -119,6 +120,7 @@ endfunc console_16550_register .equ console_core_init,console_16550_core_init .equ console_core_putc,console_16550_core_putc .equ console_core_getc,console_16550_core_getc + .equ console_core_flush,console_16550_core_flush #endif /* -------------------------------------------------------- @@ -222,8 +224,7 @@ func console_16550_getc endfunc console_16550_getc /* --------------------------------------------- - * int console_core_flush(uintptr_t base_addr) - * DEPRECATED: Not used with MULTI_CONSOLE_API! + * int console_16550_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address @@ -231,8 +232,36 @@ endfunc console_16550_getc * Clobber list : x0, x1 * --------------------------------------------- */ -func console_core_flush - /* Placeholder */ +func console_16550_core_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + + /* Loop until the transmit FIFO is empty */ +1: ldr w1, [x0, #UARTLSR] + and w1, w1, #(UARTLSR_TEMT | UARTLSR_THRE) + cmp w1, #(UARTLSR_TEMT | UARTLSR_THRE) + b.ne 1b + mov w0, #0 ret -endfunc console_core_flush +endfunc console_16550_core_flush + + /* --------------------------------------------- + * int console_16550_flush(console_pl011_t *console) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - pointer to console_t structure + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_16550_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_16550_BASE] + b console_16550_core_flush +endfunc console_16550_flush diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 4ef916f5..09a394dd 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -64,33 +64,41 @@ #include <types.h> #include <utils_def.h> /* To retain compatibility */ + /* * Declarations of linker defined symbols to help determine memory layout of * BL images */ #if SEPARATE_CODE_AND_RODATA -extern uintptr_t __TEXT_START__; -extern uintptr_t __TEXT_END__; -extern uintptr_t __RODATA_START__; -extern uintptr_t __RODATA_END__; +IMPORT_SYM(unsigned long, __TEXT_START__, BL_CODE_BASE); +IMPORT_SYM(unsigned long, __TEXT_END__, BL_CODE_END); +IMPORT_SYM(unsigned long, __RODATA_START__, BL_RO_DATA_BASE); +IMPORT_SYM(unsigned long, __RODATA_END__, BL_RO_DATA_END); #else -extern uintptr_t __RO_START__; -extern uintptr_t __RO_END__; +IMPORT_SYM(unsigned long, __RO_START__, BL_CODE_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL_CODE_END); #endif #if defined(IMAGE_BL2) -extern uintptr_t __BL2_END__; +IMPORT_SYM(unsigned long, __BL2_END__, BL2_END); #elif defined(IMAGE_BL2U) -extern uintptr_t __BL2U_END__; +IMPORT_SYM(unsigned long, __BL2U_END__, BL2U_END); #elif defined(IMAGE_BL31) -extern uintptr_t __BL31_END__; +IMPORT_SYM(unsigned long, __BL31_END__, BL31_END); #elif defined(IMAGE_BL32) -extern uintptr_t __BL32_END__; +IMPORT_SYM(unsigned long, __BL32_END__, BL32_END); #endif /* IMAGE_BLX */ +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ #if USE_COHERENT_MEM -extern uintptr_t __COHERENT_RAM_START__; -extern uintptr_t __COHERENT_RAM_END__; +IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE); +IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL_COHERENT_RAM_END); #endif /******************************************************************************* diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h index 6150b322..5d9fa390 100644 --- a/include/common/runtime_svc.h +++ b/include/common/runtime_svc.h @@ -8,7 +8,7 @@ #define __RUNTIME_SVC_H__ #include <bl_common.h> /* to include exception types */ -#include <smcc_helpers.h> /* to include SMCC definitions */ +#include <smccc_helpers.h> /* to include SMCCC definitions */ /******************************************************************************* @@ -122,8 +122,8 @@ CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \ void runtime_svc_init(void); uintptr_t handle_runtime_svc(uint32_t smc_fid, void *cookie, void *handle, unsigned int flags); -extern uintptr_t __RT_SVC_DESCS_START__; -extern uintptr_t __RT_SVC_DESCS_END__; +IMPORT_SYM(uintptr_t, __RT_SVC_DESCS_START__, RT_SVC_DESCS_START); +IMPORT_SYM(uintptr_t, __RT_SVC_DESCS_END__, RT_SVC_DESCS_END); void init_crash_reporting(void); extern uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; diff --git a/include/drivers/console.h b/include/drivers/console.h index f8ec83d2..c8a43a28 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h @@ -66,6 +66,8 @@ int console_flush(void); /* REMOVED on AArch64 -- use console_<driver>_register() instead! */ int console_init(uintptr_t base_addr, unsigned int uart_clk, unsigned int baud_rate); +int console_core_init(uintptr_t base_addr, + unsigned int uart_clk, unsigned int baud_rate); void console_uninit(void); #endif diff --git a/include/lib/aarch32/smcc_helpers.h b/include/lib/aarch32/smcc_helpers.h index ed3b722f..7f79f8fa 100644 --- a/include/lib/aarch32/smcc_helpers.h +++ b/include/lib/aarch32/smcc_helpers.h @@ -7,159 +7,8 @@ #ifndef __SMCC_HELPERS_H__ #define __SMCC_HELPERS_H__ -#include <smcc.h> +#if !ERROR_DEPRECATED +#include <smccc_helpers.h> +#endif -/* These are offsets to registers in smc_ctx_t */ -#define SMC_CTX_GPREG_R0 0x0 -#define SMC_CTX_GPREG_R1 0x4 -#define SMC_CTX_GPREG_R2 0x8 -#define SMC_CTX_GPREG_R3 0xC -#define SMC_CTX_GPREG_R4 0x10 -#define SMC_CTX_GPREG_R5 0x14 -#define SMC_CTX_SP_USR 0x34 -#define SMC_CTX_SPSR_MON 0x78 -#define SMC_CTX_SP_MON 0x7C -#define SMC_CTX_LR_MON 0x80 -#define SMC_CTX_SCR 0x84 -#define SMC_CTX_PMCR 0x88 -#define SMC_CTX_SIZE 0x90 - -#ifndef __ASSEMBLY__ -#include <cassert.h> -#include <types.h> - -/* - * The generic structure to save arguments and callee saved registers during - * an SMC. Also this structure is used to store the result return values after - * the completion of SMC service. - */ -typedef struct smc_ctx { - u_register_t r0; - u_register_t r1; - u_register_t r2; - u_register_t r3; - u_register_t r4; - u_register_t r5; - u_register_t r6; - u_register_t r7; - u_register_t r8; - u_register_t r9; - u_register_t r10; - u_register_t r11; - u_register_t r12; - /* spsr_usr doesn't exist */ - u_register_t sp_usr; - u_register_t lr_usr; - u_register_t spsr_irq; - u_register_t sp_irq; - u_register_t lr_irq; - u_register_t spsr_fiq; - u_register_t sp_fiq; - u_register_t lr_fiq; - u_register_t spsr_svc; - u_register_t sp_svc; - u_register_t lr_svc; - u_register_t spsr_abt; - u_register_t sp_abt; - u_register_t lr_abt; - u_register_t spsr_und; - u_register_t sp_und; - u_register_t lr_und; - u_register_t spsr_mon; - /* - * `sp_mon` will point to the C runtime stack in monitor mode. But prior - * to exit from SMC, this will point to the `smc_ctx_t` so that - * on next entry due to SMC, the `smc_ctx_t` can be easily accessed. - */ - u_register_t sp_mon; - u_register_t lr_mon; - u_register_t scr; - u_register_t pmcr; - /* - * The workaround for CVE-2017-5715 requires storing information in - * the bottom 3 bits of the stack pointer. Add a padding field to - * force the size of the struct to be a multiple of 8. - */ - u_register_t pad; -} smc_ctx_t __aligned(8); - -/* - * Compile time assertions related to the 'smc_context' structure to - * ensure that the assembler and the compiler view of the offsets of - * the structure members is the same. - */ -CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \ - assert_smc_ctx_greg_r0_offset_mismatch); -CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \ - assert_smc_ctx_greg_r1_offset_mismatch); -CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \ - assert_smc_ctx_greg_r2_offset_mismatch); -CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \ - assert_smc_ctx_greg_r3_offset_mismatch); -CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \ - assert_smc_ctx_greg_r4_offset_mismatch); -CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \ - assert_smc_ctx_sp_usr_offset_mismatch); -CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \ - assert_smc_ctx_lr_mon_offset_mismatch); -CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \ - assert_smc_ctx_spsr_mon_offset_mismatch); - -CASSERT((sizeof(smc_ctx_t) & 0x7) == 0, assert_smc_ctx_not_aligned); -CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch); - -/* Convenience macros to return from SMC handler */ -#define SMC_RET0(_h) { \ - return (uintptr_t)(_h); \ -} -#define SMC_RET1(_h, _r0) { \ - ((smc_ctx_t *)(_h))->r0 = (_r0); \ - SMC_RET0(_h); \ -} -#define SMC_RET2(_h, _r0, _r1) { \ - ((smc_ctx_t *)(_h))->r1 = (_r1); \ - SMC_RET1(_h, (_r0)); \ -} -#define SMC_RET3(_h, _r0, _r1, _r2) { \ - ((smc_ctx_t *)(_h))->r2 = (_r2); \ - SMC_RET2(_h, (_r0), (_r1)); \ -} -#define SMC_RET4(_h, _r0, _r1, _r2, _r3) { \ - ((smc_ctx_t *)(_h))->r3 = (_r3); \ - SMC_RET3(_h, (_r0), (_r1), (_r2)); \ -} - -/* Return a UUID in the SMC return registers */ -#define SMC_UUID_RET(_h, _uuid) \ - SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ - ((const uint32_t *) &(_uuid))[1], \ - ((const uint32_t *) &(_uuid))[2], \ - ((const uint32_t *) &(_uuid))[3]) - -/* - * Helper macro to retrieve the SMC parameters from smc_ctx_t. - */ -#define get_smc_params_from_ctx(_hdl, _r1, _r2, _r3, _r4) { \ - _r1 = ((smc_ctx_t *)_hdl)->r1; \ - _r2 = ((smc_ctx_t *)_hdl)->r2; \ - _r3 = ((smc_ctx_t *)_hdl)->r3; \ - _r4 = ((smc_ctx_t *)_hdl)->r4; \ - } - -/* ------------------------------------------------------------------------ - * Helper APIs for setting and retrieving appropriate `smc_ctx_t`. - * These functions need to implemented by the BL including this library. - * ------------------------------------------------------------------------ - */ - -/* Get the pointer to `smc_ctx_t` corresponding to the security state. */ -void *smc_get_ctx(unsigned int security_state); - -/* Set the next `smc_ctx_t` corresponding to the security state. */ -void smc_set_next_ctx(unsigned int security_state); - -/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */ -void *smc_get_next_ctx(void); - -#endif /*__ASSEMBLY__*/ #endif /* __SMCC_HELPERS_H__ */ diff --git a/include/lib/aarch32/smcc_macros.S b/include/lib/aarch32/smcc_macros.S index 93f211f7..66f3d0ea 100644 --- a/include/lib/aarch32/smcc_macros.S +++ b/include/lib/aarch32/smcc_macros.S @@ -1,199 +1,15 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef __SMCC_MACROS_S__ #define __SMCC_MACROS_S__ -#include <arch.h> +#if !ERROR_DEPRECATED +#include <smccc_macros.S> -/* - * Macro to save the General purpose registers (r0 - r12), the banked - * spsr, lr, sp registers and the `scr` register to the SMC context on entry - * due a SMC call. The `lr` of the current mode (monitor) is expected to be - * already saved. The `sp` must point to the `smc_ctx_t` to save to. - * Additionally, also save the 'pmcr' register as this is updated whilst - * executing in the secure world. - */ - .macro smcc_save_gp_mode_regs - /* Save r0 - r12 in the SMC context */ - stm sp, {r0-r12} - mov r0, sp - add r0, r0, #SMC_CTX_SP_USR - -#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) - /* Must be in secure state to restore Monitor mode */ - ldcopr r4, SCR - bic r2, r4, #SCR_NS_BIT - stcopr r2, SCR - isb - - cps #MODE32_sys - stm r0!, {sp, lr} - - cps #MODE32_irq - mrs r2, spsr - stm r0!, {r2, sp, lr} - - cps #MODE32_fiq - mrs r2, spsr - stm r0!, {r2, sp, lr} - - cps #MODE32_svc - mrs r2, spsr - stm r0!, {r2, sp, lr} - - cps #MODE32_abt - mrs r2, spsr - stm r0!, {r2, sp, lr} - - cps #MODE32_und - mrs r2, spsr - stm r0!, {r2, sp, lr} - - /* lr_mon is already saved by caller */ - cps #MODE32_mon - mrs r2, spsr - stm r0!, {r2} - - stcopr r4, SCR - isb -#else - /* Save the banked registers including the current SPSR and LR */ - mrs r4, sp_usr - mrs r5, lr_usr - mrs r6, spsr_irq - mrs r7, sp_irq - mrs r8, lr_irq - mrs r9, spsr_fiq - mrs r10, sp_fiq - mrs r11, lr_fiq - mrs r12, spsr_svc - stm r0!, {r4-r12} - - mrs r4, sp_svc - mrs r5, lr_svc - mrs r6, spsr_abt - mrs r7, sp_abt - mrs r8, lr_abt - mrs r9, spsr_und - mrs r10, sp_und - mrs r11, lr_und - mrs r12, spsr - stm r0!, {r4-r12} - /* lr_mon is already saved by caller */ - - ldcopr r4, SCR -#endif - str r4, [sp, #SMC_CTX_SCR] - ldcopr r4, PMCR - str r4, [sp, #SMC_CTX_PMCR] - .endm - -/* - * Macro to restore the `smc_ctx_t`, which includes the General purpose - * registers and banked mode registers, and exit from the monitor mode. - * r0 must point to the `smc_ctx_t` to restore from. - */ - .macro monitor_exit - /* - * Save the current sp and restore the smc context - * pointer to sp which will be used for handling the - * next SMC. - */ - str sp, [r0, #SMC_CTX_SP_MON] - mov sp, r0 - - /* - * Restore SCR first so that we access the right banked register - * when the other mode registers are restored. - */ - ldr r1, [r0, #SMC_CTX_SCR] - stcopr r1, SCR - isb - - /* - * Restore the PMCR register. - */ - ldr r1, [r0, #SMC_CTX_PMCR] - stcopr r1, PMCR - - /* Restore the banked registers including the current SPSR */ - add r1, r0, #SMC_CTX_SP_USR - -#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) - /* Must be in secure state to restore Monitor mode */ - ldcopr r4, SCR - bic r2, r4, #SCR_NS_BIT - stcopr r2, SCR - isb - - cps #MODE32_sys - ldm r1!, {sp, lr} - - cps #MODE32_irq - ldm r1!, {r2, sp, lr} - msr spsr_fsxc, r2 - - cps #MODE32_fiq - ldm r1!, {r2, sp, lr} - msr spsr_fsxc, r2 - - cps #MODE32_svc - ldm r1!, {r2, sp, lr} - msr spsr_fsxc, r2 - - cps #MODE32_abt - ldm r1!, {r2, sp, lr} - msr spsr_fsxc, r2 - - cps #MODE32_und - ldm r1!, {r2, sp, lr} - msr spsr_fsxc, r2 - - cps #MODE32_mon - ldm r1!, {r2} - msr spsr_fsxc, r2 - - stcopr r4, SCR - isb -#else - ldm r1!, {r4-r12} - msr sp_usr, r4 - msr lr_usr, r5 - msr spsr_irq, r6 - msr sp_irq, r7 - msr lr_irq, r8 - msr spsr_fiq, r9 - msr sp_fiq, r10 - msr lr_fiq, r11 - msr spsr_svc, r12 - - ldm r1!, {r4-r12} - msr sp_svc, r4 - msr lr_svc, r5 - msr spsr_abt, r6 - msr sp_abt, r7 - msr lr_abt, r8 - msr spsr_und, r9 - msr sp_und, r10 - msr lr_und, r11 - /* - * Use the `_fsxc` suffix explicitly to instruct the assembler - * to update all the 32 bits of SPSR. Else, by default, the - * assembler assumes `_fc` suffix which only modifies - * f->[31:24] and c->[7:0] bits of SPSR. - */ - msr spsr_fsxc, r12 +#define smcc_save_gp_mode_regs smccc_save_gp_mode_regs #endif - /* Restore the LR */ - ldr lr, [r0, #SMC_CTX_LR_MON] - - /* Restore the rest of the general purpose registers */ - ldm r0, {r0-r12} - eret - .endm - #endif /* __SMCC_MACROS_S__ */ diff --git a/include/lib/aarch32/smccc_helpers.h b/include/lib/aarch32/smccc_helpers.h new file mode 100644 index 00000000..240dd13f --- /dev/null +++ b/include/lib/aarch32/smccc_helpers.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SMCCC_HELPERS_H__ +#define __SMCCC_HELPERS_H__ + +#include <smccc.h> + +/* These are offsets to registers in smc_ctx_t */ +#define SMC_CTX_GPREG_R0 0x0 +#define SMC_CTX_GPREG_R1 0x4 +#define SMC_CTX_GPREG_R2 0x8 +#define SMC_CTX_GPREG_R3 0xC +#define SMC_CTX_GPREG_R4 0x10 +#define SMC_CTX_GPREG_R5 0x14 +#define SMC_CTX_SP_USR 0x34 +#define SMC_CTX_SPSR_MON 0x78 +#define SMC_CTX_SP_MON 0x7C +#define SMC_CTX_LR_MON 0x80 +#define SMC_CTX_SCR 0x84 +#define SMC_CTX_PMCR 0x88 +#define SMC_CTX_SIZE 0x90 + +#ifndef __ASSEMBLY__ +#include <cassert.h> +#include <types.h> + +/* + * The generic structure to save arguments and callee saved registers during + * an SMC. Also this structure is used to store the result return values after + * the completion of SMC service. + */ +typedef struct smc_ctx { + u_register_t r0; + u_register_t r1; + u_register_t r2; + u_register_t r3; + u_register_t r4; + u_register_t r5; + u_register_t r6; + u_register_t r7; + u_register_t r8; + u_register_t r9; + u_register_t r10; + u_register_t r11; + u_register_t r12; + /* spsr_usr doesn't exist */ + u_register_t sp_usr; + u_register_t lr_usr; + u_register_t spsr_irq; + u_register_t sp_irq; + u_register_t lr_irq; + u_register_t spsr_fiq; + u_register_t sp_fiq; + u_register_t lr_fiq; + u_register_t spsr_svc; + u_register_t sp_svc; + u_register_t lr_svc; + u_register_t spsr_abt; + u_register_t sp_abt; + u_register_t lr_abt; + u_register_t spsr_und; + u_register_t sp_und; + u_register_t lr_und; + u_register_t spsr_mon; + /* + * `sp_mon` will point to the C runtime stack in monitor mode. But prior + * to exit from SMC, this will point to the `smc_ctx_t` so that + * on next entry due to SMC, the `smc_ctx_t` can be easily accessed. + */ + u_register_t sp_mon; + u_register_t lr_mon; + u_register_t scr; + u_register_t pmcr; + /* + * The workaround for CVE-2017-5715 requires storing information in + * the bottom 3 bits of the stack pointer. Add a padding field to + * force the size of the struct to be a multiple of 8. + */ + u_register_t pad; +} smc_ctx_t __aligned(8); + +/* + * Compile time assertions related to the 'smc_context' structure to + * ensure that the assembler and the compiler view of the offsets of + * the structure members is the same. + */ +CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \ + assert_smc_ctx_greg_r0_offset_mismatch); +CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \ + assert_smc_ctx_greg_r1_offset_mismatch); +CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \ + assert_smc_ctx_greg_r2_offset_mismatch); +CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \ + assert_smc_ctx_greg_r3_offset_mismatch); +CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \ + assert_smc_ctx_greg_r4_offset_mismatch); +CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \ + assert_smc_ctx_sp_usr_offset_mismatch); +CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \ + assert_smc_ctx_lr_mon_offset_mismatch); +CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \ + assert_smc_ctx_spsr_mon_offset_mismatch); + +CASSERT((sizeof(smc_ctx_t) & 0x7) == 0, assert_smc_ctx_not_aligned); +CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch); + +/* Convenience macros to return from SMC handler */ +#define SMC_RET0(_h) { \ + return (uintptr_t)(_h); \ +} +#define SMC_RET1(_h, _r0) { \ + ((smc_ctx_t *)(_h))->r0 = (_r0); \ + SMC_RET0(_h); \ +} +#define SMC_RET2(_h, _r0, _r1) { \ + ((smc_ctx_t *)(_h))->r1 = (_r1); \ + SMC_RET1(_h, (_r0)); \ +} +#define SMC_RET3(_h, _r0, _r1, _r2) { \ + ((smc_ctx_t *)(_h))->r2 = (_r2); \ + SMC_RET2(_h, (_r0), (_r1)); \ +} +#define SMC_RET4(_h, _r0, _r1, _r2, _r3) { \ + ((smc_ctx_t *)(_h))->r3 = (_r3); \ + SMC_RET3(_h, (_r0), (_r1), (_r2)); \ +} + +/* Return a UUID in the SMC return registers */ +#define SMC_UUID_RET(_h, _uuid) \ + SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ + ((const uint32_t *) &(_uuid))[1], \ + ((const uint32_t *) &(_uuid))[2], \ + ((const uint32_t *) &(_uuid))[3]) + +/* + * Helper macro to retrieve the SMC parameters from smc_ctx_t. + */ +#define get_smc_params_from_ctx(_hdl, _r1, _r2, _r3, _r4) { \ + _r1 = ((smc_ctx_t *)_hdl)->r1; \ + _r2 = ((smc_ctx_t *)_hdl)->r2; \ + _r3 = ((smc_ctx_t *)_hdl)->r3; \ + _r4 = ((smc_ctx_t *)_hdl)->r4; \ + } + +/* ------------------------------------------------------------------------ + * Helper APIs for setting and retrieving appropriate `smc_ctx_t`. + * These functions need to implemented by the BL including this library. + * ------------------------------------------------------------------------ + */ + +/* Get the pointer to `smc_ctx_t` corresponding to the security state. */ +void *smc_get_ctx(unsigned int security_state); + +/* Set the next `smc_ctx_t` corresponding to the security state. */ +void smc_set_next_ctx(unsigned int security_state); + +/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */ +void *smc_get_next_ctx(void); + +#endif /*__ASSEMBLY__*/ + +#endif /* __SMCCC_HELPERS_H__ */ diff --git a/include/lib/aarch32/smccc_macros.S b/include/lib/aarch32/smccc_macros.S new file mode 100644 index 00000000..fdb65e80 --- /dev/null +++ b/include/lib/aarch32/smccc_macros.S @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __SMCCC_MACROS_S__ +#define __SMCCC_MACROS_S__ + +#include <arch.h> + +/* + * Macro to save the General purpose registers (r0 - r12), the banked + * spsr, lr, sp registers and the `scr` register to the SMC context on entry + * due a SMC call. The `lr` of the current mode (monitor) is expected to be + * already saved. The `sp` must point to the `smc_ctx_t` to save to. + * Additionally, also save the 'pmcr' register as this is updated whilst + * executing in the secure world. + */ + .macro smccc_save_gp_mode_regs + /* Save r0 - r12 in the SMC context */ + stm sp, {r0-r12} + mov r0, sp + add r0, r0, #SMC_CTX_SP_USR + +#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) + /* Must be in secure state to restore Monitor mode */ + ldcopr r4, SCR + bic r2, r4, #SCR_NS_BIT + stcopr r2, SCR + isb + + cps #MODE32_sys + stm r0!, {sp, lr} + + cps #MODE32_irq + mrs r2, spsr + stm r0!, {r2, sp, lr} + + cps #MODE32_fiq + mrs r2, spsr + stm r0!, {r2, sp, lr} + + cps #MODE32_svc + mrs r2, spsr + stm r0!, {r2, sp, lr} + + cps #MODE32_abt + mrs r2, spsr + stm r0!, {r2, sp, lr} + + cps #MODE32_und + mrs r2, spsr + stm r0!, {r2, sp, lr} + + /* lr_mon is already saved by caller */ + cps #MODE32_mon + mrs r2, spsr + stm r0!, {r2} + + stcopr r4, SCR + isb +#else + /* Save the banked registers including the current SPSR and LR */ + mrs r4, sp_usr + mrs r5, lr_usr + mrs r6, spsr_irq + mrs r7, sp_irq + mrs r8, lr_irq + mrs r9, spsr_fiq + mrs r10, sp_fiq + mrs r11, lr_fiq + mrs r12, spsr_svc + stm r0!, {r4-r12} + + mrs r4, sp_svc + mrs r5, lr_svc + mrs r6, spsr_abt + mrs r7, sp_abt + mrs r8, lr_abt + mrs r9, spsr_und + mrs r10, sp_und + mrs r11, lr_und + mrs r12, spsr + stm r0!, {r4-r12} + /* lr_mon is already saved by caller */ + + ldcopr r4, SCR +#endif + str r4, [sp, #SMC_CTX_SCR] + ldcopr r4, PMCR + str r4, [sp, #SMC_CTX_PMCR] + .endm + +/* + * Macro to restore the `smc_ctx_t`, which includes the General purpose + * registers and banked mode registers, and exit from the monitor mode. + * r0 must point to the `smc_ctx_t` to restore from. + */ + .macro monitor_exit + /* + * Save the current sp and restore the smc context + * pointer to sp which will be used for handling the + * next SMC. + */ + str sp, [r0, #SMC_CTX_SP_MON] + mov sp, r0 + + /* + * Restore SCR first so that we access the right banked register + * when the other mode registers are restored. + */ + ldr r1, [r0, #SMC_CTX_SCR] + stcopr r1, SCR + isb + + /* + * Restore the PMCR register. + */ + ldr r1, [r0, #SMC_CTX_PMCR] + stcopr r1, PMCR + + /* Restore the banked registers including the current SPSR */ + add r1, r0, #SMC_CTX_SP_USR + +#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) + /* Must be in secure state to restore Monitor mode */ + ldcopr r4, SCR + bic r2, r4, #SCR_NS_BIT + stcopr r2, SCR + isb + + cps #MODE32_sys + ldm r1!, {sp, lr} + + cps #MODE32_irq + ldm r1!, {r2, sp, lr} + msr spsr_fsxc, r2 + + cps #MODE32_fiq + ldm r1!, {r2, sp, lr} + msr spsr_fsxc, r2 + + cps #MODE32_svc + ldm r1!, {r2, sp, lr} + msr spsr_fsxc, r2 + + cps #MODE32_abt + ldm r1!, {r2, sp, lr} + msr spsr_fsxc, r2 + + cps #MODE32_und + ldm r1!, {r2, sp, lr} + msr spsr_fsxc, r2 + + cps #MODE32_mon + ldm r1!, {r2} + msr spsr_fsxc, r2 + + stcopr r4, SCR + isb +#else + ldm r1!, {r4-r12} + msr sp_usr, r4 + msr lr_usr, r5 + msr spsr_irq, r6 + msr sp_irq, r7 + msr lr_irq, r8 + msr spsr_fiq, r9 + msr sp_fiq, r10 + msr lr_fiq, r11 + msr spsr_svc, r12 + + ldm r1!, {r4-r12} + msr sp_svc, r4 + msr lr_svc, r5 + msr spsr_abt, r6 + msr sp_abt, r7 + msr lr_abt, r8 + msr spsr_und, r9 + msr sp_und, r10 + msr lr_und, r11 + /* + * Use the `_fsxc` suffix explicitly to instruct the assembler + * to update all the 32 bits of SPSR. Else, by default, the + * assembler assumes `_fc` suffix which only modifies + * f->[31:24] and c->[7:0] bits of SPSR. + */ + msr spsr_fsxc, r12 +#endif + + /* Restore the LR */ + ldr lr, [r0, #SMC_CTX_LR_MON] + + /* Restore the rest of the general purpose registers */ + ldm r0, {r0-r12} + eret + .endm + +#endif /* __SMCCC_MACROS_S__ */ diff --git a/include/lib/aarch64/smcc_helpers.h b/include/lib/aarch64/smcc_helpers.h index 62294d04..11300b7e 100644 --- a/include/lib/aarch64/smcc_helpers.h +++ b/include/lib/aarch64/smcc_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,84 +7,8 @@ #ifndef __SMCC_HELPERS_H__ #define __SMCC_HELPERS_H__ -#include <smcc.h> +#if !ERROR_DEPRECATED +#include <smccc_helpers.h> +#endif -#ifndef __ASSEMBLY__ -#include <context.h> - -/* Convenience macros to return from SMC handler */ -#define SMC_RET0(_h) { \ - return (uint64_t) (_h); \ -} -#define SMC_RET1(_h, _x0) { \ - write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \ - SMC_RET0(_h); \ -} -#define SMC_RET2(_h, _x0, _x1) { \ - write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \ - SMC_RET1(_h, (_x0)); \ -} -#define SMC_RET3(_h, _x0, _x1, _x2) { \ - write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \ - SMC_RET2(_h, (_x0), (_x1)); \ -} -#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ - write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \ - SMC_RET3(_h, (_x0), (_x1), (_x2)); \ -} -#define SMC_RET5(_h, _x0, _x1, _x2, _x3, _x4) { \ - write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \ - SMC_RET4(_h, (_x0), (_x1), (_x2), (_x3)); \ -} -#define SMC_RET6(_h, _x0, _x1, _x2, _x3, _x4, _x5) { \ - write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \ - SMC_RET5(_h, (_x0), (_x1), (_x2), (_x3), (_x4)); \ -} -#define SMC_RET7(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6) { \ - write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \ - SMC_RET6(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5)); \ -} -#define SMC_RET8(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7) { \ - write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \ - SMC_RET7(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6)); \ -} - -/* - * Convenience macros to access general purpose registers using handle provided - * to SMC handler. These take the offset values defined in context.h - */ -#define SMC_GET_GP(_h, _g) \ - read_ctx_reg((get_gpregs_ctx(_h)), (_g)) -#define SMC_SET_GP(_h, _g, _v) \ - write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v)) - -/* - * Convenience macros to access EL3 context registers using handle provided to - * SMC handler. These take the offset values defined in context.h - */ -#define SMC_GET_EL3(_h, _e) \ - read_ctx_reg((get_el3state_ctx(_h)), (_e)) -#define SMC_SET_EL3(_h, _e, _v) \ - write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v)) - -/* Return a UUID in the SMC return registers */ -#define SMC_UUID_RET(_h, _uuid) \ - SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ - ((const uint32_t *) &(_uuid))[1], \ - ((const uint32_t *) &(_uuid))[2], \ - ((const uint32_t *) &(_uuid))[3]) - -/* - * Helper macro to retrieve the SMC parameters from cpu_context_t. - */ -#define get_smc_params_from_ctx(_hdl, _x1, _x2, _x3, _x4) \ - do { \ - const gp_regs_t *regs = get_gpregs_ctx(_hdl); \ - _x1 = read_ctx_reg(regs, CTX_GPREG_X1); \ - _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \ - _x3 = read_ctx_reg(regs, CTX_GPREG_X3); \ - _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \ - } while (0) - -#endif /*__ASSEMBLY__*/ #endif /* __SMCC_HELPERS_H__ */ diff --git a/include/lib/aarch64/smccc_helpers.h b/include/lib/aarch64/smccc_helpers.h new file mode 100644 index 00000000..1b33a0d1 --- /dev/null +++ b/include/lib/aarch64/smccc_helpers.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SMCCC_HELPERS_H__ +#define __SMCCC_HELPERS_H__ + +#include <smccc.h> + +#ifndef __ASSEMBLY__ +#include <context.h> + +/* Convenience macros to return from SMC handler */ +#define SMC_RET0(_h) { \ + return (uint64_t) (_h); \ +} +#define SMC_RET1(_h, _x0) { \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \ + SMC_RET0(_h); \ +} +#define SMC_RET2(_h, _x0, _x1) { \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \ + SMC_RET1(_h, (_x0)); \ +} +#define SMC_RET3(_h, _x0, _x1, _x2) { \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \ + SMC_RET2(_h, (_x0), (_x1)); \ +} +#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \ + SMC_RET3(_h, (_x0), (_x1), (_x2)); \ +} +#define SMC_RET5(_h, _x0, _x1, _x2, _x3, _x4) { \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \ + SMC_RET4(_h, (_x0), (_x1), (_x2), (_x3)); \ +} +#define SMC_RET6(_h, _x0, _x1, _x2, _x3, _x4, _x5) { \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \ + SMC_RET5(_h, (_x0), (_x1), (_x2), (_x3), (_x4)); \ +} +#define SMC_RET7(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6) { \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \ + SMC_RET6(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5)); \ +} +#define SMC_RET8(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7) { \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \ + SMC_RET7(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6)); \ +} + +/* + * Convenience macros to access general purpose registers using handle provided + * to SMC handler. These take the offset values defined in context.h + */ +#define SMC_GET_GP(_h, _g) \ + read_ctx_reg((get_gpregs_ctx(_h)), (_g)) +#define SMC_SET_GP(_h, _g, _v) \ + write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v)) + +/* + * Convenience macros to access EL3 context registers using handle provided to + * SMC handler. These take the offset values defined in context.h + */ +#define SMC_GET_EL3(_h, _e) \ + read_ctx_reg((get_el3state_ctx(_h)), (_e)) +#define SMC_SET_EL3(_h, _e, _v) \ + write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v)) + +/* Return a UUID in the SMC return registers */ +#define SMC_UUID_RET(_h, _uuid) \ + SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ + ((const uint32_t *) &(_uuid))[1], \ + ((const uint32_t *) &(_uuid))[2], \ + ((const uint32_t *) &(_uuid))[3]) + +/* + * Helper macro to retrieve the SMC parameters from cpu_context_t. + */ +#define get_smc_params_from_ctx(_hdl, _x1, _x2, _x3, _x4) \ + do { \ + const gp_regs_t *regs = get_gpregs_ctx(_hdl); \ + _x1 = read_ctx_reg(regs, CTX_GPREG_X1); \ + _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \ + _x3 = read_ctx_reg(regs, CTX_GPREG_X3); \ + _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \ + } while (0) + +#endif /*__ASSEMBLY__*/ + +#endif /* __SMCCC_HELPERS_H__ */ diff --git a/include/lib/smcc.h b/include/lib/smcc.h index 0a2d9277..ed1da2cf 100644 --- a/include/lib/smcc.h +++ b/include/lib/smcc.h @@ -7,103 +7,8 @@ #ifndef __SMCC_H__ #define __SMCC_H__ -#include <utils_def.h> - -/******************************************************************************* - * Bit definitions inside the function id as per the SMC calling convention - ******************************************************************************/ -#define FUNCID_TYPE_SHIFT U(31) -#define FUNCID_CC_SHIFT U(30) -#define FUNCID_OEN_SHIFT U(24) -#define FUNCID_NUM_SHIFT U(0) - -#define FUNCID_TYPE_MASK U(0x1) -#define FUNCID_CC_MASK U(0x1) -#define FUNCID_OEN_MASK U(0x3f) -#define FUNCID_NUM_MASK U(0xffff) - -#define FUNCID_TYPE_WIDTH U(1) -#define FUNCID_CC_WIDTH U(1) -#define FUNCID_OEN_WIDTH U(6) -#define FUNCID_NUM_WIDTH U(16) - -#define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ - FUNCID_CC_MASK) -#define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \ - FUNCID_TYPE_MASK) - -#define SMC_64 U(1) -#define SMC_32 U(0) -#define SMC_OK U(0) -#define SMC_UNK -1 -#define SMC_TYPE_FAST ULL(1) #if !ERROR_DEPRECATED -#define SMC_TYPE_STD ULL(0) +#include <smccc.h> #endif -#define SMC_TYPE_YIELD U(0) -#define SMC_PREEMPTED -2 -/******************************************************************************* - * Owning entity number definitions inside the function id as per the SMC - * calling convention - ******************************************************************************/ -#define OEN_ARM_START U(0) -#define OEN_ARM_END U(0) -#define OEN_CPU_START U(1) -#define OEN_CPU_END U(1) -#define OEN_SIP_START U(2) -#define OEN_SIP_END U(2) -#define OEN_OEM_START U(3) -#define OEN_OEM_END U(3) -#define OEN_STD_START U(4) /* Standard Service Calls */ -#define OEN_STD_END U(4) -#define OEN_TAP_START U(48) /* Trusted Applications */ -#define OEN_TAP_END U(49) -#define OEN_TOS_START U(50) /* Trusted OS */ -#define OEN_TOS_END U(63) -#define OEN_LIMIT U(64) - -#ifndef __ASSEMBLY__ - -#include <cassert.h> -#include <stdint.h> - -#define SMCCC_MAJOR_VERSION U(1) -#define SMCCC_MINOR_VERSION U(1) - -#define MAKE_SMCCC_VERSION(_major, _minor) (((_major) << 16) | (_minor)) - -/* Various flags passed to SMC handlers */ -#define SMC_FROM_SECURE (U(0) << 0) -#define SMC_FROM_NON_SECURE (U(1) << 0) - -#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) -#define is_caller_secure(_f) (!(is_caller_non_secure(_f))) - -/* The macro below is used to identify a Standard Service SMC call */ -#define is_std_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \ - FUNCID_OEN_MASK) == OEN_STD_START) - -/* The macro below is used to identify a Arm Architectural Service SMC call */ -#define is_arm_arch_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \ - FUNCID_OEN_MASK) == OEN_ARM_START) - -/* The macro below is used to identify a valid Fast SMC call */ -#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \ - (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) - -/* - * Macro to define UUID for services. Apart from defining and initializing a - * uuid_t structure, this macro verifies that the first word of the defined UUID - * does not equal SMC_UNK. This is to ensure that the caller won't mistake the - * returned UUID in x0 for an invalid SMC error return - */ -#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \ - _n0, _n1, _n2, _n3, _n4, _n5) \ - CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\ - static const uuid_t _name = { \ - _tl, _tm, _th, _cl, _ch, \ - { _n0, _n1, _n2, _n3, _n4, _n5 } \ - } -#endif /*__ASSEMBLY__*/ #endif /* __SMCC_H__ */ diff --git a/include/lib/smccc.h b/include/lib/smccc.h new file mode 100644 index 00000000..d6834203 --- /dev/null +++ b/include/lib/smccc.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SMCCC_H__ +#define __SMCCC_H__ + +#include <utils_def.h> + +/******************************************************************************* + * Bit definitions inside the function id as per the SMC calling convention + ******************************************************************************/ +#define FUNCID_TYPE_SHIFT U(31) +#define FUNCID_CC_SHIFT U(30) +#define FUNCID_OEN_SHIFT U(24) +#define FUNCID_NUM_SHIFT U(0) + +#define FUNCID_TYPE_MASK U(0x1) +#define FUNCID_CC_MASK U(0x1) +#define FUNCID_OEN_MASK U(0x3f) +#define FUNCID_NUM_MASK U(0xffff) + +#define FUNCID_TYPE_WIDTH U(1) +#define FUNCID_CC_WIDTH U(1) +#define FUNCID_OEN_WIDTH U(6) +#define FUNCID_NUM_WIDTH U(16) + +#define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ + FUNCID_CC_MASK) +#define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \ + FUNCID_TYPE_MASK) + +#define SMC_64 U(1) +#define SMC_32 U(0) +#define SMC_OK U(0) +#define SMC_UNK -1 +#define SMC_TYPE_FAST ULL(1) +#if !ERROR_DEPRECATED +#define SMC_TYPE_STD ULL(0) +#endif +#define SMC_TYPE_YIELD U(0) +#define SMC_PREEMPTED -2 +/******************************************************************************* + * Owning entity number definitions inside the function id as per the SMC + * calling convention + ******************************************************************************/ +#define OEN_ARM_START U(0) +#define OEN_ARM_END U(0) +#define OEN_CPU_START U(1) +#define OEN_CPU_END U(1) +#define OEN_SIP_START U(2) +#define OEN_SIP_END U(2) +#define OEN_OEM_START U(3) +#define OEN_OEM_END U(3) +#define OEN_STD_START U(4) /* Standard Service Calls */ +#define OEN_STD_END U(4) +#define OEN_TAP_START U(48) /* Trusted Applications */ +#define OEN_TAP_END U(49) +#define OEN_TOS_START U(50) /* Trusted OS */ +#define OEN_TOS_END U(63) +#define OEN_LIMIT U(64) + +#ifndef __ASSEMBLY__ + +#include <cassert.h> +#include <stdint.h> + +#define SMCCC_MAJOR_VERSION U(1) +#define SMCCC_MINOR_VERSION U(1) + +#define MAKE_SMCCC_VERSION(_major, _minor) (((_major) << 16) | (_minor)) + +/* Various flags passed to SMC handlers */ +#define SMC_FROM_SECURE (U(0) << 0) +#define SMC_FROM_NON_SECURE (U(1) << 0) + +#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) +#define is_caller_secure(_f) (!(is_caller_non_secure(_f))) + +/* The macro below is used to identify a Standard Service SMC call */ +#define is_std_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \ + FUNCID_OEN_MASK) == OEN_STD_START) + +/* The macro below is used to identify a Arm Architectural Service SMC call */ +#define is_arm_arch_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \ + FUNCID_OEN_MASK) == OEN_ARM_START) + +/* The macro below is used to identify a valid Fast SMC call */ +#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \ + (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) + +/* + * Macro to define UUID for services. Apart from defining and initializing a + * uuid_t structure, this macro verifies that the first word of the defined UUID + * does not equal SMC_UNK. This is to ensure that the caller won't mistake the + * returned UUID in x0 for an invalid SMC error return + */ +#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \ + _n0, _n1, _n2, _n3, _n4, _n5) \ + CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\ + static const uuid_t _name = { \ + _tl, _tm, _th, _cl, _ch, \ + { _n0, _n1, _n2, _n3, _n4, _n5 } \ + } + +#endif /*__ASSEMBLY__*/ +#endif /* __SMCCC_H__ */ diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 4a5c3e0b..8abc73c0 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -99,4 +99,21 @@ ((ARM_ARCH_MAJOR > _maj) || \ ((ARM_ARCH_MAJOR == _maj) && (ARM_ARCH_MINOR >= _min))) +/* + * Import an assembly or linker symbol as a C expression with the specified + * type + */ +#define IMPORT_SYM(type, sym, name) \ + extern char sym[];\ + static const __attribute__((unused)) type name = (type) sym; + +/* + * When the symbol is used to hold a pointer, its alignment can be asserted + * with this macro. For example, if there is a linker symbol that is going to + * be used as a 64-bit pointer, the value of the linker symbol must also be + * aligned to 64 bit. This macro makes sure this is the case. + */ +#define ASSERT_SYM_PTR_ALIGN(sym) assert(((size_t)(sym) % __alignof__(*(sym))) == 0) + + #endif /* __UTILS_DEF_H__ */ diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h index a841c3db..84923b9a 100644 --- a/include/plat/common/common_def.h +++ b/include/plat/common/common_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,33 +74,13 @@ * page of it with the right memory attributes. */ #if SEPARATE_CODE_AND_RODATA -#define BL_CODE_BASE (unsigned long)(&__TEXT_START__) -#define BL_CODE_END (unsigned long)(&__TEXT_END__) -#define BL_RO_DATA_BASE (unsigned long)(&__RODATA_START__) -#define BL_RO_DATA_END (unsigned long)(&__RODATA_END__) #define BL1_CODE_END BL_CODE_END -#define BL1_RO_DATA_BASE (unsigned long)(&__RODATA_START__) +#define BL1_RO_DATA_BASE BL_RO_DATA_BASE #define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE) #else -#define BL_CODE_BASE (unsigned long)(&__RO_START__) -#define BL_CODE_END (unsigned long)(&__RO_END__) #define BL_RO_DATA_BASE 0 #define BL_RO_DATA_END 0 - #define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE) -#define BL1_RO_DATA_BASE 0 -#define BL1_RO_DATA_END 0 #endif /* SEPARATE_CODE_AND_RODATA */ - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL_COHERENT_RAM_END (unsigned long)(&__COHERENT_RAM_END__) - #endif /* __COMMON_DEF_H__ */ diff --git a/include/services/secure_partition.h b/include/services/secure_partition.h index 93df2a13..f68f711b 100644 --- a/include/services/secure_partition.h +++ b/include/services/secure_partition.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,15 +11,11 @@ #include <types.h> #include <utils_def.h> -/* Linker symbols */ -extern uintptr_t __SP_IMAGE_XLAT_TABLES_START__; -extern uintptr_t __SP_IMAGE_XLAT_TABLES_END__; +/* Import linker symbols */ +IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_START__, SP_IMAGE_XLAT_TABLES_START); +IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_END__, SP_IMAGE_XLAT_TABLES_END); /* Definitions */ -#define SP_IMAGE_XLAT_TABLES_START \ - (uintptr_t)(&__SP_IMAGE_XLAT_TABLES_START__) -#define SP_IMAGE_XLAT_TABLES_END \ - (uintptr_t)(&__SP_IMAGE_XLAT_TABLES_END__) #define SP_IMAGE_XLAT_TABLES_SIZE \ (SP_IMAGE_XLAT_TABLES_END - SP_IMAGE_XLAT_TABLES_START) diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index 76e440e3..c784c225 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,7 @@ #include <context_mgmt.h> #include <platform.h> #include <platform_def.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> #include <string.h> #include <utils.h> diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index c6c2249a..2608d1fc 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,7 +15,7 @@ #include <platform.h> #include <platform_def.h> #include <pubsub_events.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> #include <spe.h> #include <string.h> #include <sve.h> diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c index 8f59215e..37697f52 100644 --- a/lib/locks/bakery/bakery_lock_normal.c +++ b/lib/locks/bakery/bakery_lock_normal.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <cpu_data.h> #include <platform.h> #include <string.h> +#include <utils_def.h> /* * Functions in this file implement Bakery Algorithm for mutual exclusion with the @@ -49,8 +50,7 @@ CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \ * Use the linker defined symbol which has evaluated the size reqiurement. * This is not as efficient as using a platform defined constant */ -extern void *__PERCPU_BAKERY_LOCK_SIZE__; -#define PERCPU_BAKERY_LOCK_SIZE ((uintptr_t)&__PERCPU_BAKERY_LOCK_SIZE__) +IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE); #endif #define get_bakery_info(cpu_ix, lock) \ diff --git a/lib/pmf/pmf_main.c b/lib/pmf/pmf_main.c index 2cf260ec..0208948f 100644 --- a/lib/pmf/pmf_main.c +++ b/lib/pmf/pmf_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #include <platform.h> #include <pmf.h> #include <string.h> +#include <utils_def.h> /******************************************************************************* * The 'pmf_svc_descs' array holds the PMF service descriptors exported by @@ -21,16 +22,12 @@ * index of the descriptor in the 'pmf_svc_descs' array which contains the * service function pointers. ******************************************************************************/ -extern uintptr_t __PMF_SVC_DESCS_START__; -extern uintptr_t __PMF_SVC_DESCS_END__; -#define PMF_SVC_DESCS_START ((uintptr_t)(&__PMF_SVC_DESCS_START__)) -#define PMF_SVC_DESCS_END ((uintptr_t)(&__PMF_SVC_DESCS_END__)) -extern void *__PERCPU_TIMESTAMP_SIZE__; -#define PMF_PERCPU_TIMESTAMP_SIZE ((uintptr_t)&__PERCPU_TIMESTAMP_SIZE__) -extern uintptr_t __PMF_TIMESTAMP_START__; -#define PMF_TIMESTAMP_ARRAY_START ((uintptr_t)&__PMF_TIMESTAMP_START__) -extern uintptr_t __PMF_TIMESTAMP_END__; -#define PMF_TIMESTAMP_ARRAY_END ((uintptr_t)&__PMF_TIMESTAMP_END__) + +IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_START__, PMF_SVC_DESCS_START); +IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_END__, PMF_SVC_DESCS_END); +IMPORT_SYM(uintptr_t, __PERCPU_TIMESTAMP_SIZE__, PMF_PERCPU_TIMESTAMP_SIZE); +IMPORT_SYM(intptr_t, __PMF_TIMESTAMP_START__, PMF_TIMESTAMP_ARRAY_START); +IMPORT_SYM(uintptr_t, __PMF_TIMESTAMP_END__, PMF_TIMESTAMP_ARRAY_END); #define PMF_SVC_DESCS_MAX 10 diff --git a/lib/pmf/pmf_smc.c b/lib/pmf/pmf_smc.c index 248c1fac..5cf193e2 100644 --- a/lib/pmf/pmf_smc.c +++ b/lib/pmf/pmf_smc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #include <debug.h> #include <platform.h> #include <pmf.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> /* * This function is responsible for handling all PMF SMC calls. diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index 88cf5cbe..d25d1775 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c @@ -12,7 +12,7 @@ #include <platform.h> #include <pmf.h> #include <runtime_instr.h> -#include <smcc.h> +#include <smccc.h> #include <string.h> #include "psci_private.h" diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c index 3e79c5d7..e925d34e 100644 --- a/lib/psci/psci_stat.c +++ b/lib/psci/psci_stat.c @@ -24,7 +24,8 @@ typedef struct psci_stat { * Following is used to keep track of the last cpu * that goes to power down in non cpu power domains. */ -static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {-1}; +static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = { + [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS-1] = -1}; /* * Following are used to store PSCI STAT values for @@ -129,6 +130,10 @@ void psci_stats_update_pwr_up(unsigned int end_pwrlvl, * prior to this CPU powering on. */ parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + /* Return early if this is the first power up. */ + if (last_cpu_in_non_cpu_pd[parent_idx] == -1) + return; + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { local_state = state_info->pwr_domain_state[lvl]; if (is_local_state_run(local_state)) { diff --git a/lib/stdlib/puts.c b/lib/stdlib/puts.c index 693a6bff..284cf8c5 100644 --- a/lib/stdlib/puts.c +++ b/lib/stdlib/puts.c @@ -9,23 +9,17 @@ int puts(const char *s) { int count = 0; - while(*s) - { - if (putchar(*s++) != EOF) { - count++; - } else { - count = EOF; - break; - } + while(*s) { + if (putchar(*s++) == EOF) + return EOF; + count++; } /* According to the puts(3) manpage, the function should write a * trailing newline. */ - if ((count != EOF) && (putchar('\n') != EOF)) - count++; - else - count = EOF; + if (putchar('\n') == EOF) + return EOF; - return count; + return count + 1; } diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index a8650be0..cac9dfc4 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -199,7 +199,7 @@ $(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) $(eval DEP := $(patsubst %.o,%.d,$(OBJ))) $(eval IMAGE := IMAGE_BL$(call uppercase,$(3))) -$(OBJ): $(2) | bl$(3)_dirs +$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs @echo " CC $$<" $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@ @@ -218,7 +218,7 @@ $(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2)))) $(eval DEP := $(patsubst %.o,%.d,$(OBJ))) $(eval IMAGE := IMAGE_BL$(call uppercase,$(3))) -$(OBJ): $(2) | bl$(3)_dirs +$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs @echo " AS $$<" $$(Q)$$(AS) $$(ASFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@ @@ -235,7 +235,7 @@ define MAKE_LD $(eval DEP := $(1).d) -$(1): $(2) | bl$(3)_dirs +$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs @echo " PP $$<" $$(Q)$$(CPP) $$(CPPFLAGS) -P -D__ASSEMBLY__ -D__LINKER__ $(MAKE_DEP) -o $$@ $$< @@ -374,7 +374,7 @@ define MAKE_DTB $(eval DOBJ := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2)))) $(eval DEP := $(patsubst %.dtb,%.d,$(DOBJ))) -$(DOBJ): $(2) | fdt_dirs +$(DOBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | fdt_dirs @echo " DTC $$<" $$(Q)$$(DTC) $$(DTC_FLAGS) -d $(DEP) -o $$@ $$< diff --git a/make_helpers/plat_helpers.mk b/make_helpers/plat_helpers.mk index a2f383a5..a7ae9a27 100644 --- a/make_helpers/plat_helpers.mk +++ b/make_helpers/plat_helpers.mk @@ -15,14 +15,14 @@ ifndef PLAT_HELPERS_MK $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform") endif - # PLATFORM_ROOT can be overridden for when building tools directly - PLATFORM_ROOT ?= plat/ + # TF_PLATFORM_ROOT can be overridden for when building tools directly + TF_PLATFORM_ROOT ?= plat/ PLAT_MAKEFILE := platform.mk # Generate the platforms list by recursively searching for all directories # under /plat containing a PLAT_MAKEFILE. Append each platform with a `|` # char and strip out the final '|'. - ALL_PLATFORM_MK_FILES := $(call rwildcard,${PLATFORM_ROOT},${PLAT_MAKEFILE}) + ALL_PLATFORM_MK_FILES := $(call rwildcard,${TF_PLATFORM_ROOT},${PLAT_MAKEFILE}) ALL_PLATFORM_DIRS := $(patsubst %/,%,$(dir ${ALL_PLATFORM_MK_FILES})) ALL_PLATFORMS := $(sort $(notdir ${ALL_PLATFORM_DIRS})) diff --git a/plat/arm/board/fvp/aarch64/fvp_helpers.S b/plat/arm/board/fvp/aarch64/fvp_helpers.S index 6ea45851..88fcdb1b 100644 --- a/plat/arm/board/fvp/aarch64/fvp_helpers.S +++ b/plat/arm/board/fvp/aarch64/fvp_helpers.S @@ -178,19 +178,22 @@ func plat_is_my_cpu_primary ret endfunc plat_is_my_cpu_primary - /* ----------------------------------------------------- + /* --------------------------------------------------------------------- * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) * * Function to calculate the core position on FVP. * - * (ClusterId * FVP_MAX_CPUS_PER_CLUSTER) + + * (ClusterId * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) + * (CPUId * FVP_MAX_PE_PER_CPU) + * ThreadId - * ----------------------------------------------------- + * + * which can be simplified as: + * + * ((ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU) + * + ThreadId + * --------------------------------------------------------------------- */ func plat_arm_calc_core_pos - mov x3, x0 - /* * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it * look as if in a multi-threaded implementation. @@ -205,9 +208,9 @@ func plat_arm_calc_core_pos ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS /* Compute linear position */ - mov x4, #FVP_MAX_PE_PER_CPU - madd x0, x1, x4, x0 - mov x5, #FVP_MAX_CPUS_PER_CLUSTER - madd x0, x2, x5, x0 + mov x4, #FVP_MAX_CPUS_PER_CLUSTER + madd x1, x2, x4, x1 + mov x5, #FVP_MAX_PE_PER_CPU + madd x0, x1, x5, x0 ret endfunc plat_arm_calc_core_pos diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/execution_state_switch.c index 8499db07..22d552ad 100644 --- a/plat/arm/common/execution_state_switch.c +++ b/plat/arm/common/execution_state_switch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ #include <context_mgmt.h> #include <plat_arm.h> #include <psci.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> #include <string.h> #include <utils.h> diff --git a/plat/hisilicon/hikey/aarch64/hikey_common.c b/plat/hisilicon/hikey/aarch64/hikey_common.c index f95af587..658760b5 100644 --- a/plat/hisilicon/hikey/aarch64/hikey_common.c +++ b/plat/hisilicon/hikey/aarch64/hikey_common.c @@ -9,13 +9,12 @@ #include <assert.h> #include <bl_common.h> #include <debug.h> +#include <hikey_def.h> +#include <hikey_layout.h> #include <mmio.h> #include <platform.h> -#include <platform_def.h> #include <xlat_tables.h> -#include "../hikey_def.h" - #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \ DDR_SIZE - DDR_SEC_SIZE, \ MT_DEVICE | MT_RW | MT_NS) diff --git a/plat/hisilicon/hikey/aarch64/hikey_helpers.S b/plat/hisilicon/hikey/aarch64/hikey_helpers.S index 680c0a1d..32ff8b40 100644 --- a/plat/hisilicon/hikey/aarch64/hikey_helpers.S +++ b/plat/hisilicon/hikey/aarch64/hikey_helpers.S @@ -1,12 +1,12 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch.h> #include <asm_macros.S> -#include "../hikey_def.h" +#include <hikey_def.h> .globl plat_my_core_pos .globl platform_mem_init diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c index 69b194a5..28ad9df2 100644 --- a/plat/hisilicon/hikey/hikey_bl1_setup.c +++ b/plat/hisilicon/hikey/hikey_bl1_setup.c @@ -13,33 +13,16 @@ #include <emmc.h> #include <errno.h> #include <hi6220.h> +#include <hikey_def.h> +#include <hikey_layout.h> #include <mmio.h> #include <platform.h> -#include <platform_def.h> #include <string.h> #include <tbbr/tbbr_img_desc.h> #include "../../bl1/bl1_private.h" -#include "hikey_def.h" #include "hikey_private.h" -/* - * Declarations of linker defined symbols which will help us find the layout - * of trusted RAM - */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) - /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -103,8 +86,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } /* diff --git a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c index 7c025c34..23c16ed9 100644 --- a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c +++ b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c @@ -7,7 +7,7 @@ #include <bl_common.h> #include <desc_image_load.h> #include <platform.h> -#include <platform_def.h> +#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ /******************************************************************************* diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index 20bb7527..8bb28248 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -21,10 +21,9 @@ #include <optee_utils.h> #endif #include <platform.h> -#include <platform_def.h> +#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ #include <string.h> -#include "hikey_def.h" #include "hikey_private.h" /* diff --git a/plat/hisilicon/hikey/hikey_bl31_setup.c b/plat/hisilicon/hikey/hikey_bl31_setup.c index e13ecf67..a193b5a7 100644 --- a/plat/hisilicon/hikey/hikey_bl31_setup.c +++ b/plat/hisilicon/hikey/hikey_bl31_setup.c @@ -14,12 +14,12 @@ #include <errno.h> #include <gicv2.h> #include <hi6220.h> +#include <hikey_def.h> #include <hisi_ipc.h> #include <hisi_pwrc.h> #include <mmio.h> #include <platform_def.h> -#include "hikey_def.h" #include "hikey_private.h" /* diff --git a/plat/hisilicon/hikey/hikey_pm.c b/plat/hisilicon/hikey/hikey_pm.c index d4dd683e..3128a3d1 100644 --- a/plat/hisilicon/hikey/hikey_pm.c +++ b/plat/hisilicon/hikey/hikey_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <debug.h> #include <gicv2.h> #include <hi6220.h> +#include <hikey_def.h> #include <hisi_ipc.h> #include <hisi_pwrc.h> #include <hisi_sram_map.h> @@ -17,8 +18,6 @@ #include <psci.h> #include <sp804_delay_timer.h> -#include "hikey_def.h" - #define CORE_PWR_STATE(state) \ ((state)->pwr_domain_state[MPIDR_AFFLVL0]) #define CLUSTER_PWR_STATE(state) \ diff --git a/plat/hisilicon/hikey/hikey_def.h b/plat/hisilicon/hikey/include/hikey_def.h index 668b4592..deb375da 100644 --- a/plat/hisilicon/hikey/hikey_def.h +++ b/plat/hisilicon/hikey/include/hikey_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,9 +7,6 @@ #ifndef __HIKEY_DEF_H__ #define __HIKEY_DEF_H__ -#include <common_def.h> -#include <tbbr_img_def.h> - /* Always assume DDR is 1GB size. */ #define DDR_BASE 0x0 #define DDR_SIZE 0x40000000 @@ -17,9 +14,6 @@ #define DEVICE_BASE 0xF4000000 #define DEVICE_SIZE 0x05800000 -#define XG2RAM0_BASE 0xF9800000 -#define XG2RAM0_SIZE 0x00400000 - /* Memory location options for TSP */ #define HIKEY_SRAM_ID 0 #define HIKEY_DRAM_ID 1 @@ -43,13 +37,6 @@ #define SRAM_SIZE 0x00012000 /* - * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). - */ -#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) -#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) -#define BL1_XG2RAM0_OFFSET 0x1000 - -/* * PL011 related constants */ #define PL011_UART0_BASE 0xF8015000 diff --git a/plat/hisilicon/hikey/include/hikey_layout.h b/plat/hisilicon/hikey/include/hikey_layout.h new file mode 100644 index 00000000..637a1c9b --- /dev/null +++ b/plat/hisilicon/hikey/include/hikey_layout.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HIKEY_LAYOUT_H +#define __HIKEY_LAYOUT_H + +/* + * Platform memory map related constants + */ +#define XG2RAM0_BASE 0xF9800000 +#define XG2RAM0_SIZE 0x00400000 + +/* + * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). + */ +#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) +#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) +#define BL1_XG2RAM0_OFFSET 0x1000 + +/* + * BL1 specific defines. + * + * Both loader and BL1_RO region stay in SRAM since they are used to simulate + * ROM. + * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. + * + * ++++++++++ 0xF980_0000 + * + loader + + * ++++++++++ 0xF980_1000 + * + BL1_RO + + * ++++++++++ 0xF981_0000 + * + BL1_RW + + * ++++++++++ 0xF989_8000 + */ +#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) +#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) +#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ +#define BL1_RW_SIZE (0x00088000) +#define BL1_RW_LIMIT (0xF9898000) + +/* + * Non-Secure BL1U specific defines. + */ +#define NS_BL1U_BASE (0xf9818000) +#define NS_BL1U_SIZE (0x00010000) +#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) + +/* + * BL2 specific defines. + * + * Both loader and BL2 region stay in SRAM. + * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. + * + * ++++++++++ 0xF980_0000 + * + loader + + * ++++++++++ 0xF980_1000 + * + BL2 + + * ++++++++++ 0xF981_8000 + */ +#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ +#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */ + +/* + * SCP_BL2 specific defines. + * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer + * at 0x0100_0000. Then BL2 will parse the sections and loaded them into + * predefined separated buffers. + */ +#define SCP_BL2_BASE (DDR_BASE + 0x01000000) +#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) +#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) + +/* + * BL31 specific defines. + */ +#define BL31_BASE (0xF9858000) /* 0xf985_8000 */ +#define BL31_LIMIT (0xF9898000) + +/* + * BL3-2 specific defines. + */ + +/* + * The TSP currently executes from TZC secured area of DRAM or SRAM. + */ +#define BL32_SRAM_BASE BL31_LIMIT +#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ + +#define BL32_DRAM_BASE DDR_SEC_BASE +#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) + +#ifdef SPD_opteed +/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ +#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ +#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ +#endif + +#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) +#define TSP_SEC_MEM_BASE BL32_DRAM_BASE +#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) +#define BL32_BASE BL32_DRAM_BASE +#define BL32_LIMIT BL32_DRAM_LIMIT +#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) +#define TSP_SEC_MEM_BASE BL32_SRAM_BASE +#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) +#define BL32_BASE BL32_SRAM_BASE +#define BL32_LIMIT BL32_SRAM_LIMIT +#else +#error "Currently unsupported HIKEY_TSP_LOCATION_ID value" +#endif + +/* BL32 is mandatory in AArch32 */ +#ifndef AARCH32 +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ +#endif + +#endif /* !__HIKEY_LAYOUT_H */ diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h index 9b4f4631..8c560047 100644 --- a/plat/hisilicon/hikey/include/platform_def.h +++ b/plat/hisilicon/hikey/include/platform_def.h @@ -8,7 +8,10 @@ #define __PLATFORM_DEF_H__ #include <arch.h> -#include "../hikey_def.h" +#include <common_def.h> +#include <hikey_def.h> +#include <hikey_layout.h> /* BL memory region sizes, etc */ +#include <tbbr_img_def.h> /* Special value used to verify platform parameters from BL2 to BL3-1 */ #define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL @@ -27,7 +30,7 @@ #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_CORE_COUNT_PER_CLUSTER) -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 +#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ PLATFORM_CLUSTER_COUNT + 1) @@ -45,114 +48,6 @@ #define PLAT_ARM_GICH_BASE 0xF6804000 #define PLAT_ARM_GICV_BASE 0xF6806000 - -/* - * Platform memory map related constants - */ - -/* - * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). - */ -#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) -#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) -#define BL1_XG2RAM0_OFFSET 0x1000 - -/* - * BL1 specific defines. - * - * Both loader and BL1_RO region stay in SRAM since they are used to simulate - * ROM. - * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. - * - * ++++++++++ 0xF980_0000 - * + loader + - * ++++++++++ 0xF980_1000 - * + BL1_RO + - * ++++++++++ 0xF981_0000 - * + BL1_RW + - * ++++++++++ 0xF989_8000 - */ -#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) -#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) -#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ -#define BL1_RW_SIZE (0x00088000) -#define BL1_RW_LIMIT (0xF9898000) - -/* - * BL2 specific defines. - * - * Both loader and BL2 region stay in SRAM. - * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. - * - * ++++++++++ 0xF980_0000 - * + loader + - * ++++++++++ 0xF980_1000 - * + BL2 + - * ++++++++++ 0xF981_8000 - */ -#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ -#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */ - -/* - * SCP_BL2 specific defines. - * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer - * at 0x0100_0000. Then BL2 will parse the sections and loaded them into - * predefined separated buffers. - */ -#define SCP_BL2_BASE (DDR_BASE + 0x01000000) -#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) -#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) - -/* - * BL31 specific defines. - */ -#define BL31_BASE (0xF9858000) /* 0xf985_8000 */ -#define BL31_LIMIT (0xF9898000) - -/* - * BL3-2 specific defines. - */ - -/* - * The TSP currently executes from TZC secured area of DRAM or SRAM. - */ -#define BL32_SRAM_BASE BL31_LIMIT -#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ - -#define BL32_DRAM_BASE DDR_SEC_BASE -#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) - -#ifdef SPD_opteed -/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ -#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ -#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ -#endif - -#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) -#define TSP_SEC_MEM_BASE BL32_DRAM_BASE -#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) -#define BL32_BASE BL32_DRAM_BASE -#define BL32_LIMIT BL32_DRAM_LIMIT -#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) -#define TSP_SEC_MEM_BASE BL32_SRAM_BASE -#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) -#define BL32_BASE BL32_SRAM_BASE -#define BL32_LIMIT BL32_SRAM_LIMIT -#else -#error "Currently unsupported HIKEY_TSP_LOCATION_ID value" -#endif - -/* BL32 is mandatory in AArch32 */ -#ifndef AARCH32 -#ifdef SPD_none -#undef BL32_BASE -#endif /* SPD_none */ -#endif - -#define NS_BL1U_BASE (0xf9818000) -#define NS_BL1U_SIZE (0x00010000) -#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) - /* * Platform specific page table and MMU setup constants */ @@ -172,8 +67,6 @@ #define MAX_MMAP_REGIONS 16 -#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000) - /* * Declarations and constants to access the mailboxes safely. Each mailbox is * aligned on the biggest cache line size in the platform. This is known only diff --git a/plat/hisilicon/hikey960/hikey960_bl1_setup.c b/plat/hisilicon/hikey960/hikey960_bl1_setup.c index 9cadba0b..6a07f092 100644 --- a/plat/hisilicon/hikey960/hikey960_bl1_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl1_setup.c @@ -37,18 +37,6 @@ enum { * Declarations of linker defined symbols which will help us find the layout * of trusted RAM */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to - * page-aligned addresses. - */ -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -131,8 +119,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } static void hikey960_ufs_reset(void) diff --git a/plat/hisilicon/hikey960/hikey960_pm.c b/plat/hisilicon/hikey960/hikey960_pm.c index 22963c4f..ffe7fcf8 100644 --- a/plat/hisilicon/hikey960/hikey960_pm.c +++ b/plat/hisilicon/hikey960/hikey960_pm.c @@ -9,6 +9,7 @@ #include <cci.h> #include <console.h> #include <debug.h> +#include <delay_timer.h> #include <gicv2.h> #include <hi3660.h> #include <hi3660_crg.h> @@ -114,6 +115,9 @@ void hikey960_pwr_domain_off(const psci_power_state_t *target_state) static void __dead2 hikey960_system_reset(void) { + dsb(); + isb(); + mdelay(2000); mmio_write_32(SCTRL_SCPEREN1_REG, SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS); mmio_write_32(SCTRL_SCSYSSTAT_REG, 0xdeadbeef); diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c index 39551135..25eed593 100644 --- a/plat/hisilicon/poplar/bl1_plat_setup.c +++ b/plat/hisilicon/poplar/bl1_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,13 +23,6 @@ #include "hi3798cv200.h" #include "plat_private.h" -/* Symbols from link script for conherent section */ -extern unsigned long __COHERENT_RAM_START__; -extern unsigned long __COHERENT_RAM_END__; - -#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) - /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -92,8 +85,8 @@ void bl1_plat_arch_setup(void) bl1_tzram_layout.total_size, BL1_RO_BASE, /* l-loader and BL1 ROM */ BL1_RO_LIMIT, - BL1_COHERENT_RAM_BASE, - BL1_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } void bl1_platform_setup(void) diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c index 803f1ed8..32f01572 100644 --- a/plat/mediatek/mt6795/bl31_plat_setup.c +++ b/plat/mediatek/mt6795/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,22 +21,21 @@ #include <plat_private.h> #include <platform.h> #include <string.h> +#include <utils_def.h> #include <xlat_tables.h> + /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); /* * Placeholder variables for copying the arguments that have been passed to diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index 7b293077..e51bdbb9 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,24 +17,6 @@ #include <platform.h> #include <spm.h> -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted SRAM - ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL31 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) -#define BL31_END (unsigned long)(&__BL31_END__) - static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; @@ -156,10 +138,10 @@ void bl31_plat_arch_setup(void) plat_cci_init(); plat_cci_enable(); - plat_configure_mmu_el3(BL31_RO_BASE, - BL_COHERENT_RAM_END - BL31_RO_BASE, - BL31_RO_BASE, - BL31_RO_LIMIT, + plat_configure_mmu_el3(BL_CODE_BASE, + BL_COHERENT_RAM_END - BL_CODE_BASE, + BL_CODE_BASE, + BL_CODE_END, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); } diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index d89ad7b9..2fe4e7db 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,6 +23,7 @@ #include <string.h> #include <tegra_def.h> #include <tegra_private.h> +#include <utils_def.h> /* length of Trusty's input parameters (in bytes) */ #define TRUSTY_PARAMS_LEN_BYTES (4096*2) @@ -33,29 +34,17 @@ extern void zeromem16(void *mem, unsigned int length); * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ -extern unsigned long __TEXT_START__; -extern unsigned long __TEXT_END__; -extern unsigned long __RW_START__; -extern unsigned long __RW_END__; -extern unsigned long __RODATA_START__; -extern unsigned long __RODATA_END__; -extern unsigned long __BL31_END__; + +IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); +IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); +IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE); +IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END); +IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START); +IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END); extern uint64_t tegra_bl31_phys_base; extern uint64_t tegra_console_base; -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL3-1 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RW_START (unsigned long)(&__RW_START__) -#define BL31_RW_END (unsigned long)(&__RW_END__) -#define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__) -#define BL31_RODATA_END (unsigned long)(&__RODATA_END__) -#define BL31_END (unsigned long)(&__BL31_END__) static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { @@ -311,8 +300,8 @@ void bl31_plat_arch_setup(void) unsigned long rw_size = BL31_RW_END - BL31_RW_START; unsigned long rodata_start = BL31_RODATA_BASE; unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; - unsigned long code_base = (unsigned long)(&__TEXT_START__); - unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base; + unsigned long code_base = TEXT_START; + unsigned long code_size = TEXT_END - TEXT_START; const mmap_region_t *plat_mmio_map = NULL; #if USE_COHERENT_MEM unsigned long coh_start, coh_size; diff --git a/plat/nvidia/tegra/soc/t186/plat_smmu.c b/plat/nvidia/tegra/soc/t186/plat_smmu.c index 4a8e1bee..ead4c22b 100644 --- a/plat/nvidia/tegra/soc/t186/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t186/plat_smmu.c @@ -1,23 +1,7 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. + * SPDX-License-Identifier: BSD-3-Clause */ #include <bl_common.h> diff --git a/plat/qemu/aarch64/plat_helpers.S b/plat/qemu/aarch64/plat_helpers.S index ed553795..ca5eec62 100644 --- a/plat/qemu/aarch64/plat_helpers.S +++ b/plat/qemu/aarch64/plat_helpers.S @@ -14,12 +14,13 @@ .globl platform_mem_init .globl plat_qemu_calc_core_pos .globl plat_crash_console_init +#if MULTI_CONSOLE_API .globl plat_crash_console_putc +#endif /* MULTI_CONSOLE_API */ .globl plat_secondary_cold_boot_setup .globl plat_get_my_entrypoint .globl plat_is_my_cpu_primary - func plat_my_core_pos mrs x0, mpidr_el1 b plat_qemu_calc_core_pos @@ -96,10 +97,7 @@ endfunc platform_mem_init * --------------------------------------------- */ func plat_crash_console_init - mov_imm x0, PLAT_QEMU_CRASH_UART_BASE - mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ - mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE - b console_core_init + b qemu_crash_console_init endfunc plat_crash_console_init /* --------------------------------------------- @@ -109,9 +107,10 @@ endfunc plat_crash_console_init * Clobber list : x1, x2 * --------------------------------------------- */ +#if !MULTI_CONSOLE_API func plat_crash_console_putc mov_imm x1, PLAT_QEMU_CRASH_UART_BASE b console_core_putc endfunc plat_crash_console_putc - +#endif /* MULTI_CONSOLE_API */ diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk index e11f5042..379ab3dc 100644 --- a/plat/qemu/platform.mk +++ b/plat/qemu/platform.mk @@ -47,8 +47,9 @@ $(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1)) $(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1)) -PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \ - drivers/arm/pl011/${ARCH}/pl011_console.S +PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \ + plat/qemu/qemu_console.c \ + drivers/arm/pl011/${ARCH}/pl011_console.S \ ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1) PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \ @@ -173,6 +174,12 @@ ifneq ($(ENABLE_STACK_PROTECTOR), 0) PLAT_BL_COMMON_SOURCES += plat/qemu/qemu_stack_protector.c endif +# Use MULTI_CONSOLE_API by default only on AArch64 +# as it is not yet supported on AArch32 +ifeq ($(ARCH),aarch64) +MULTI_CONSOLE_API := 1 +endif + # Disable the PSCI platform compatibility layer ENABLE_PLAT_COMPAT := 0 diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c index 3f617e24..556aae59 100644 --- a/plat/qemu/qemu_bl1_setup.c +++ b/plat/qemu/qemu_bl1_setup.c @@ -8,7 +8,6 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> -#include <console.h> #include <platform_def.h> #include "qemu_private.h" @@ -27,8 +26,7 @@ meminfo_t *bl1_plat_sec_mem_layout(void) void bl1_early_platform_setup(void) { /* Initialize the console to provide early debug support */ - console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, - PLAT_QEMU_CONSOLE_BAUDRATE); + qemu_console_init(); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = BL_RAM_BASE; diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c index 987c6028..7650873e 100644 --- a/plat/qemu/qemu_bl2_setup.c +++ b/plat/qemu/qemu_bl2_setup.c @@ -6,7 +6,6 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> -#include <console.h> #include <debug.h> #include <desc_image_load.h> #include <optee_utils.h> @@ -123,8 +122,7 @@ struct entry_point_info *bl2_plat_get_bl31_ep_info(void) void bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ - console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, - PLAT_QEMU_CONSOLE_BAUDRATE); + qemu_console_init(); /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c index 6ded9295..1e8b2ecb 100644 --- a/plat/qemu/qemu_bl31_setup.c +++ b/plat/qemu/qemu_bl31_setup.c @@ -6,7 +6,6 @@ #include <assert.h> #include <bl_common.h> -#include <console.h> #include <gic_common.h> #include <gicv2.h> #include <platform_def.h> @@ -45,8 +44,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, #endif { /* Initialize the console to provide early debug support */ - console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, - PLAT_QEMU_CONSOLE_BAUDRATE); + qemu_console_init(); #if LOAD_IMAGE_V2 /* diff --git a/plat/qemu/qemu_console.c b/plat/qemu/qemu_console.c new file mode 100644 index 00000000..1cf84aa7 --- /dev/null +++ b/plat/qemu/qemu_console.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <console.h> +#include <pl011.h> +#include <platform_def.h> + +#if MULTI_CONSOLE_API +static console_pl011_t console; +static console_pl011_t crash_console; +#endif /* MULTI_CONSOLE_API */ + +void qemu_console_init(void) +{ +#if MULTI_CONSOLE_API + (void)console_pl011_register(PLAT_QEMU_BOOT_UART_BASE, + PLAT_QEMU_BOOT_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE, &console); +#else + console_init(PLAT_QEMU_BOOT_UART_BASE, + PLAT_QEMU_BOOT_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE); +#endif /* MULTI_CONSOLE_API */ +} + +void qemu_crash_console_init(void) +{ +#if MULTI_CONSOLE_API + (void)console_pl011_register(PLAT_QEMU_CRASH_UART_BASE, + PLAT_QEMU_CRASH_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE, &crash_console); +#else + console_core_init(PLAT_QEMU_CRASH_UART_BASE, + PLAT_QEMU_CRASH_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE); +#endif /* MULTI_CONSOLE_API */ +} diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h index 716440fb..c66d0f9c 100644 --- a/plat/qemu/qemu_private.h +++ b/plat/qemu/qemu_private.h @@ -34,4 +34,7 @@ unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); int dt_add_psci_node(void *fdt); int dt_add_psci_cpu_enable_methods(void *fdt); +void qemu_console_init(void); +void qemu_crash_console_init(void); + #endif /*__QEMU_PRIVATE_H*/ diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 6199edae..e5ee68f1 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,21 +17,14 @@ #include <platform_def.h> #include <uart_16550.h> -/******************************************************************************* - * Declarations of linker defined symbols which will help us find the layout - * of trusted SRAM - ******************************************************************************/ -unsigned long __RO_START__; -unsigned long __RO_END__; - /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); +IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; diff --git a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c index d0e59861..f1a5e2b7 100644 --- a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c +++ b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <cdn_dp.h> -#include <smcc.h> +#include <smccc.h> #include <stdlib.h> #include <string.h> diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index f4893efe..caea7a72 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -1319,10 +1319,14 @@ void wdt_register_restore(void) { int i; - for (i = 0; i < 2; i++) { + for (i = 1; i >= 0; i--) { mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]); mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]); } + + /* write 0x76 to cnt_restart to keep watchdog alive */ + mmio_write_32(WDT0_BASE + 0x0c, 0x76); + mmio_write_32(WDT1_BASE + 0x0c, 0x76); } int rockchip_soc_sys_pwr_dm_suspend(void) @@ -1383,6 +1387,7 @@ int rockchip_soc_sys_pwr_dm_suspend(void) } mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); + wdt_register_save(); secure_watchdog_disable(); /* @@ -1398,7 +1403,6 @@ int rockchip_soc_sys_pwr_dm_suspend(void) suspend_uart(); grf_register_save(); cru_register_save(); - wdt_register_save(); sram_save(); plat_rockchip_save_gpio(); @@ -1411,7 +1415,6 @@ int rockchip_soc_sys_pwr_dm_resume(void) uint32_t status = 0; plat_rockchip_restore_gpio(); - wdt_register_restore(); cru_register_restore(); grf_register_restore(); resume_uart(); @@ -1426,6 +1429,7 @@ int rockchip_soc_sys_pwr_dm_resume(void) secure_watchdog_enable(); secure_sgrf_init(); secure_sgrf_ddr_rgn_init(); + wdt_register_restore(); /* restore clk_ddrc_bpll_src_en gate */ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), diff --git a/plat/rpi3/aarch64/plat_helpers.S b/plat/rpi3/aarch64/plat_helpers.S index 76a542f5..65c1bf2d 100644 --- a/plat/rpi3/aarch64/plat_helpers.S +++ b/plat/rpi3/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -137,7 +137,7 @@ func plat_crash_console_init mov_imm x0, PLAT_RPI3_UART_BASE mov_imm x1, PLAT_RPI3_UART_CLK_IN_HZ mov_imm x2, PLAT_RPI3_UART_BAUDRATE - b console_core_init + b console_16550_core_init endfunc plat_crash_console_init /* --------------------------------------------- @@ -149,7 +149,7 @@ endfunc plat_crash_console_init */ func plat_crash_console_putc mov_imm x1, PLAT_RPI3_UART_BASE - b console_core_putc + b console_16550_core_putc endfunc plat_crash_console_putc /* --------------------------------------------- @@ -161,8 +161,8 @@ endfunc plat_crash_console_putc * --------------------------------------------- */ func plat_crash_console_flush - mov_imm x1, PLAT_RPI3_UART_BASE - b console_core_flush + mov_imm x0, PLAT_RPI3_UART_BASE + b console_16550_core_flush endfunc plat_crash_console_flush /* --------------------------------------------- diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk index e201ceed..2cb7a152 100644 --- a/plat/rpi3/platform.mk +++ b/plat/rpi3/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -81,6 +81,9 @@ USE_COHERENT_MEM := 1 # Enable new version of image loading LOAD_IMAGE_V2 := 1 +# Use multi console API +MULTI_CONSOLE_API := 1 + # Platform build flags # -------------------- @@ -110,6 +113,10 @@ ifneq (${LOAD_IMAGE_V2}, 1) $(error Error: rpi3 needs LOAD_IMAGE_V2=1) endif +ifneq (${MULTI_CONSOLE_API}, 1) + $(error Error: rpi3 needs MULTI_CONSOLE_API=1) +endif + ifeq (${ARCH},aarch32) $(error Error: AArch32 not supported on rpi3) endif diff --git a/plat/rpi3/rpi3_bl1_setup.c b/plat/rpi3/rpi3_bl1_setup.c index 11c0f4af..c98715b9 100644 --- a/plat/rpi3/rpi3_bl1_setup.c +++ b/plat/rpi3/rpi3_bl1_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,6 @@ #include <arch.h> #include <arch_helpers.h> #include <bl_common.h> -#include <console.h> #include <platform_def.h> #include <xlat_mmu_helpers.h> #include <xlat_tables_defs.h> @@ -29,8 +28,7 @@ meminfo_t *bl1_plat_sec_mem_layout(void) void bl1_early_platform_setup(void) { /* Initialize the console to provide early debug support */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); + rpi3_console_init(); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = BL_RAM_BASE; diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c index 1fd822e9..6d43dcea 100644 --- a/plat/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi3/rpi3_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,6 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> -#include <console.h> #include <debug.h> #include <desc_image_load.h> #include <platform_def.h> @@ -27,8 +26,7 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); void bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); + rpi3_console_init(); /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; @@ -40,7 +38,7 @@ void bl2_platform_setup(void) { /* * This is where a TrustZone address space controller and other - * security related peripherals, would be configured. + * security related peripherals would be configured. */ } diff --git a/plat/rpi3/rpi3_bl31_setup.c b/plat/rpi3/rpi3_bl31_setup.c index 39133564..58344ae9 100644 --- a/plat/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi3/rpi3_bl31_setup.c @@ -1,12 +1,11 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> #include <bl_common.h> -#include <console.h> #include <platform.h> #include <platform_def.h> #include <xlat_mmu_helpers.h> @@ -58,8 +57,7 @@ void bl31_early_platform_setup(void *from_bl2, void *plat_params_from_bl2) { /* Initialize the console to provide early debug support */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); + rpi3_console_init(); #if RESET_TO_BL31 @@ -159,10 +157,3 @@ void bl31_platform_setup(void) return; } - -void bl31_plat_runtime_setup(void) -{ - /* Initialize the runtime console */ - console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE); -} diff --git a/plat/rpi3/rpi3_common.c b/plat/rpi3/rpi3_common.c index 97dce091..03914a6d 100644 --- a/plat/rpi3/rpi3_common.c +++ b/plat/rpi3/rpi3_common.c @@ -1,14 +1,16 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch_helpers.h> #include <bl_common.h> +#include <console.h> #include <debug.h> #include <interrupt_mgmt.h> #include <platform_def.h> +#include <uart_16550.h> #include <xlat_tables_v2.h> #include "rpi3_hw.h" @@ -69,6 +71,30 @@ static const mmap_region_t plat_rpi3_mmap[] = { #endif /******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_16550_t rpi3_console; + +void rpi3_console_init(void) +{ + int rc = console_16550_register(PLAT_RPI3_UART_BASE, + PLAT_RPI3_UART_CLK_IN_HZ, + PLAT_RPI3_UART_BAUDRATE, + &rpi3_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&rpi3_console.console, + CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); +} + +/******************************************************************************* * Function that sets up the translation tables. ******************************************************************************/ void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, diff --git a/plat/rpi3/rpi3_private.h b/plat/rpi3/rpi3_private.h index 01c4055f..a9fbfe47 100644 --- a/plat/rpi3/rpi3_private.h +++ b/plat/rpi3/rpi3_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ ******************************************************************************/ /* Utility functions */ +void rpi3_console_init(void); void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, uintptr_t code_start, uintptr_t code_limit, uintptr_t rodata_start, uintptr_t rodata_limit @@ -1,21 +1,24 @@ -Trusted Firmware-A - version 1.4 +Trusted Firmware-A - version 1.5 ================================ Trusted Firmware-A (TF-A) provides a reference implementation of secure world -software for `Armv8-A`_, including a `Secure Monitor`_ executing at Exception -Level 3 (EL3). It implements various Arm interface standards, such as: +software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing +at Exception Level 3 (EL3). It implements various Arm interface standards, +such as: - The `Power State Coordination Interface (PSCI)`_ - Trusted Board Boot Requirements (TBBR, Arm DEN0006C-1) - `SMC Calling Convention`_ - `System Control and Management Interface`_ +- `Software Delegated Exception Interface (SDEI)`_ -As far as possible the code is designed for reuse or porting to other Armv8-A -model and hardware platforms. +Where possible, the code is designed for reuse or porting to other Armv7-A and +Armv8-A model and hardware platforms. Arm will continue development in collaboration with interested parties to provide a full reference implementation of Secure Monitor code and Arm standards -to the benefit of all developers working with Armv8-A TrustZone technology. +to the benefit of all developers working with Armv7-A and Armv8-A TrustZone +technology. License ------- @@ -37,7 +40,10 @@ license text is included in those source files. project under the terms of the NCSA license (also known as the University of Illinois/NCSA Open Source License). -This Release +- The zlib source code is licensed under the Zlib license, which is a + permissive license compatible with BSD-3-Clause. + +This release ------------ This release provides a suitable starting point for productization of secure @@ -93,12 +99,30 @@ Functionality recovery mode), and packaging of the various firmware images into a Firmware Image Package (FIP). -- Pre-integration of TBB with the Arm TrustZone CryptoCell product, to take - advantage of its hardware Root of Trust and crypto acceleration services. +- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of + its hardware Root of Trust and crypto acceleration services. + +- Reliability, Availability, and Serviceability (RAS) functionality, including + + - A Secure Partition Manager (SPM) to manage Secure Partitions in + Secure-EL0, which can be used to implement simple management and + security services. + + - An SDEI dispatcher to route interrupt-based SDEI events. + + - An Exception Handling Framework (EHF) that allows dispatching of EL3 + interrupts to their registered handlers, to facilitate firmware-first + error handling. + +- A dynamic configuration framework that enables each of the firmware images + to be configured at runtime if required by the platform. It also enables + loading of a hardware configuration (for example, a kernel device tree) + as part of the FIP, to be passed through the firmware stages. - Support for alternative boot flows, for example to support platforms where the EL3 Runtime Software is loaded using other firmware or a separate - secure system processor. + secure system processor, or where a non-TF-A ROM expects BL2 to be loaded + at EL3. - Support for the GCC, LLVM and Arm Compiler 6 toolchains. @@ -113,12 +137,13 @@ Various AArch32 and AArch64 builds of this release has been tested on variants r0, r1 and r2 of the `Juno Arm Development Platform`_. Various AArch64 builds of this release have been tested on the following Arm -`FVP`_\ s (64-bit host machine only): +Fixed Virtual Platforms (`FVP`_) without shifted affinities, and that do not +support threaded CPU cores (64-bit host machine only): -NOTE: Unless otherwise stated, the FVP Version is 11.0, Build 11.0.34. +NOTE: Unless otherwise stated, the FVP Version is 11.2 Build 11.2.33. - ``Foundation_Platform`` -- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.5, Build 0.8.8502) +- ``FVP_Base_AEMv8A-AEMv8A`` (and also Version 9.0, Build 0.8.9005) - ``FVP_Base_Cortex-A35x4`` - ``FVP_Base_Cortex-A53x4`` - ``FVP_Base_Cortex-A57x4-A53x4`` @@ -127,44 +152,56 @@ NOTE: Unless otherwise stated, the FVP Version is 11.0, Build 11.0.34. - ``FVP_Base_Cortex-A72x4`` - ``FVP_Base_Cortex-A73x4-A53x4`` - ``FVP_Base_Cortex-A73x4`` -- ``FVP_CSS_SGM-775`` (Version 11.0, Build 11.0.36) + +Additionally, various AArch64 builds were tested on the following Arm `FVP`_ s +with shifted affinities, supporting threaded CPU cores (64-bit host machine +only). + +- ``FVP_Base_Cortex-A55x4-A75x4`` (Version 0.0, build 0.0.4395) +- ``FVP_Base_Cortex-A55x4`` (Version 0.0, build 0.0.4395) +- ``FVP_Base_Cortex-A75x4`` (Version 0.0, build 0.0.4395) +- ``FVP_Base_RevC-2xAEMv8A`` Various AArch32 builds of this release has been tested on the following Arm -`FVP`_\ s (64-bit host machine only): +`FVP`_\ s without shifted affinities, and that do not support threaded CPU cores +(64-bit host machine only): -- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.5, Build 0.8.8502) +- ``FVP_Base_AEMv8A-AEMv8A`` - ``FVP_Base_Cortex-A32x4`` The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from Arm. See the `Arm FVP website`_. -All the above platforms have been tested with `Linaro Release 17.04`_. +All the above platforms have been tested with `Linaro Release 17.10`_. This release also contains the following platform support: -- HiKey and HiKey960 boards +- HiKey, HiKey960 and Poplar boards - MediaTek MT6795 and MT8173 SoCs - NVidia T132, T186 and T210 SoCs - QEMU emulator +- Raspberry Pi 3 board - RockChip RK3328, RK3368 and RK3399 SoCs - Socionext UniPhier SoC family - Xilinx Zynq UltraScale + MPSoC -Still to Come +Still to come ~~~~~~~~~~~~~ - More platform support. +- Improved dynamic configuration support. + - Ongoing support for new architectural features, CPUs and System IP. -- Ongoing support for new `PSCI`_, `SCMI`_ and TBBR features. +- Ongoing support for new Arm system architecture specifications. - Ongoing security hardening, optimization and quality improvements. For a full list of detailed issues in the current code, please see the `Change Log`_ and the `GitHub issue tracker`_. -Getting Started +Getting started --------------- Get the TF-A source code from `GitHub`_. @@ -175,7 +212,7 @@ the TF-A with the Arm `FVP`_\ s. See the `Firmware Design`_ for information on how the TF-A works. See the `Porting Guide`_ as well for information about how to use this -software on another Armv8-A platform. +software on another Armv7-A or Armv8-A platform. See the `Contributing Guidelines`_ for information on how to contribute to this project and the `Acknowledgments`_ file for a list of contributors to the @@ -195,17 +232,19 @@ Arm licensees may contact Arm directly via their partner managers. *Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.* -.. _Armv8-A: http://www.arm.com/products/processors/armv8-architecture.php +.. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile .. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php .. _Power State Coordination Interface (PSCI): PSCI_ .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf .. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf .. _System Control and Management Interface: SCMI_ .. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf +.. _Software Delegated Exception Interface (SDEI): SDEI_ +.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf .. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php .. _Arm FVP website: FVP_ .. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms -.. _Linaro Release 17.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease17.04 +.. _Linaro Release 17.10: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease17.10 .. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os .. _NVidia Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary .. _Trusty Secure OS: https://source.android.com/security/trusty diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c index f75a737e..83d3625f 100644 --- a/services/arm_arch_svc/arm_arch_svc_setup.c +++ b/services/arm_arch_svc/arm_arch_svc_setup.c @@ -8,8 +8,8 @@ #include <debug.h> #include <errata_report.h> #include <runtime_svc.h> -#include <smcc.h> -#include <smcc_helpers.h> +#include <smccc.h> +#include <smccc_helpers.h> #include <workaround_cve_2017_5715.h> static int32_t smccc_version(void) diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c index d6e57267..97f202cb 100644 --- a/services/spd/trusty/trusty.c +++ b/services/spd/trusty/trusty.c @@ -451,7 +451,7 @@ static int32_t trusty_setup(void) uint32_t spsr; ns_ep_info = bl31_plat_get_next_image_ep_info(NON_SECURE); - if (!ep_info) { + if (ns_ep_info == NULL) { NOTICE("Trusty: non-secure image missing.\n"); return -1; } diff --git a/services/std_svc/spm/spm_main.c b/services/std_svc/spm/spm_main.c index d31fad67..6c4e1f0f 100644 --- a/services/std_svc/spm/spm_main.c +++ b/services/std_svc/spm/spm_main.c @@ -14,8 +14,8 @@ #include <platform.h> #include <runtime_svc.h> #include <secure_partition.h> -#include <smcc.h> -#include <smcc_helpers.h> +#include <smccc.h> +#include <smccc_helpers.h> #include <spinlock.h> #include <spm_svc.h> #include <utils.h> diff --git a/services/std_svc/spm/spm_shim_private.h b/services/std_svc/spm/spm_shim_private.h index ad953cde..8408d1e0 100644 --- a/services/std_svc/spm/spm_shim_private.h +++ b/services/std_svc/spm/spm_shim_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,21 +8,17 @@ #define __SPM_SHIM_PRIVATE__ #include <types.h> +#include <utils_def.h> /* Assembly source */ -extern uintptr_t spm_shim_exceptions_ptr; +IMPORT_SYM(uintptr_t, spm_shim_exceptions_ptr, SPM_SHIM_EXCEPTIONS_PTR); /* Linker symbols */ -extern uintptr_t __SPM_SHIM_EXCEPTIONS_START__; -extern uintptr_t __SPM_SHIM_EXCEPTIONS_END__; +IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START); +IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); /* Definitions */ -#define SPM_SHIM_EXCEPTIONS_PTR (uintptr_t)(&spm_shim_exceptions_ptr) -#define SPM_SHIM_EXCEPTIONS_START \ - (uintptr_t)(&__SPM_SHIM_EXCEPTIONS_START__) -#define SPM_SHIM_EXCEPTIONS_END \ - (uintptr_t)(&__SPM_SHIM_EXCEPTIONS_END__) #define SPM_SHIM_EXCEPTIONS_SIZE \ (SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START) diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c index eae078ed..41befe5b 100644 --- a/services/std_svc/std_svc_setup.c +++ b/services/std_svc/std_svc_setup.c @@ -12,7 +12,7 @@ #include <runtime_instr.h> #include <runtime_svc.h> #include <sdei.h> -#include <smcc_helpers.h> +#include <smccc_helpers.h> #include <spm_svc.h> #include <std_svc.h> #include <stdint.h> diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile index 437b6927..b0994b8c 100644 --- a/tools/cert_create/Makefile +++ b/tools/cert_create/Makefile @@ -35,7 +35,7 @@ PLAT_INCLUDE := ../../include/tools_share else PLAT_MSG := ${PLAT} -PLATFORM_ROOT := ../../plat/ +TF_PLATFORM_ROOT := ../../plat/ include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk PLAT_INCLUDE := $(wildcard ${PLAT_DIR}include) |