diff options
162 files changed, 5860 insertions, 3381 deletions
@@ -22,3 +22,9 @@ tools/cert_create/cert_create.exe # Ignore header files copied. tools/fiptool/firmware_image_package.h tools/fiptool/uuid.h + +# GNU GLOBAL files +GPATH +GRTAGS +GSYMS +GTAGS @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -116,7 +116,7 @@ endif # Default build string (git branch and commit) ifeq (${BUILD_STRING},) - BUILD_STRING := $(shell git log -n 1 --pretty=format:"%h") + BUILD_STRING := $(shell git describe --always --dirty --tags 2> /dev/null) endif VERSION_STRING := v${VERSION_MAJOR}.${VERSION_MINOR}(${BUILD_TYPE}):${BUILD_STRING} @@ -154,7 +154,7 @@ ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \ -D__ASSEMBLY__ -ffreestanding \ -Wa,--fatal-warnings TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ - -ffreestanding -Wall -std=c99 -Os \ + -ffreestanding -fno-builtin -Wall -std=c99 -Os \ -ffunction-sections -fdata-sections LDFLAGS += --fatal-warnings -O1 @@ -185,6 +185,7 @@ INCLUDES += -Iinclude/bl1 \ -Iinclude/drivers/ti/uart \ -Iinclude/lib \ -Iinclude/lib/${ARCH} \ + -Iinclude/lib/cpus \ -Iinclude/lib/cpus/${ARCH} \ -Iinclude/lib/el3_runtime \ -Iinclude/lib/el3_runtime/${ARCH} \ @@ -350,9 +351,8 @@ ifneq (${GENERATE_COT},0) endif endif -# Make sure PMF is enabled if PSCI STAT is enabled. -ifeq (${ENABLE_PSCI_STAT},1) -ENABLE_PMF := 1 +ifneq (${FIP_ALIGN},0) +FIP_ARGS += --align ${FIP_ALIGN} endif ################################################################################ @@ -397,6 +397,9 @@ $(eval $(call assert_boolean,SPIN_ON_BL1_EXIT)) $(eval $(call assert_boolean,TRUSTED_BOARD_BOOT)) $(eval $(call assert_boolean,USE_COHERENT_MEM)) +$(eval $(call assert_numeric,ARM_ARCH_MAJOR)) +$(eval $(call assert_numeric,ARM_ARCH_MINOR)) + ################################################################################ # Add definitions to the cpp preprocessor based on the current build options. # This is done after including the platform specific makefile to allow the @@ -404,6 +407,8 @@ $(eval $(call assert_boolean,USE_COHERENT_MEM)) ################################################################################ $(eval $(call add_define,ARM_CCI_PRODUCT_ID)) +$(eval $(call add_define,ARM_ARCH_MAJOR)) +$(eval $(call add_define,ARM_ARCH_MINOR)) $(eval $(call add_define,ARM_GIC_ARCH)) $(eval $(call add_define,ASM_ASSERTION)) $(eval $(call add_define,COLD_BOOT_SINGLE_CPU)) diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index b9554d15..b69065ee 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -133,7 +133,8 @@ SECTIONS /* * The .bss section gets initialised to 0 at runtime. - * Its base address must be 16-byte aligned. + * Its base address should be 16-byte aligned for better performance of the + * zero-initialization code. */ .bss : ALIGN(16) { __BSS_START__ = .; @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -34,6 +34,7 @@ BL1_SOURCES += bl1/bl1_main.c \ bl1/${ARCH}/bl1_entrypoint.S \ bl1/${ARCH}/bl1_exceptions.S \ lib/cpus/${ARCH}/cpu_helpers.S \ + lib/cpus/errata_report.c \ lib/el3_runtime/${ARCH}/context_mgmt.c \ plat/common/plat_bl1_common.c diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index 1cc7daf6..f7fae682 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -335,7 +335,7 @@ static int bl1_fwu_image_auth(unsigned int image_id, */ if (image_desc->state == IMAGE_STATE_COPIED) { /* Clear the memory.*/ - memset((void *)base_addr, 0, total_size); + zero_normalmem((void *)base_addr, total_size); flush_dcache_range(base_addr, total_size); /* Indicate that image can be copied again*/ diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index fbb75e02..90c06afe 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,6 +35,7 @@ #include <bl1.h> #include <bl_common.h> #include <debug.h> +#include <errata_report.h> #include <platform.h> #include <platform_def.h> #include <smcc_helpers.h> @@ -110,6 +111,7 @@ void bl1_main(void) INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT); + print_errata_status(); #if DEBUG u_register_t val; diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S index 25363ace..31f77879 100644 --- a/bl2/aarch64/bl2_entrypoint.S +++ b/bl2/aarch64/bl2_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -94,12 +94,12 @@ func bl2_entrypoint */ ldr x0, =__BSS_START__ ldr x1, =__BSS_SIZE__ - bl zeromem16 + bl zeromem #if USE_COHERENT_MEM ldr x0, =__COHERENT_RAM_START__ ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ - bl zeromem16 + bl zeromem #endif /* -------------------------------------------- diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index fa694de2..b9275f34 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -113,7 +113,8 @@ SECTIONS /* * The .bss section gets initialised to 0 at runtime. - * Its base address must be 16-byte aligned. + * Its base address should be 16-byte aligned for better performance of the + * zero-initialization code. */ .bss : ALIGN(16) { __BSS_START__ = .; diff --git a/bl2u/aarch64/bl2u_entrypoint.S b/bl2u/aarch64/bl2u_entrypoint.S index 1175c6ff..9fa84bf4 100644 --- a/bl2u/aarch64/bl2u_entrypoint.S +++ b/bl2u/aarch64/bl2u_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -94,7 +94,7 @@ func bl2u_entrypoint */ ldr x0, =__BSS_START__ ldr x1, =__BSS_SIZE__ - bl zeromem16 + bl zeromem /* -------------------------------------------- * Allocate a stack whose memory will be marked diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S index d72589fc..91e8556e 100644 --- a/bl2u/bl2u.ld.S +++ b/bl2u/bl2u.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -100,7 +100,8 @@ SECTIONS /* * The .bss section gets initialised to 0 at runtime. - * Its base address must be 16-byte aligned. + * Its base address should be 16-byte aligned for better performance of the + * zero-initialization code. */ .bss : ALIGN(16) { __BSS_START__ = .; diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 9a05e6c3..e5d6232e 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -158,7 +158,8 @@ SECTIONS /* * The .bss section gets initialised to 0 at runtime. - * Its base address must be 16-byte aligned. + * Its base address should be 16-byte aligned for better performance of the + * zero-initialization code. */ .bss (NOLOAD) : ALIGN(16) { __BSS_START__ = .; diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index e0e23e8f..f1d4d0b3 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -134,9 +134,10 @@ SECTIONS /* * The .bss section gets initialised to 0 at runtime. - * Its base address must be 16-byte aligned. + * Its base address should be 8-byte aligned for better performance of the + * zero-initialization code. */ - .bss (NOLOAD) : ALIGN(16) { + .bss (NOLOAD) : ALIGN(8) { __BSS_START__ = .; *(.bss*) *(COMMON) diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c index 02663a29..f34716ed 100644 --- a/bl32/sp_min/sp_min_main.c +++ b/bl32/sp_min/sp_min_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -45,6 +45,7 @@ #include <stdint.h> #include <string.h> #include <types.h> +#include <utils.h> #include "sp_min_private.h" /* Pointers to per-core cpu contexts */ @@ -203,7 +204,7 @@ void sp_min_warm_boot(void) smc_set_next_ctx(NON_SECURE); next_smc_ctx = smc_get_next_ctx(); - memset(next_smc_ctx, 0, sizeof(smc_ctx_t)); + zeromem(next_smc_ctx, sizeof(smc_ctx_t)); copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), next_smc_ctx); diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 4c296d4a..bdb882ab 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -120,12 +120,12 @@ func tsp_entrypoint */ ldr x0, =__BSS_START__ ldr x1, =__BSS_SIZE__ - bl zeromem16 + bl zeromem #if USE_COHERENT_MEM ldr x0, =__COHERENT_RAM_START__ ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ - bl zeromem16 + bl zeromem #endif /* -------------------------------------------- diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index 7e24f66d..d93e3bb0 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -104,7 +104,8 @@ SECTIONS /* * The .bss section gets initialised to 0 at runtime. - * Its base address must be 16-byte aligned. + * Its base address should be 16-byte aligned for better performance of the + * zero-initialization code. */ .bss : ALIGN(16) { __BSS_START__ = .; diff --git a/common/bl_common.c b/common/bl_common.c index 47bdad5a..1d665307 100644 --- a/common/bl_common.c +++ b/common/bl_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -347,7 +347,7 @@ static int load_auth_image_internal(unsigned int image_id, image_data->image_size); if (rc != 0) { /* Authentication error, zero memory and flush it right away. */ - memset((void *)image_data->image_base, 0x00, + zero_normalmem((void *)image_data->image_base, image_data->image_size); flush_dcache_range(image_data->image_base, image_data->image_size); @@ -543,7 +543,7 @@ static int load_auth_image_internal(meminfo_t *mem_layout, image_data->image_size); if (rc != 0) { /* Authentication error, zero memory and flush it right away. */ - memset((void *)image_data->image_base, 0x00, + zero_normalmem((void *)image_data->image_base, image_data->image_size); flush_dcache_range(image_data->image_base, image_data->image_size); diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index df2fbd86..a743487f 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -34,6 +34,9 @@ errata notice document. The format of the define used to enable/disable the errata workaround is `ERRATA_<Processor name>_<ID>`, where the `Processor name` is for example `A57` for the `Cortex_A57` CPU. +Refer to the section _CPU errata status reporting_ in [Firmware Design +guide][Firmware Design] for information on to write errata workaround functions. + All workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the errata workaround build flags in the platform specific makefile. In case @@ -116,3 +119,4 @@ _Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved._ [A57 SW Optimization Guide]: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf [A53 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html [A57 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf +[Firmware Design]: firmware-design.md diff --git a/docs/firmware-design.md b/docs/firmware-design.md index 0acb1fa8..523fa55c 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -16,8 +16,9 @@ Contents : 11. [Use of coherent memory in Trusted Firmware](#11--use-of-coherent-memory-in-trusted-firmware) 12. [Isolating code and read-only data on separate memory pages](#12--isolating-code-and-read-only-data-on-separate-memory-pages) 13. [Performance Measurement Framework](#13--performance-measurement-framework) -14. [Code Structure](#14--code-structure) -15. [References](#15--references) +14. [ARMv8 Architecture Extensions](#14--armv8-architecture-extensions) +15. [Code Structure](#15--code-structure) +16. [References](#16--references) 1. Introduction @@ -1087,7 +1088,7 @@ already been performed and act as appropriate. Possible courses of actions are, e.g. skip the action the second time, or undo/redo it. 8. CPU specific operations framework ------------------------------ +------------------------------------- Certain aspects of the ARMv8 architecture are implementation defined, that is, certain behaviours are not architecturally defined, but must be defined @@ -1102,6 +1103,8 @@ behaviour. The categories are: 3. Processor specific register dumping as a part of crash reporting. +4. Errata status reporting. + Each of the above categories fulfils a different requirement. 1. allows any processor specific initialization before the caches and MMU @@ -1115,6 +1118,9 @@ Each of the above categories fulfils a different requirement. in the event of a crash, for example Cortex-A53 has registers which can expose the data cache contents. +4. allows a processor to define a function that inspects and reports the status + of all errata workarounds on that processor. + Please note that only 2. is mandated by the TRM. The CPU specific operations framework scales to accommodate a large number of @@ -1185,6 +1191,70 @@ reporting framework calls `do_cpu_reg_dump` which retrieves the matching be reported and a pointer to the ASCII list of register names in a format expected by the crash reporting framework. +### CPU errata status reporting + +Errata workarounds for CPUs supported in ARM Trusted Firmware are applied during +both cold and warm boots, shortly after reset. Individual Errata workarounds are +enabled as build options. Some errata workarounds have potential run-time +implications; therefore some are enabled by default, others not. Platform ports +shall override build options to enable or disable errata as appropriate. The CPU +drivers take care of applying errata workarounds that are enabled and applicable +to a given CPU. Refer to the section titled _CPU Errata Workarounds_ in [CPUBM] +for more information. + +Functions in CPU drivers that apply errata workaround must follow the +conventions listed below. + +The errata workaround must be authored as two separate functions: + +* One that checks for errata. This function must determine whether that errata + applies to the current CPU. Typically this involves matching the current + CPUs revision and variant against a value that's known to be affected by the + errata. If the function determines that the errata applies to this CPU, it + must return `ERRATA_APPLIES`; otherwise, it must return + `ERRATA_NOT_APPLIES`. The utility functions `cpu_get_rev_var` and + `cpu_rev_var_ls` functions may come in handy for this purpose. + + For an errata identified as `E`, the check function must be named + `check_errata_E`. + + This function will be invoked at different times, both from assembly and from + C run time. Therefore it must follow AAPCS, and must not use stack. + +* Another one that applies the errata workaround. This function would call the + check function described above, and applies errata workaround if required. + +CPU drivers that apply errata workaround can optionally implement an assembly +function that report the status of errata workarounds pertaining to that CPU. +For a driver that registers the CPU, for example, `cpux` via. `declare_cpu_ops` +macro, the errata reporting function, if it exists, must be named +`cpux_errata_report`. This function will always be called with MMU enabled; it +must follow AAPCS and may use stack. + +In a debug build of ARM Trusted Firmware, on a CPU that comes out of reset, both +BL1 and the run time firmware (BL31 in AArch64, and BL32 in AArch32) will invoke +errata status reporting function, if one exists, for that type of CPU. + +To report the status of each errata workaround, the function shall use the +assembler macro `report_errata`, passing it: + +* The build option that enables the errata; + +* The name of the CPU: this must be the same identifier that CPU driver + registered itself with, using `declare_cpu_ops`; + +* And the errata identifier: the identifier must match what's used in the + errata's check function described above. + +The errata status reporting function will be called once per CPU type/errata +combination during the software's active life time. + +It's expected that whenever an errata workaround is submitted to ARM Trusted +Firmware, the errata reporting function is appropriately extended to report its +status as well. + +Reporting the status of errata workaround is for informational purpose only; it +has no functional significance. 9. Memory layout of BL images ----------------------------- @@ -1273,7 +1343,7 @@ All BL images share the following requirements: The following linker symbols are defined for this purpose: -* `__BSS_START__` Must be aligned on a 16-byte boundary. +* `__BSS_START__` * `__BSS_SIZE__` * `__COHERENT_RAM_START__` Must be aligned on a page-size boundary. * `__COHERENT_RAM_END__` Must be aligned on a page-size boundary. @@ -2139,7 +2209,39 @@ in this implementation. 5. `pmf_helpers.h` is an internal header used by `pmf.h`. -14. Code Structure +14. ARMv8 Architecture Extensions +---------------------------------- + +ARM Trusted Firmware makes use of ARMv8 Architecture Extensions where +applicable. This section lists the usage of Architecture Extensions, and build +flags controlling them. + +In general, and unless individually mentioned, the build options +`ARM_ARCH_MAJOR` and `ARM_ARCH_MINOR` selects the Architecture Extension to +target when building ARM Trusted Firmware. Subsequent ARM Architecture +Extensions are backward compatible with previous versions. + +The build system only requires that `ARM_ARCH_MAJOR` and `ARM_ARCH_MINOR` have a +valid numeric value. These build options only control whether or not +Architecture Extension-specific code is included in the build. Otherwise, ARM +Trusted Firmware targets the base ARMv8.0 architecture; i.e. as if +`ARM_ARCH_MAJOR` == 8 and `ARM_ARCH_MINOR` == 0, which are also their respective +default values. + +See also the _Summary of build options_ in [User Guide]. + +For details on the Architecture Extension and available features, please refer +to the respective Architecture Extension Supplement. + +### ARMv8.1 + +This Architecture Extension is targeted when `ARM_ARCH_MAJOR` >= 8, or when +`ARM_ARCH_MAJOR` == 8 and `ARM_ARCH_MINOR` >= 1. + +* The Compare and Swap instruction is used to implement spinlocks. Otherwise, + the load-/store-exclusive instruction pair is used. + +15. Code Structure ------------------- Trusted Firmware code is logically divided between the three boot loader @@ -2183,7 +2285,7 @@ FDTs provide a description of the hardware platform and are used by the Linux kernel at boot time. These can be found in the `fdts` directory. -15. References +16. References --------------- 1. Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index b29532c9..f82085b1 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -62,6 +62,22 @@ TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31' Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>' to the build command line. +The Tegra platform code expects a pointer to the following platform specific +structure via 'x1' register from the BL2 layer which is used by the +bl31_early_platform_setup() handler to extract the TZDRAM carveout base and +size for loading the Trusted OS and the UART port ID to be used. The Tegra +memory controller driver programs this base/size in order to restrict NS +accesses. + +typedef struct plat_params_from_bl2 { + /* TZ memory size */ + uint64_t tzdram_size; + /* TZ memory base */ + uint64_t tzdram_base; + /* UART port ID */ + int uart_id; +} plat_params_from_bl2_t; + Power Management ================ The PSCI implementation expects each platform to expose the 'power state' diff --git a/docs/plat/xilinx-zynqmp.md b/docs/plat/xilinx-zynqmp.md index 09546b01..d2dc8b76 100644 --- a/docs/plat/xilinx-zynqmp.md +++ b/docs/plat/xilinx-zynqmp.md @@ -12,12 +12,12 @@ BL33 is the non-secure world software (U-Boot, Linux etc). To build: ```bash -make ERROR_DEPRECATED=1 RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31 +make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31 ``` To build bl32 TSP you have to rebuild bl31 too: ```bash -make ERROR_DEPRECATED=1 RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32 +make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32 ``` # ZynqMP platform specific build options diff --git a/docs/porting-guide.md b/docs/porting-guide.md index e8486f12..a5e59667 100644 --- a/docs/porting-guide.md +++ b/docs/porting-guide.md @@ -1707,10 +1707,56 @@ level could enter. It depends on the `validate_power_state()` handler to convert the power-state parameter (possibly encoding a composite power state) passed in a PSCI `CPU_SUSPEND` call to this representation. -The following functions must be implemented to initialize PSCI functionality in -the ARM Trusted Firmware. +The following functions form part of platform port of PSCI functionality. +### Function : plat_psci_stat_accounting_start() [optional] + + Argument : const psci_power_state_t * + Return : void + +This is an optional hook that platforms can implement for residency statistics +accounting before entering a low power state. The `pwr_domain_state` field of +`state_info` (first argument) can be inspected if stat accounting is done +differently at CPU level versus higher levels. As an example, if the element at +index 0 (CPU power level) in the `pwr_domain_state` array indicates a power down +state, special hardware logic may be programmed in order to keep track of the +residency statistics. For higher levels (array indices > 0), the residency +statistics could be tracked in software using PMF. If `ENABLE_PMF` is set, the +default implementation will use PMF to capture timestamps. + +### Function : plat_psci_stat_accounting_stop() [optional] + + Argument : const psci_power_state_t * + Return : void + +This is an optional hook that platforms can implement for residency statistics +accounting after exiting from a low power state. The `pwr_domain_state` field +of `state_info` (first argument) can be inspected if stat accounting is done +differently at CPU level versus higher levels. As an example, if the element at +index 0 (CPU power level) in the `pwr_domain_state` array indicates a power down +state, special hardware logic may be programmed in order to keep track of the +residency statistics. For higher levels (array indices > 0), the residency +statistics could be tracked in software using PMF. If `ENABLE_PMF` is set, the +default implementation will use PMF to capture timestamps. + +### Function : plat_psci_stat_get_residency() [optional] + + Argument : unsigned int, const psci_power_state_t *, int + Return : u_register_t + +This is an optional interface that is is invoked after resuming from a low power +state and provides the time spent resident in that low power state by the power +domain at a particular power domain level. When a CPU wakes up from suspend, +all its parent power domain levels are also woken up. The generic PSCI code +invokes this function for each parent power domain that is resumed and it +identified by the `lvl` (first argument) parameter. The `state_info` (second +argument) describes the low power state that the power domain has resumed from. +The current CPU is the first CPU in the power domain to resume from the low +power state and the `last_cpu_idx` (third parameter) is the index of the last +CPU in the power domain to suspend and may be needed to calculate the residency +for that power domain. + ### Function : plat_get_target_pwr_state() [optional] Argument : unsigned int, const plat_local_state_t *, unsigned int diff --git a/docs/user-guide.md b/docs/user-guide.md index 056c4145..091aeba0 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -37,6 +37,9 @@ the different software components required to boot a Linux system: * Linux kernel image * Root filesystem +Note: the ARM TF v1.3 release was tested with Linaro Release 16.06, and the +latest version of ARM TF is tested with Linaro Release 16.12. + This document also assumes that the user is familiar with the FVP models and the different command line options available to launch the model. @@ -181,6 +184,14 @@ performed. is used to determine the number of valid slave interfaces available in the ARM CCI driver. Default is 400 (that is, CCI-400). +* `ARM_ARCH_MAJOR`: The major version of ARM Architecture to target when + compiling ARM Trusted Firmware. Its value must be numeric, and defaults to + 8. See also, _ARMv8 Architecture Extensions_ in [Firmware Design]. + +* `ARM_ARCH_MINOR`: The minor version of ARM Architecture to target when + compiling ARM Trusted Firmware. Its value must be a numeric, and defaults + to 0. See also, _ARMv8 Architecture Extensions_ in [Firmware Design]. + * `ARM_GIC_ARCH`: Choice of ARM GIC architecture version used by the ARM Legacy GIC driver for implementing the platform GIC API. This API is used by the interrupt management framework. Default is 2 (that is, version 2.0). @@ -274,8 +285,9 @@ performed. * `ENABLE_PSCI_STAT`: Boolean option to enable support for optional PSCI functions `PSCI_STAT_RESIDENCY` and `PSCI_STAT_COUNT`. Default is 0. - Enabling this option enables the `ENABLE_PMF` build option as well. - The PMF is used for collecting the statistics. + In the absence of an alternate stat collection backend, `ENABLE_PMF` must + be enabled. If `ENABLE_PMF` is set, the residency statistics are tracked in + software. * `ENABLE_RUNTIME_INSTRUMENTATION`: Boolean option to enable runtime instrumentation which injects timestamp collection points into @@ -878,8 +890,8 @@ Firmware, obtain the additional required firmware, and pack it all together in a single FIP binary. It assumes that a [Linaro Release][Linaro Release Notes] has been installed. -Note currently [Linaro Release][Linaro Release Notes] only includes pre-built -binaries for AArch64. For AArch32, pre-built binaries are not available. +Note: Linaro Release 16.06 only includes pre-built binaries for AArch64. For +AArch32, pre-built binaries are only available from Linaro Release 16.12. Note: follow the full instructions for one platform before switching to a different one. Mixing instructions for different platforms may result in @@ -1099,19 +1111,19 @@ to load the ELF file over JTAG on Juno. 9. Running the software on FVP ------------------------------- -The AArch64 build of this version of ARM Trusted Firmware has been tested on -the following ARM FVPs (64-bit host machine only). +The latest version of the AArch64 build of ARM Trusted Firmware has been tested +on the following ARM FVPs (64-bit host machine only). * `Foundation_Platform` (Version 10.2, Build 10.2.20) -* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) -* `FVP_Base_Cortex-A57x4-A53x4` (Version 7.7, Build 0.8.7701) -* `FVP_Base_Cortex-A57x1-A53x1` (Version 7.7, Build 0.8.7701) -* `FVP_Base_Cortex-A57x2-A53x4` (Version 7.7, Build 0.8.7701) +* `FVP_Base_AEMv8A-AEMv8A` (Version 8.2, Build 0.8.8202) +* `FVP_Base_Cortex-A57x4-A53x4` (Version 8.2, Build 0.8.8202) +* `FVP_Base_Cortex-A57x1-A53x1` (Version 8.2, Build 0.8.8202) +* `FVP_Base_Cortex-A57x2-A53x4` (Version 8.2, Build 0.8.8202) -The AArch32 build of this version of ARM Trusted Firmware has been tested on -the following ARM FVPs (64-bit host machine only). +The latest version of the AArch32 build of ARM Trusted Firmware has been tested +on the following ARM FVPs (64-bit host machine only). -* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) +* `FVP_Base_AEMv8A-AEMv8A` (Version 8.2, Build 0.8.8202) * `FVP_Base_Cortex-A32x4` (Version 10.1, Build 10.1.32) NOTE: The build numbers quoted above are those reported by launching the FVP @@ -1120,7 +1132,9 @@ with the `--version` parameter. NOTE: The software will not work on Version 1.0 of the Foundation FVP. The commands below would report an `unhandled argument` error in this case. -NOTE: The Foundation FVP does not provide a debugger interface. +NOTE: FVPs can be launched with `--cadi-server` option such that a +CADI-compliant debugger (for example, ARM DS-5) can connect to and control its +execution. The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be downloaded for free from [ARM's website][ARM FVP website]. @@ -1129,6 +1143,9 @@ Please refer to the FVP documentation for a detailed description of the model parameter options. A brief description of the important ones that affect the ARM Trusted Firmware and normal world software behavior is provided below. +Note the instructions in the following sections assume that Linaro Release 16.06 +is being used. + ### Obtaining the Flattened Device Trees Depending on the FVP configuration and Linux configuration used, different @@ -1434,12 +1451,12 @@ wakeup interrupt from RTC. - - - - - - - - - - - - - - - - - - - - - - - - - - -_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._ +_Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved._ [Firmware Design]: firmware-design.md -[ARM FVP website]: http://www.arm.com/fvp -[Linaro Release Notes]: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1606 +[ARM FVP website]: https://developer.arm.com/products/system-design/fixed-virtual-platforms +[Linaro Release Notes]: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated [ARM Platforms Portal]: https://community.arm.com/groups/arm-development-platforms [Linaro SW Instructions]: https://community.arm.com/docs/DOC-10803 [Juno Instructions]: https://community.arm.com/docs/DOC-10804 diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c index 11d3ede4..1a96e8f8 100644 --- a/drivers/auth/mbedtls/mbedtls_crypto.c +++ b/drivers/auth/mbedtls/mbedtls_crypto.c @@ -217,7 +217,7 @@ static int verify_hash(void *data_ptr, unsigned int data_len, } /* Compare values */ - rc = timingsafe_bcmp(data_hash, hash, mbedtls_md_get_size(md_info)); + rc = memcmp(data_hash, hash, mbedtls_md_get_size(md_info)); if (rc != 0) { return CRYPTO_ERR_HASH; } diff --git a/drivers/auth/mbedtls/mbedtls_x509_parser.c b/drivers/auth/mbedtls/mbedtls_x509_parser.c index f9485de3..092c346b 100644 --- a/drivers/auth/mbedtls/mbedtls_x509_parser.c +++ b/drivers/auth/mbedtls/mbedtls_x509_parser.c @@ -43,6 +43,7 @@ #include <stddef.h> #include <stdint.h> #include <string.h> +#include <utils.h> /* mbed TLS headers */ #include <mbedtls/asn1.h> @@ -71,7 +72,7 @@ static void clear_temp_vars(void) { #define ZERO_AND_CLEAN(x) \ do { \ - memset(&x, 0, sizeof(x)); \ + zeromem(&x, sizeof(x)); \ clean_dcache_range((uintptr_t)&x, sizeof(x)); \ } while (0); @@ -111,7 +112,7 @@ static int get_ext(const char *oid, void **ext, unsigned int *ext_len) MBEDTLS_ASN1_SEQUENCE); while (p < end) { - memset(&extn_oid, 0x0, sizeof(extn_oid)); + zeromem(&extn_oid, sizeof(extn_oid)); is_critical = 0; /* DEFAULT FALSE */ mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | @@ -392,7 +393,7 @@ static int cert_parse(void *img, unsigned int img_len) if (sig_alg1.len != sig_alg2.len) { return IMG_PARSER_ERR_FORMAT; } - if (0 != timingsafe_bcmp(sig_alg1.p, sig_alg2.p, sig_alg1.len)) { + if (0 != memcmp(sig_alg1.p, sig_alg2.p, sig_alg1.len)) { return IMG_PARSER_ERR_FORMAT; } memcpy(&sig_alg, &sig_alg1, sizeof(sig_alg)); diff --git a/drivers/emmc/emmc.c b/drivers/emmc/emmc.c index 3fae2a15..1c1ea82a 100644 --- a/drivers/emmc/emmc.c +++ b/drivers/emmc/emmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -36,6 +36,7 @@ #include <emmc.h> #include <errno.h> #include <string.h> +#include <utils.h> static const emmc_ops_t *ops; static unsigned int emmc_ocr_value; @@ -53,7 +54,7 @@ static int emmc_device_state(void) int ret; do { - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD13; cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET; cmd.resp_type = EMMC_RESPONSE_R1; @@ -71,7 +72,7 @@ static void emmc_set_ext_csd(unsigned int ext_cmd, unsigned int value) emmc_cmd_t cmd; int ret, state; - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD6; cmd.cmd_arg = EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) | EXTCSD_VALUE(value) | 1; @@ -107,14 +108,14 @@ static int emmc_enumerate(int clk, int bus_width) ops->init(); /* CMD0: reset to IDLE */ - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD0; ret = ops->send_cmd(&cmd); assert(ret == 0); while (1) { /* CMD1: get OCR register */ - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD1; cmd.cmd_arg = OCR_SECTOR_MODE | OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7; @@ -127,14 +128,14 @@ static int emmc_enumerate(int clk, int bus_width) } /* CMD2: Card Identification */ - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD2; cmd.resp_type = EMMC_RESPONSE_R2; ret = ops->send_cmd(&cmd); assert(ret == 0); /* CMD3: Set Relative Address */ - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD3; cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET; cmd.resp_type = EMMC_RESPONSE_R1; @@ -142,7 +143,7 @@ static int emmc_enumerate(int clk, int bus_width) assert(ret == 0); /* CMD9: CSD Register */ - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD9; cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET; cmd.resp_type = EMMC_RESPONSE_R2; @@ -151,7 +152,7 @@ static int emmc_enumerate(int clk, int bus_width) memcpy(&emmc_csd, &cmd.resp_data, sizeof(cmd.resp_data)); /* CMD7: Select Card */ - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD7; cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET; cmd.resp_type = EMMC_RESPONSE_R1; @@ -181,7 +182,7 @@ size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size) assert(ret == 0); if (is_cmd23_enabled()) { - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); /* set block count */ cmd.cmd_idx = EMMC_CMD23; cmd.cmd_arg = size / EMMC_BLOCK_SIZE; @@ -189,7 +190,7 @@ size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size) ret = ops->send_cmd(&cmd); assert(ret == 0); - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD18; } else { if (size > EMMC_BLOCK_SIZE) @@ -213,7 +214,7 @@ size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size) if (is_cmd23_enabled() == 0) { if (size > EMMC_BLOCK_SIZE) { - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD12; ret = ops->send_cmd(&cmd); assert(ret == 0); @@ -240,17 +241,17 @@ size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size) if (is_cmd23_enabled()) { /* set block count */ - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD23; cmd.cmd_arg = size / EMMC_BLOCK_SIZE; cmd.resp_type = EMMC_RESPONSE_R1; ret = ops->send_cmd(&cmd); assert(ret == 0); - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD25; } else { - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); if (size > EMMC_BLOCK_SIZE) cmd.cmd_idx = EMMC_CMD25; else @@ -272,7 +273,7 @@ size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size) if (is_cmd23_enabled() == 0) { if (size > EMMC_BLOCK_SIZE) { - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD12; ret = ops->send_cmd(&cmd); assert(ret == 0); @@ -291,21 +292,21 @@ size_t emmc_erase_blocks(int lba, size_t size) assert(ops != 0); assert((size != 0) && ((size % EMMC_BLOCK_SIZE) == 0)); - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD35; cmd.cmd_arg = lba; cmd.resp_type = EMMC_RESPONSE_R1; ret = ops->send_cmd(&cmd); assert(ret == 0); - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD36; cmd.cmd_arg = lba + (size / EMMC_BLOCK_SIZE) - 1; cmd.resp_type = EMMC_RESPONSE_R1; ret = ops->send_cmd(&cmd); assert(ret == 0); - memset(&cmd, 0, sizeof(emmc_cmd_t)); + zeromem(&cmd, sizeof(emmc_cmd_t)); cmd.cmd_idx = EMMC_CMD38; cmd.resp_type = EMMC_RESPONSE_R1B; ret = ops->send_cmd(&cmd); diff --git a/drivers/io/io_block.c b/drivers/io/io_block.c index 4ec59bc7..a855581b 100644 --- a/drivers/io/io_block.c +++ b/drivers/io/io_block.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -36,6 +36,7 @@ #include <io_storage.h> #include <platform_def.h> #include <string.h> +#include <utils.h> typedef struct { io_block_dev_spec_t *dev_spec; @@ -135,8 +136,8 @@ static int free_dev_info(io_dev_info_t *dev_info) result = find_first_block_state(state->dev_spec, &index); if (result == 0) { /* free if device info is valid */ - memset(state, 0, sizeof(block_dev_state_t)); - memset(dev_info, 0, sizeof(io_dev_info_t)); + zeromem(state, sizeof(block_dev_state_t)); + zeromem(dev_info, sizeof(io_dev_info_t)); --block_dev_count; } diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c index 99cf15b9..6724fc3b 100644 --- a/drivers/io/io_fip.c +++ b/drivers/io/io_fip.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -40,6 +40,7 @@ #include <platform_def.h> #include <stdint.h> #include <string.h> +#include <utils.h> #include <uuid.h> /* Useful for printing UUIDs when debugging.*/ @@ -351,7 +352,7 @@ static int fip_file_close(io_entity_t *entity) * If we had malloc() we would free() here. */ if (current_file.entry.offset_address != 0) { - memset(¤t_file, 0, sizeof(current_file)); + zeromem(¤t_file, sizeof(current_file)); } /* Clear the Entity info. */ diff --git a/drivers/io/io_memmap.c b/drivers/io/io_memmap.c index fe39652b..5104fb19 100644 --- a/drivers/io/io_memmap.c +++ b/drivers/io/io_memmap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ #include <io_driver.h> #include <io_storage.h> #include <string.h> +#include <utils.h> /* As we need to be able to keep state for seek, only one file can be open * at a time. Make this a structure and point to the entity->info. When we @@ -118,13 +119,14 @@ static int memmap_dev_close(io_dev_info_t *dev_info) /* Open a file on the memmap device */ -/* TODO: Can we do any sensible limit checks on requested memory */ static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity) { int result = -ENOMEM; const io_block_spec_t *block_spec = (io_block_spec_t *)spec; + assert(block_spec->length >= 0); + /* Since we need to track open state for seek() we only allow one open * spec at a time. When we have dynamic memory we can malloc and set * entity->info. @@ -152,13 +154,19 @@ static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset) { int result = -ENOENT; + file_state_t *fp; /* We only support IO_SEEK_SET for the moment. */ if (mode == IO_SEEK_SET) { assert(entity != NULL); - /* TODO: can we do some basic limit checks on seek? */ - ((file_state_t *)entity->info)->file_pos = offset; + fp = (file_state_t *) entity->info; + + /* Assert that new file position is valid */ + assert((offset >= 0) && (offset < fp->size)); + + /* Reset file position */ + fp->file_pos = offset; result = 0; } @@ -183,18 +191,24 @@ static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) { file_state_t *fp; + size_t pos_after; assert(entity != NULL); assert(buffer != (uintptr_t)NULL); assert(length_read != NULL); - fp = (file_state_t *)entity->info; + fp = (file_state_t *) entity->info; + + /* Assert that file position is valid for this read operation */ + pos_after = fp->file_pos + length; + assert((pos_after >= fp->file_pos) && (pos_after <= fp->size)); memcpy((void *)buffer, (void *)(fp->base + fp->file_pos), length); *length_read = length; - /* advance the file 'cursor' for incremental reads */ - fp->file_pos += length; + + /* Set file position after read */ + fp->file_pos = pos_after; return 0; } @@ -205,19 +219,24 @@ static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, size_t length, size_t *length_written) { file_state_t *fp; + size_t pos_after; assert(entity != NULL); assert(buffer != (uintptr_t)NULL); assert(length_written != NULL); - fp = (file_state_t *)entity->info; + fp = (file_state_t *) entity->info; + + /* Assert that file position is valid for this write operation */ + pos_after = fp->file_pos + length; + assert((pos_after >= fp->file_pos) && (pos_after <= fp->size)); memcpy((void *)(fp->base + fp->file_pos), (void *)buffer, length); *length_written = length; - /* advance the file 'cursor' for incremental writes */ - fp->file_pos += length; + /* Set file position after write */ + fp->file_pos = pos_after; return 0; } @@ -231,7 +250,7 @@ static int memmap_block_close(io_entity_t *entity) entity->info = 0; /* This would be a mem free() if we had malloc.*/ - memset((void *)¤t_file, 0, sizeof(current_file)); + zeromem((void *)¤t_file, sizeof(current_file)); return 0; } diff --git a/drivers/io/io_semihosting.c b/drivers/io/io_semihosting.c index 30ca99cb..e33a044d 100644 --- a/drivers/io/io_semihosting.c +++ b/drivers/io/io_semihosting.c @@ -95,7 +95,7 @@ static int sh_file_open(io_dev_info_t *dev_info __unused, const uintptr_t spec, io_entity_t *entity) { int result = -ENOENT; - long sh_result = -1; + long sh_result; const io_file_spec_t *file_spec = (const io_file_spec_t *)spec; assert(file_spec != NULL); @@ -151,7 +151,7 @@ static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) { int result = -ENOENT; - long sh_result = -1; + long sh_result; size_t bytes = length; long file_handle; @@ -176,7 +176,7 @@ static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, static int sh_file_write(io_entity_t *entity, const uintptr_t buffer, size_t length, size_t *length_written) { - long sh_result = -1; + long sh_result; long file_handle; size_t bytes = length; @@ -197,7 +197,7 @@ static int sh_file_write(io_entity_t *entity, const uintptr_t buffer, /* Close a file on the semi-hosting device */ static int sh_file_close(io_entity_t *entity) { - long sh_result = -1; + long sh_result; long file_handle; assert(entity != NULL); diff --git a/drivers/partition/gpt.c b/drivers/partition/gpt.c index 9240d5a7..05f13f34 100644 --- a/drivers/partition/gpt.c +++ b/drivers/partition/gpt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ #include <errno.h> #include <gpt.h> #include <string.h> +#include <utils.h> static int unicode_to_ascii(unsigned short *str_in, unsigned char *str_out) { @@ -65,7 +66,7 @@ int parse_gpt_entry(gpt_entry_t *gpt_entry, partition_entry_t *entry) return -EINVAL; } - memset(entry, 0, sizeof(partition_entry_t)); + zeromem(entry, sizeof(partition_entry_t)); result = unicode_to_ascii(gpt_entry->name, (uint8_t *)entry->name); if (result != 0) { return result; diff --git a/include/bl32/payloads/tlk.h b/include/bl32/payloads/tlk.h index 6ce1eb69..d355313e 100644 --- a/include/bl32/payloads/tlk.h +++ b/include/bl32/payloads/tlk.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,6 +31,8 @@ #ifndef __TLK_H__ #define __TLK_H__ +#include <utils.h> + /* * Generate function IDs for the Trusted OS/Apps */ @@ -51,13 +53,13 @@ * SMC function IDs that TLK uses to signal various forms of completions * to the secure payload dispatcher. */ -#define TLK_REQUEST_DONE (0x32000001 | (1 << 31)) -#define TLK_PREEMPTED (0x32000002 | (1 << 31)) -#define TLK_ENTRY_DONE (0x32000003 | (1 << 31)) -#define TLK_VA_TRANSLATE (0x32000004 | (1 << 31)) -#define TLK_SUSPEND_DONE (0x32000005 | (1 << 31)) -#define TLK_RESUME_DONE (0x32000006 | (1 << 31)) -#define TLK_SYSTEM_OFF_DONE (0x32000007 | (1 << 31)) +#define TLK_REQUEST_DONE (0x32000001 | (ULL(1) << 31)) +#define TLK_PREEMPTED (0x32000002 | (ULL(1) << 31)) +#define TLK_ENTRY_DONE (0x32000003 | (ULL(1) << 31)) +#define TLK_VA_TRANSLATE (0x32000004 | (ULL(1) << 31)) +#define TLK_SUSPEND_DONE (0x32000005 | (ULL(1) << 31)) +#define TLK_RESUME_DONE (0x32000006 | (ULL(1) << 31)) +#define TLK_SYSTEM_OFF_DONE (0x32000007 | (ULL(1) << 31)) /* * Trusted Application specific function IDs diff --git a/include/common/aarch32/asm_macros.S b/include/common/aarch32/asm_macros.S index 23122f34..45023a0b 100644 --- a/include/common/aarch32/asm_macros.S +++ b/include/common/aarch32/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -32,6 +32,7 @@ #include <arch.h> #include <asm_macros_common.S> +#include <spinlock.h> #define WORD_SIZE 4 @@ -124,4 +125,13 @@ #endif .endm + /* + * Reserve space for a spin lock in assembly file. + */ + .macro define_asm_spinlock _name:req + .align SPINLOCK_ASM_ALIGN + \_name: + .space SPINLOCK_ASM_SIZE + .endm + #endif /* __ASM_MACROS_S__ */ diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S index 463a0806..f6b7527e 100644 --- a/include/common/aarch32/el3_common_macros.S +++ b/include/common/aarch32/el3_common_macros.S @@ -98,6 +98,11 @@ orr r0, r0, #FPEXC_EN_BIT vmsr FPEXC, r0 isb + + /* Disable secure self-hosted invasive debug. */ + ldr r0, =SDCR_DEF_VAL + stcopr r0, SDCR + .endm /* ----------------------------------------------------------------------------- diff --git a/include/common/aarch64/asm_macros.S b/include/common/aarch64/asm_macros.S index 88e8d9c6..b0f3a0db 100644 --- a/include/common/aarch64/asm_macros.S +++ b/include/common/aarch64/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -32,6 +32,7 @@ #include <arch.h> #include <asm_macros_common.S> +#include <spinlock.h> .macro func_prologue @@ -200,4 +201,13 @@ #endif .endm + /* + * Reserve space for a spin lock in assembly file. + */ + .macro define_asm_spinlock _name:req + .align SPINLOCK_ASM_ALIGN + \_name: + .space SPINLOCK_ASM_SIZE + .endm + #endif /* __ASM_MACROS_S__ */ diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S index cbfa6eec..e085f9f1 100644 --- a/include/common/aarch64/el3_common_macros.S +++ b/include/common/aarch64/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -79,10 +79,11 @@ msr scr_el3, x0 /* --------------------------------------------------------------------- - * Reset registers that may have architecturally unknown reset values + * Disable secure self-hosted invasive debug. * --------------------------------------------------------------------- */ - msr mdcr_el3, xzr + mov_imm x0, MDCR_DEF_VAL + msr mdcr_el3, x0 /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception @@ -252,12 +253,12 @@ ldr x0, =__BSS_START__ ldr x1, =__BSS_SIZE__ - bl zeromem16 + bl zeromem #if USE_COHERENT_MEM ldr x0, =__COHERENT_RAM_START__ ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ - bl zeromem16 + bl zeromem #endif #ifdef IMAGE_BL1 diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 170fa841..8525c7ba 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -125,6 +125,14 @@ #define SCTLR_AFE_BIT (1 << 29) #define SCTLR_TE_BIT (1 << 30) +/* SDCR definitions */ +#define SDCR_SPD(x) ((x) << 14) +#define SDCR_SPD_LEGACY 0x0 +#define SDCR_SPD_DISABLE 0x2 +#define SDCR_SPD_ENABLE 0x3 + +#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE) + /* HSCTLR definitions */ #define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \ | (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \ @@ -345,6 +353,7 @@ /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ #define SCR p15, 0, c1, c1, 0 #define SCTLR p15, 0, c1, c0, 0 +#define SDCR p15, 0, c1, c3, 1 #define MPIDR p15, 0, c0, c0, 5 #define MIDR p15, 0, c0, c0, 0 #define VBAR p15, 0, c12, c0, 0 diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 989667a7..5876ce81 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -39,8 +39,10 @@ #define MIDR_IMPL_SHIFT 0x18 #define MIDR_VAR_SHIFT 20 #define MIDR_VAR_BITS 4 +#define MIDR_VAR_MASK 0xf #define MIDR_REV_SHIFT 0 #define MIDR_REV_BITS 4 +#define MIDR_REV_MASK 0xf #define MIDR_PN_MASK 0xfff #define MIDR_PN_SHIFT 0x4 @@ -193,6 +195,15 @@ #define SCR_NS_BIT (1 << 0) #define SCR_VALID_BIT_MASK 0x2f8f +/* MDCR definitions */ +#define MDCR_SPD32(x) ((x) << 14) +#define MDCR_SPD32_LEGACY 0x0 +#define MDCR_SPD32_DISABLE 0x2 +#define MDCR_SPD32_ENABLE 0x3 +#define MDCR_SDD_BIT (1 << 16) + +#define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) + /* HCR definitions */ #define HCR_RW_BIT (1ull << 31) #define HCR_AMO_BIT (1 << 5) diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S index 64df2366..bf16e180 100644 --- a/include/lib/cpus/aarch32/cpu_macros.S +++ b/include/lib/cpus/aarch32/cpu_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,6 +31,7 @@ #define __CPU_MACROS_S__ #include <arch.h> +#include <errata_report.h> #define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ (MIDR_PN_MASK << MIDR_PN_SHIFT) @@ -44,6 +45,16 @@ /* Word size for 32-bit CPUs */ #define CPU_WORD_SIZE 4 +/* + * Whether errata status needs reporting. Errata status is printed in debug + * builds for both BL1 and BL32 images. + */ +#if (defined(IMAGE_BL1) || defined(IMAGE_BL32)) && DEBUG +# define REPORT_ERRATA 1 +#else +# define REPORT_ERRATA 0 +#endif + /* * Define the offsets to the fields in cpu_ops structure. */ @@ -59,6 +70,22 @@ CPU_RESET_FUNC: /* cpu_ops reset_func */ CPU_PWR_DWN_OPS: /* cpu_ops power down functions */ .space (4 * CPU_MAX_PWR_DWN_OPS) #endif + +/* + * Fields required to print errata status. Only in BL32 that the printing + * require mutual exclusion and printed flag. + */ +#if REPORT_ERRATA +CPU_ERRATA_FUNC: /* CPU errata status printing function */ + .space 4 +#ifdef IMAGE_BL32 +CPU_ERRATA_LOCK: + .space 4 +CPU_ERRATA_PRINTED: + .space 4 +#endif +#endif + CPU_OPS_SIZE = . /* @@ -137,6 +164,79 @@ CPU_OPS_SIZE = . .endif .endif #endif + +#if REPORT_ERRATA + .ifndef \_name\()_cpu_str + /* + * Place errata reported flag, and the spinlock to arbitrate access to + * it in the data section. + */ + .pushsection .data + define_asm_spinlock \_name\()_errata_lock + \_name\()_errata_reported: + .word 0 + .popsection + + /* Place CPU string in rodata */ + .pushsection .rodata + \_name\()_cpu_str: + .asciz "\_name" + .popsection + .endif + + /* + * Weakly-bound, optional errata status printing function for CPUs of + * this class. + */ + .weak \_name\()_errata_report + .word \_name\()_errata_report + +#ifdef IMAGE_BL32 + /* Pointers to errata lock and reported flag */ + .word \_name\()_errata_lock + .word \_name\()_errata_reported +#endif +#endif + .endm + +#if REPORT_ERRATA + /* + * Print status of a CPU errata + * + * _chosen: + * Identifier indicating whether or not a CPU errata has been + * compiled in. + * _cpu: + * Name of the CPU + * _id: + * Errata identifier + * _rev_var: + * Register containing the combined value CPU revision and variant + * - typically the return value of cpu_get_rev_var + */ + .macro report_errata _chosen, _cpu, _id, _rev_var=r4 + /* Stash a string with errata ID */ + .pushsection .rodata + \_cpu\()_errata_\_id\()_str: + .asciz "\_id" + .popsection + + /* Check whether errata applies */ + mov r0, \_rev_var + bl check_errata_\_id + + .ifeq \_chosen + /* + * Errata workaround has not been compiled in. If the errata would have + * applied had it been compiled in, print its status as missing. + */ + cmp r0, #0 + movne r0, #ERRATA_MISSING + .endif + ldr r1, =\_cpu\()_cpu_str + ldr r2, =\_cpu\()_errata_\_id\()_str + bl errata_print_msg .endm +#endif #endif /* __CPU_MACROS_S__ */ diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index 5012877e..e3b4afdc 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,6 +31,7 @@ #define __CPU_MACROS_S__ #include <arch.h> +#include <errata_report.h> #define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ (MIDR_PN_MASK << MIDR_PN_SHIFT) @@ -44,6 +45,16 @@ /* Word size for 64-bit CPUs */ #define CPU_WORD_SIZE 8 +/* + * Whether errata status needs reporting. Errata status is printed in debug + * builds for both BL1 and BL31 images. + */ +#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG +# define REPORT_ERRATA 1 +#else +# define REPORT_ERRATA 0 +#endif + /* * Define the offsets to the fields in cpu_ops structure. */ @@ -59,6 +70,22 @@ CPU_RESET_FUNC: /* cpu_ops reset_func */ CPU_PWR_DWN_OPS: /* cpu_ops power down functions */ .space (8 * CPU_MAX_PWR_DWN_OPS) #endif + +/* + * Fields required to print errata status. Only in BL31 that the printing + * require mutual exclusion and printed flag. + */ +#if REPORT_ERRATA +CPU_ERRATA_FUNC: + .space 8 +#ifdef IMAGE_BL31 +CPU_ERRATA_LOCK: + .space 8 +CPU_ERRATA_PRINTED: + .space 8 +#endif +#endif + #if defined(IMAGE_BL31) && CRASH_REPORTING CPU_REG_DUMP: /* cpu specific register dump for crash reporting */ .space 8 @@ -141,9 +168,84 @@ CPU_OPS_SIZE = . .endif .endif #endif + +#if REPORT_ERRATA + .ifndef \_name\()_cpu_str + /* + * Place errata reported flag, and the spinlock to arbitrate access to + * it in the data section. + */ + .pushsection .data + define_asm_spinlock \_name\()_errata_lock + \_name\()_errata_reported: + .word 0 + .popsection + + /* Place CPU string in rodata */ + .pushsection .rodata + \_name\()_cpu_str: + .asciz "\_name" + .popsection + .endif + + /* + * Weakly-bound, optional errata status printing function for CPUs of + * this class. + */ + .weak \_name\()_errata_report + .quad \_name\()_errata_report + +#ifdef IMAGE_BL31 + /* Pointers to errata lock and reported flag */ + .quad \_name\()_errata_lock + .quad \_name\()_errata_reported +#endif +#endif + #if defined(IMAGE_BL31) && CRASH_REPORTING .quad \_name\()_cpu_reg_dump #endif .endm +#if REPORT_ERRATA + /* + * Print status of a CPU errata + * + * _chosen: + * Identifier indicating whether or not a CPU errata has been + * compiled in. + * _cpu: + * Name of the CPU + * _id: + * Errata identifier + * _rev_var: + * Register containing the combined value CPU revision and variant + * - typically the return value of cpu_get_rev_var + */ + .macro report_errata _chosen, _cpu, _id, _rev_var=x8 + /* Stash a string with errata ID */ + .pushsection .rodata + \_cpu\()_errata_\_id\()_str: + .asciz "\_id" + .popsection + + /* Check whether errata applies */ + mov x0, \_rev_var + bl check_errata_\_id + + .ifeq \_chosen + /* + * Errata workaround has not been compiled in. If the errata would have + * applied had it been compiled in, print its status as missing. + */ + cbz x0, 900f + mov x0, #ERRATA_MISSING + .endif +900: + adr x1, \_cpu\()_cpu_str + adr x2, \_cpu\()_errata_\_id\()_str + bl errata_print_msg + .endm +#endif + #endif /* __CPU_MACROS_S__ */ diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index c7bee808..e0835337 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,10 +31,24 @@ #ifndef __DENVER_H__ #define __DENVER_H__ -/* MIDR for Denver v1.0 */ -#define DENVER_1_0_MIDR 0x4E0F0000 +/* MIDR values for Denver */ +#define DENVER_MIDR_PN0 0x4E0F0000 +#define DENVER_MIDR_PN1 0x4E0F0010 +#define DENVER_MIDR_PN2 0x4E0F0020 +#define DENVER_MIDR_PN3 0x4E0F0030 +#define DENVER_MIDR_PN4 0x4E0F0040 + +/* Implementer code in the MIDR register */ +#define DENVER_IMPL 0x4E /* CPU state ids - implementation defined */ #define DENVER_CPU_STATE_POWER_DOWN 0x3 +#ifndef __ASSEMBLY__ + +/* Disable Dynamic Code Optimisation */ +void denver_disable_dco(void); + +#endif + #endif /* __DENVER_H__ */ diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h new file mode 100644 index 00000000..6c6a844d --- /dev/null +++ b/include/lib/cpus/errata_report.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ERRATA_H__ +#define __ERRATA_H__ + +#ifndef __ASSEMBLY__ + +#include <arch.h> +#include <arch_helpers.h> +#include <spinlock.h> +#include <utils.h> + +#if DEBUG +void print_errata_status(void); +#else +static inline void print_errata_status(void) {} +#endif + +#endif /* __ASSEMBLY__ */ + +/* Errata status */ +#define ERRATA_NOT_APPLIES 0 +#define ERRATA_APPLIES 1 +#define ERRATA_MISSING 2 + +#endif /* __ERRATA_H__ */ + diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index 7c333875..d5415f4c 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h @@ -37,13 +37,13 @@ /* * Constants used for/by PMF services. */ -#define PMF_ARM_TIF_IMPL_ID (0x41000000) +#define PMF_ARM_TIF_IMPL_ID 0x41 #define PMF_TID_SHIFT 0 #define PMF_TID_MASK (0xFF << PMF_TID_SHIFT) #define PMF_SVC_ID_SHIFT 10 #define PMF_SVC_ID_MASK (0x3F << PMF_SVC_ID_SHIFT) #define PMF_IMPL_ID_SHIFT 24 -#define PMF_IMPL_ID_MASK (0xFF << PMF_IMPL_ID_SHIFT) +#define PMF_IMPL_ID_MASK (0xFFU << PMF_IMPL_ID_SHIFT) /* * Flags passed to PMF_REGISTER_SERVICE diff --git a/include/lib/smcc.h b/include/lib/smcc.h index c415ba10..2f562c5d 100644 --- a/include/lib/smcc.h +++ b/include/lib/smcc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,6 +31,8 @@ #ifndef __SMCC_H__ #define __SMCC_H__ +#include <utils.h> + /******************************************************************************* * Bit definitions inside the function id as per the SMC calling convention ******************************************************************************/ @@ -57,7 +59,7 @@ #define SMC_64 1 #define SMC_32 0 #define SMC_UNK 0xffffffff -#define SMC_TYPE_FAST 1 +#define SMC_TYPE_FAST ULL(1) #define SMC_TYPE_STD 0 #define SMC_PREEMPTED 0xfffffffe /******************************************************************************* diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h index cb0bc3e5..8273c784 100644 --- a/include/lib/spinlock.h +++ b/include/lib/spinlock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,11 +31,23 @@ #ifndef __SPINLOCK_H__ #define __SPINLOCK_H__ +#ifndef __ASSEMBLY__ + +#include <types.h> + typedef struct spinlock { - volatile unsigned int lock; + volatile uint32_t lock; } spinlock_t; void spin_lock(spinlock_t *lock); void spin_unlock(spinlock_t *lock); +#else + +/* Spin lock definitions for use in assembly */ +#define SPINLOCK_ASM_ALIGN 2 +#define SPINLOCK_ASM_SIZE 4 + +#endif + #endif /* __SPINLOCK_H__ */ diff --git a/include/lib/utils.h b/include/lib/utils.h index f7af8f66..69bbb430 100644 --- a/include/lib/utils.h +++ b/include/lib/utils.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -66,4 +66,49 @@ #define check_uptr_overflow(ptr, inc) \ (((ptr) > UINTPTR_MAX - (inc)) ? 1 : 0) +/* + * For those constants to be shared between C and other sources, apply a 'ull' + * suffix to the argument only in C, to avoid undefined or unintended behaviour. + * + * The GNU assembler and linker do not support the 'ull' suffix (it causes the + * build process to fail) therefore the suffix is omitted when used in linker + * scripts and assembler files. +*/ +#if defined(__LINKER__) || defined(__ASSEMBLY__) +# define ULL(_x) (_x) +#else +# define ULL(_x) (_x##ull) +#endif + +/* + * C code should be put in this part of the header to avoid breaking ASM files + * or linker scripts including it. + */ +#if !(defined(__LINKER__) || defined(__ASSEMBLY__)) + +#include <types.h> + +/* + * Fill a region of normal memory of size "length" in bytes with zero bytes. + * + * WARNING: This function can only operate on normal memory. This means that + * the MMU must be enabled when using this function. Otherwise, use + * zeromem. + */ +void zero_normalmem(void *mem, u_register_t length); + +/* + * Fill a region of memory of size "length" in bytes with null bytes. + * + * Unlike zero_normalmem, this function has no restriction on the type of + * memory targeted and can be used for any device memory as well as normal + * memory. This function must be used instead of zero_normalmem when MMU is + * disabled. + * + * NOTE: When data cache and MMU are enabled, prefer zero_normalmem for faster + * zeroing. + */ +void zeromem(void *mem, u_register_t length); +#endif /* !(defined(__LINKER__) || defined(__ASSEMBLY__)) */ + #endif /* __UTILS_H__ */ diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h index 975f1fc5..65e3d32d 100644 --- a/include/plat/arm/board/common/board_css_def.h +++ b/include/plat/arm/board/common/board_css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -68,7 +68,7 @@ * development platforms */ -#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x180000000) +#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) /* UART related constants */ #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 6d7bcd1e..4d264448 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -89,7 +89,7 @@ * - SCP TZC DRAM: If present, DRAM reserved for SCP use * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use */ -#define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000) +#define ARM_TZC_DRAM1_SIZE ULL(0x01000000) #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - \ @@ -113,12 +113,12 @@ #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ ARM_NS_DRAM1_SIZE - 1) -#define ARM_DRAM1_BASE MAKE_ULL(0x80000000) -#define ARM_DRAM1_SIZE MAKE_ULL(0x80000000) +#define ARM_DRAM1_BASE ULL(0x80000000) +#define ARM_DRAM1_SIZE ULL(0x80000000) #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - 1) -#define ARM_DRAM2_BASE MAKE_ULL(0x880000000) +#define ARM_DRAM2_BASE ULL(0x880000000) #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ ARM_DRAM2_SIZE - 1) diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index a2fe0d58..7cfaf59a 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -101,6 +101,13 @@ #define SSC_VERSION_DESIGNER_ID_MASK 0xff #define SSC_VERSION_PART_NUM_MASK 0xfff +/* SSC debug configuration registers */ +#define SSC_DBGCFG_SET 0x14 +#define SSC_DBGCFG_CLR 0x18 + +#define SPIDEN_INT_CLR_SHIFT 6 +#define SPIDEN_SEL_SET_SHIFT 7 + #ifndef __ASSEMBLY__ /* SSC_VERSION related accessors */ diff --git a/include/plat/arm/soc/common/soc_css_def.h b/include/plat/arm/soc/common/soc_css_def.h index f1396a6c..316f8f90 100644 --- a/include/plat/arm/soc/common/soc_css_def.h +++ b/include/plat/arm/soc/common/soc_css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -98,7 +98,7 @@ */ /* 2MB used for SCP DDR retraining */ -#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x00200000) +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000) #endif /* __SOC_CSS_DEF_H__ */ diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h index 65f31e7f..05588c13 100644 --- a/include/plat/common/common_def.h +++ b/include/plat/common/common_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -54,26 +54,6 @@ */ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" -/* - * Some of the platform porting definitions use the 'ull' suffix in order to - * avoid subtle integer overflow errors due to implicit integer type promotion - * when working with 32-bit values. - * - * The TSP linker script includes some of these definitions to define the BL32 - * memory map, but the GNU LD does not support the 'ull' suffix, causing the - * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x) - * will add the 'ull' suffix only when the macro __LINKER__ is not defined - * (__LINKER__ is defined in the command line to preprocess the linker script). - * Constants in the linker script will not have the 'ull' suffix, but this is - * not a problem since the linker evaluates all constant expressions to 64 bit - * (assuming the target architecture is 64 bit). - */ -#ifndef __LINKER__ - #define MAKE_ULL(x) x##ull -#else - #define MAKE_ULL(x) x -#endif - #if LOAD_IMAGE_V2 #define BL2_IMAGE_DESC { \ .image_id = BL2_IMAGE_ID, \ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index f904292b..73bb6431 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -254,6 +254,11 @@ const unsigned char *plat_get_power_domain_tree_desc(void); /******************************************************************************* * Optional PSCI functions (BL31). ******************************************************************************/ +void plat_psci_stat_accounting_start(const psci_power_state_t *state_info); +void plat_psci_stat_accounting_stop(const psci_power_state_t *state_info); +u_register_t plat_psci_stat_get_residency(unsigned int lvl, + const psci_power_state_t *state_info, + int last_cpu_index); plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, const plat_local_state_t *states, unsigned int ncpu); diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S index bf4084a8..dc847995 100644 --- a/lib/aarch32/misc_helpers.S +++ b/lib/aarch32/misc_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,6 +34,7 @@ .globl smc .globl zeromem + .globl zero_normalmem .globl memcpy4 .globl disable_mmu_icache_secure .globl disable_mmu_secure @@ -50,30 +51,108 @@ func smc endfunc smc /* ----------------------------------------------------------------------- - * void zeromem(void *mem, unsigned int length); + * void zeromem(void *mem, unsigned int length) + * + * Initialise a region in normal memory to 0. This functions complies with the + * AAPCS and can be called from C code. * - * Initialise a memory region to 0. - * The memory address and length must be 4-byte aligned. * ----------------------------------------------------------------------- */ func zeromem -#if ASM_ASSERTION - tst r0, #0x3 - ASM_ASSERT(eq) - tst r1, #0x3 - ASM_ASSERT(eq) -#endif - add r2, r0, r1 - mov r1, #0 -z_loop: - cmp r2, r0 - beq z_end - str r1, [r0], #4 - b z_loop -z_end: + /* + * Readable names for registers + * + * Registers r0, r1 and r2 are also set by zeromem which + * branches into the fallback path directly, so cursor, length and + * stop_address should not be retargeted to other registers. + */ + cursor .req r0 /* Start address and then current address */ + length .req r1 /* Length in bytes of the region to zero out */ + /* + * Reusing the r1 register as length is only used at the beginning of + * the function. + */ + stop_address .req r1 /* Address past the last zeroed byte */ + zeroreg1 .req r2 /* Source register filled with 0 */ + zeroreg2 .req r3 /* Source register filled with 0 */ + tmp .req r12 /* Temporary scratch register */ + + mov zeroreg1, #0 + + /* stop_address is the address past the last to zero */ + add stop_address, cursor, length + + /* + * Length cannot be used anymore as it shares the same register with + * stop_address. + */ + .unreq length + + /* + * If the start address is already aligned to 8 bytes, skip this loop. + */ + tst cursor, #(8-1) + beq .Lzeromem_8bytes_aligned + + /* Calculate the next address aligned to 8 bytes */ + orr tmp, cursor, #(8-1) + adds tmp, tmp, #1 + /* If it overflows, fallback to byte per byte zeroing */ + beq .Lzeromem_1byte_aligned + /* If the next aligned address is after the stop address, fall back */ + cmp tmp, stop_address + bhs .Lzeromem_1byte_aligned + + /* zero byte per byte */ +1: + strb zeroreg1, [cursor], #1 + cmp cursor, tmp + bne 1b + + /* zero 8 bytes at a time */ +.Lzeromem_8bytes_aligned: + + /* Calculate the last 8 bytes aligned address. */ + bic tmp, stop_address, #(8-1) + + cmp cursor, tmp + bhs 2f + + mov zeroreg2, #0 +1: + stmia cursor!, {zeroreg1, zeroreg2} + cmp cursor, tmp + blo 1b +2: + + /* zero byte per byte */ +.Lzeromem_1byte_aligned: + cmp cursor, stop_address + beq 2f +1: + strb zeroreg1, [cursor], #1 + cmp cursor, stop_address + bne 1b +2: bx lr + + .unreq cursor + /* + * length is already unreq'ed to reuse the register for another + * variable. + */ + .unreq stop_address + .unreq zeroreg1 + .unreq zeroreg2 + .unreq tmp endfunc zeromem +/* + * AArch32 does not have special ways of zeroing normal memory as AArch64 does + * using the DC ZVA instruction, so we just alias zero_normalmem to zeromem. + */ +.equ zero_normalmem, zeromem + /* -------------------------------------------------------------------------- * void memcpy4(void *dest, const void *src, unsigned int length) * diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S index 574146f6..84265e0b 100644 --- a/lib/aarch64/misc_helpers.S +++ b/lib/aarch64/misc_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -37,6 +37,8 @@ .globl eret .globl smc + .globl zero_normalmem + .globl zeromem .globl zeromem16 .globl memcpy16 @@ -80,31 +82,358 @@ endfunc smc * * Initialise a memory region to 0. * The memory address must be 16-byte aligned. + * NOTE: This function is deprecated and zeromem should be used instead. * ----------------------------------------------------------------------- */ -func zeromem16 +.equ zeromem16, zeromem + +/* ----------------------------------------------------------------------- + * void zero_normalmem(void *mem, unsigned int length); + * + * Initialise a region in normal memory to 0. This functions complies with the + * AAPCS and can be called from C code. + * + * NOTE: MMU must be enabled when using this function as it can only operate on + * normal memory. It is intended to be mainly used from C code when MMU + * is usually enabled. + * ----------------------------------------------------------------------- + */ +.equ zero_normalmem, zeromem_dczva + +/* ----------------------------------------------------------------------- + * void zeromem(void *mem, unsigned int length); + * + * Initialise a region of device memory to 0. This functions complies with the + * AAPCS and can be called from C code. + * + * NOTE: When data caches and MMU are enabled, zero_normalmem can usually be + * used instead for faster zeroing. + * + * ----------------------------------------------------------------------- + */ +func zeromem + /* x2 is the address past the last zeroed address */ + add x2, x0, x1 + /* + * Uses the fallback path that does not use DC ZVA instruction and + * therefore does not need enabled MMU + */ + b .Lzeromem_dczva_fallback_entry +endfunc zeromem + +/* ----------------------------------------------------------------------- + * void zeromem_dczva(void *mem, unsigned int length); + * + * Fill a region of normal memory of size "length" in bytes with null bytes. + * MMU must be enabled and the memory be of + * normal type. This is because this function internally uses the DC ZVA + * instruction, which generates an Alignment fault if used on any type of + * Device memory (see section D3.4.9 of the ARMv8 ARM, issue k). When the MMU + * is disabled, all memory behaves like Device-nGnRnE memory (see section + * D4.2.8), hence the requirement on the MMU being enabled. + * NOTE: The code assumes that the block size as defined in DCZID_EL0 + * register is at least 16 bytes. + * + * ----------------------------------------------------------------------- + */ +func zeromem_dczva + + /* + * The function consists of a series of loops that zero memory one byte + * at a time, 16 bytes at a time or using the DC ZVA instruction to + * zero aligned block of bytes, which is assumed to be more than 16. + * In the case where the DC ZVA instruction cannot be used or if the + * first 16 bytes loop would overflow, there is fallback path that does + * not use DC ZVA. + * Note: The fallback path is also used by the zeromem function that + * branches to it directly. + * + * +---------+ zeromem_dczva + * | entry | + * +----+----+ + * | + * v + * +---------+ + * | checks |>o-------+ (If any check fails, fallback) + * +----+----+ | + * | |---------------+ + * v | Fallback path | + * +------+------+ |---------------+ + * | 1 byte loop | | + * +------+------+ .Lzeromem_dczva_initial_1byte_aligned_end + * | | + * v | + * +-------+-------+ | + * | 16 bytes loop | | + * +-------+-------+ | + * | | + * v | + * +------+------+ .Lzeromem_dczva_blocksize_aligned + * | DC ZVA loop | | + * +------+------+ | + * +--------+ | | + * | | | | + * | v v | + * | +-------+-------+ .Lzeromem_dczva_final_16bytes_aligned + * | | 16 bytes loop | | + * | +-------+-------+ | + * | | | + * | v | + * | +------+------+ .Lzeromem_dczva_final_1byte_aligned + * | | 1 byte loop | | + * | +-------------+ | + * | | | + * | v | + * | +---+--+ | + * | | exit | | + * | +------+ | + * | | + * | +--------------+ +------------------+ zeromem + * | | +----------------| zeromem function | + * | | | +------------------+ + * | v v + * | +-------------+ .Lzeromem_dczva_fallback_entry + * | | 1 byte loop | + * | +------+------+ + * | | + * +-----------+ + */ + + /* + * Readable names for registers + * + * Registers x0, x1 and x2 are also set by zeromem which + * branches into the fallback path directly, so cursor, length and + * stop_address should not be retargeted to other registers. + */ + cursor .req x0 /* Start address and then current address */ + length .req x1 /* Length in bytes of the region to zero out */ + /* Reusing x1 as length is never used after block_mask is set */ + block_mask .req x1 /* Bitmask of the block size read in DCZID_EL0 */ + stop_address .req x2 /* Address past the last zeroed byte */ + block_size .req x3 /* Size of a block in bytes as read in DCZID_EL0 */ + tmp1 .req x4 + tmp2 .req x5 + #if ASM_ASSERTION - tst x0, #0xf - ASM_ASSERT(eq) + /* + * Check for M bit (MMU enabled) of the current SCTLR_EL(1|3) + * register value and panic if the MMU is disabled. + */ +#if defined(IMAGE_BL1) || defined(IMAGE_BL31) + mrs tmp1, sctlr_el3 +#else + mrs tmp1, sctlr_el1 #endif - add x2, x0, x1 -/* zero 16 bytes at a time */ -z_loop16: - sub x3, x2, x0 - cmp x3, #16 - b.lt z_loop1 - stp xzr, xzr, [x0], #16 - b z_loop16 -/* zero byte per byte */ -z_loop1: - cmp x0, x2 - b.eq z_end - strb wzr, [x0], #1 - b z_loop1 -z_end: + + tst tmp1, #SCTLR_M_BIT + ASM_ASSERT(ne) +#endif /* ASM_ASSERTION */ + + /* stop_address is the address past the last to zero */ + add stop_address, cursor, length + + /* + * Get block_size = (log2(<block size>) >> 2) (see encoding of + * dczid_el0 reg) + */ + mrs block_size, dczid_el0 + + /* + * Select the 4 lowest bits and convert the extracted log2(<block size + * in words>) to <block size in bytes> + */ + ubfx block_size, block_size, #0, #4 + mov tmp2, #(1 << 2) + lsl block_size, tmp2, block_size + +#if ASM_ASSERTION + /* + * Assumes block size is at least 16 bytes to avoid manual realignment + * of the cursor at the end of the DCZVA loop. + */ + cmp block_size, #16 + ASM_ASSERT(hs) +#endif + /* + * Not worth doing all the setup for a region less than a block and + * protects against zeroing a whole block when the area to zero is + * smaller than that. Also, as it is assumed that the block size is at + * least 16 bytes, this also protects the initial aligning loops from + * trying to zero 16 bytes when length is less than 16. + */ + cmp length, block_size + b.lo .Lzeromem_dczva_fallback_entry + + /* + * Calculate the bitmask of the block alignment. It will never + * underflow as the block size is between 4 bytes and 2kB. + * block_mask = block_size - 1 + */ + sub block_mask, block_size, #1 + + /* + * length alias should not be used after this point unless it is + * defined as a register other than block_mask's. + */ + .unreq length + + /* + * If the start address is already aligned to zero block size, go + * straight to the cache zeroing loop. This is safe because at this + * point, the length cannot be smaller than a block size. + */ + tst cursor, block_mask + b.eq .Lzeromem_dczva_blocksize_aligned + + /* + * Calculate the first block-size-aligned address. It is assumed that + * the zero block size is at least 16 bytes. This address is the last + * address of this initial loop. + */ + orr tmp1, cursor, block_mask + add tmp1, tmp1, #1 + + /* + * If the addition overflows, skip the cache zeroing loops. This is + * quite unlikely however. + */ + cbz tmp1, .Lzeromem_dczva_fallback_entry + + /* + * If the first block-size-aligned address is past the last address, + * fallback to the simpler code. + */ + cmp tmp1, stop_address + b.hi .Lzeromem_dczva_fallback_entry + + /* + * If the start address is already aligned to 16 bytes, skip this loop. + * It is safe to do this because tmp1 (the stop address of the initial + * 16 bytes loop) will never be greater than the final stop address. + */ + tst cursor, #0xf + b.eq .Lzeromem_dczva_initial_1byte_aligned_end + + /* Calculate the next address aligned to 16 bytes */ + orr tmp2, cursor, #0xf + add tmp2, tmp2, #1 + /* If it overflows, fallback to the simple path (unlikely) */ + cbz tmp2, .Lzeromem_dczva_fallback_entry + /* + * Next aligned address cannot be after the stop address because the + * length cannot be smaller than 16 at this point. + */ + + /* First loop: zero byte per byte */ +1: + strb wzr, [cursor], #1 + cmp cursor, tmp2 + b.ne 1b +.Lzeromem_dczva_initial_1byte_aligned_end: + + /* + * Second loop: we need to zero 16 bytes at a time from cursor to tmp1 + * before being able to use the code that deals with block-size-aligned + * addresses. + */ + cmp cursor, tmp1 + b.hs 2f +1: + stp xzr, xzr, [cursor], #16 + cmp cursor, tmp1 + b.lo 1b +2: + + /* + * Third loop: zero a block at a time using DC ZVA cache block zeroing + * instruction. + */ +.Lzeromem_dczva_blocksize_aligned: + /* + * Calculate the last block-size-aligned address. If the result equals + * to the start address, the loop will exit immediately. + */ + bic tmp1, stop_address, block_mask + + cmp cursor, tmp1 + b.hs 2f +1: + /* Zero the block containing the cursor */ + dc zva, cursor + /* Increment the cursor by the size of a block */ + add cursor, cursor, block_size + cmp cursor, tmp1 + b.lo 1b +2: + + /* + * Fourth loop: zero 16 bytes at a time and then byte per byte the + * remaining area + */ +.Lzeromem_dczva_final_16bytes_aligned: + /* + * Calculate the last 16 bytes aligned address. It is assumed that the + * block size will never be smaller than 16 bytes so that the current + * cursor is aligned to at least 16 bytes boundary. + */ + bic tmp1, stop_address, #15 + + cmp cursor, tmp1 + b.hs 2f +1: + stp xzr, xzr, [cursor], #16 + cmp cursor, tmp1 + b.lo 1b +2: + + /* Fifth and final loop: zero byte per byte */ +.Lzeromem_dczva_final_1byte_aligned: + cmp cursor, stop_address + b.eq 2f +1: + strb wzr, [cursor], #1 + cmp cursor, stop_address + b.ne 1b +2: ret -endfunc zeromem16 + /* Fallback for unaligned start addresses */ +.Lzeromem_dczva_fallback_entry: + /* + * If the start address is already aligned to 16 bytes, skip this loop. + */ + tst cursor, #0xf + b.eq .Lzeromem_dczva_final_16bytes_aligned + + /* Calculate the next address aligned to 16 bytes */ + orr tmp1, cursor, #15 + add tmp1, tmp1, #1 + /* If it overflows, fallback to byte per byte zeroing */ + cbz tmp1, .Lzeromem_dczva_final_1byte_aligned + /* If the next aligned address is after the stop address, fall back */ + cmp tmp1, stop_address + b.hs .Lzeromem_dczva_final_1byte_aligned + + /* Fallback entry loop: zero byte per byte */ +1: + strb wzr, [cursor], #1 + cmp cursor, tmp1 + b.ne 1b + + b .Lzeromem_dczva_final_16bytes_aligned + + .unreq cursor + /* + * length is already unreq'ed to reuse the register for another + * variable. + */ + .unreq stop_address + .unreq block_size + .unreq block_mask + .unreq tmp1 + .unreq tmp2 +endfunc zeromem_dczva /* -------------------------------------------------------------------------- * void memcpy16(void *dest, const void *src, unsigned int length) diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S index d8cabfe5..c41978ed 100644 --- a/lib/cpus/aarch32/cpu_helpers.S +++ b/lib/cpus/aarch32/cpu_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -172,3 +172,86 @@ func get_cpu_ops_ptr error_exit: bx lr endfunc get_cpu_ops_ptr + +/* + * Extract CPU revision and variant, and combine them into a single numeric for + * easier comparison. + */ + .globl cpu_get_rev_var +func cpu_get_rev_var + ldcopr r1, MIDR + + /* + * Extract the variant[23:20] and revision[3:0] from r1 and pack it in + * r0[0:7] as variant[7:4] and revision[3:0]: + * + * First extract r1[23:16] to r0[7:0] and zero fill the rest. Then + * extract r1[3:0] into r0[3:0] retaining other bits. + */ + ubfx r0, r1, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) + bfi r0, r1, #MIDR_REV_SHIFT, #MIDR_REV_BITS + bx lr +endfunc cpu_get_rev_var + +/* + * Compare the CPU's revision-variant (r0) with a given value (r1), for errata + * application purposes. If the revision-variant is less than or same as a given + * value, indicates that errata applies; otherwise not. + */ + .globl cpu_rev_var_ls +func cpu_rev_var_ls + cmp r0, r1 + movls r0, #ERRATA_APPLIES + movhi r0, #ERRATA_NOT_APPLIES + bx lr +endfunc cpu_rev_var_ls + +#if REPORT_ERRATA +/* + * void print_errata_status(void); + * + * Function to print errata status for CPUs of its class. Must be called only: + * + * - with MMU and data caches are enabled; + * - after cpu_ops have been initialized in per-CPU data. + */ + .globl print_errata_status +func print_errata_status + push {r4, lr} +#ifdef IMAGE_BL1 + /* + * BL1 doesn't have per-CPU data. So retrieve the CPU operations + * directly. + */ + bl get_cpu_ops_ptr + ldr r0, [r0, #CPU_ERRATA_FUNC] + cmp r0, #0 + blxne r0 +#else + /* + * Retrieve pointer to cpu_ops, and further, the errata printing + * function. If it's non-NULL, jump to the function in turn. + */ + bl _cpu_data + ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] + ldr r0, [r1, #CPU_ERRATA_FUNC] + cmp r0, #0 + beq 1f + + mov r4, r0 + + /* + * Load pointers to errata lock and printed flag. Call + * errata_needs_reporting to check whether this CPU needs to report + * errata status pertaining to its class. + */ + ldr r0, [r1, #CPU_ERRATA_LOCK] + ldr r1, [r1, #CPU_ERRATA_PRINTED] + bl errata_needs_reporting + cmp r0, #0 + blxne r4 +1: +#endif + pop {r4, pc} +endfunc print_errata_status +#endif diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 06be9ce6..1dd8a865 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,6 +35,11 @@ #include <debug.h> #include <plat_macros.S> +#if A53_DISABLE_NON_TEMPORAL_HINT +#undef ERRATA_A53_836870 +#define ERRATA_A53_836870 1 +#endif + /* --------------------------------------------- * Disable L1 data cache and unified L2 cache * --------------------------------------------- @@ -65,28 +70,29 @@ endfunc cortex_a53_disable_smp * This applies only to revision <= r0p2 of Cortex A53. * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5 + * Shall clobber: x0-x17 * -------------------------------------------------- */ func errata_a53_826319_wa /* * Compare x0 against revision r0p2 */ - cmp x0, #2 - b.ls apply_826319 -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -apply_826319: + mov x17, x30 + bl check_errata_826319 + cbz x0, 1f mrs x1, L2ACTLR_EL1 bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH msr L2ACTLR_EL1, x1 - ret +1: + ret x17 endfunc errata_a53_826319_wa +func check_errata_826319 + mov x1, #0x02 + b cpu_rev_var_ls +endfunc check_errata_826319 + /* --------------------------------------------------------------------- * Disable the cache non-temporal hint. * @@ -101,53 +107,46 @@ endfunc errata_a53_826319_wa * * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5 + * Shall clobber: x0-x17 * --------------------------------------------------------------------- */ func a53_disable_non_temporal_hint /* * Compare x0 against revision r0p3 */ - cmp x0, #3 - b.ls disable_hint -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -disable_hint: + mov x17, x30 + bl check_errata_disable_non_temporal_hint + cbz x0, 1f mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_DTAH msr CPUACTLR_EL1, x1 - ret +1: + ret x17 endfunc a53_disable_non_temporal_hint +func check_errata_disable_non_temporal_hint + mov x1, #0x03 + b cpu_rev_var_ls +endfunc check_errata_disable_non_temporal_hint + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A53. - * Clobbers: x0-x5, x15, x19, x30 + * Shall clobber: x0-x19 * ------------------------------------------------- */ func cortex_a53_reset_func mov x19, x30 - mrs x0, midr_el1 + bl cpu_get_rev_var + mov x18, x0 - /* - * Extract the variant[20:23] and revision[0:3] from x0 - * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. - * First extract x0[16:23] to x15[0:7] and zero fill the rest. - * Then extract x0[0:3] into x15[0:3] retaining other bits. - */ - ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), \ - #(MIDR_REV_BITS + MIDR_VAR_BITS) - bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS #if ERRATA_A53_826319 - mov x0, x15 + mov x0, x18 bl errata_a53_826319_wa #endif -#if ERRATA_A53_836870 || A53_DISABLE_NON_TEMPORAL_HINT - mov x0, x15 +#if ERRATA_A53_836870 + mov x0, x18 bl a53_disable_non_temporal_hint #endif @@ -223,6 +222,28 @@ func cortex_a53_cluster_pwr_dwn b cortex_a53_disable_smp endfunc cortex_a53_cluster_pwr_dwn +#if REPORT_ERRATA +/* + * Errata printing function for Cortex A53. Must follow AAPCS. + */ +func cortex_a53_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_A53_826319, cortex_a53, 826319 + report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_a53_errata_report +#endif + /* --------------------------------------------- * This function provides cortex_a53 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index e531b1e3..ffdc9309 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -92,52 +92,55 @@ endfunc cortex_a57_disable_ext_debug * This applies only to revision r0p0 of Cortex A57. * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5 + * Shall clobber: x0-x17 * -------------------------------------------------- */ func errata_a57_806969_wa /* * Compare x0 against revision r0p0 */ - cbz x0, apply_806969 -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -apply_806969: + mov x17, x30 + bl check_errata_806969 + cbz x0, 1f mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA msr CPUACTLR_EL1, x1 - ret +1: + ret x17 endfunc errata_a57_806969_wa +func check_errata_806969 + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_806969 /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #813420. * This applies only to revision r0p0 of Cortex A57. * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5 + * Shall clobber: x0-x17 * --------------------------------------------------- */ func errata_a57_813420_wa /* * Compare x0 against revision r0p0 */ - cbz x0, apply_813420 -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -apply_813420: + mov x17, x30 + bl check_errata_813420 + cbz x0, 1f mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_DCC_AS_DCCI msr CPUACTLR_EL1, x1 - ret +1: + ret x17 endfunc errata_a57_813420_wa +func check_errata_813420 + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_813420 + /* -------------------------------------------------------------------- * Disable the over-read from the LDNP instruction. * @@ -146,99 +149,97 @@ endfunc errata_a57_813420_wa * * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5, x30 + * Shall clobber: x0-x17 * --------------------------------------------------------------------- */ func a57_disable_ldnp_overread /* * Compare x0 against revision r1p2 */ - cmp x0, #0x12 - b.ls disable_hint -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -disable_hint: + mov x17, x30 + bl check_errata_disable_ldnp_overread + cbz x0, 1f mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_DIS_OVERREAD msr CPUACTLR_EL1, x1 - ret +1: + ret x17 endfunc a57_disable_ldnp_overread +func check_errata_disable_ldnp_overread + mov x1, #0x12 + b cpu_rev_var_ls +endfunc check_errata_disable_ldnp_overread + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #826974. * This applies only to revision <= r1p1 of Cortex A57. * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5 + * Shall clobber: x0-x17 * --------------------------------------------------- */ func errata_a57_826974_wa /* * Compare x0 against revision r1p1 */ - cmp x0, #0x11 - b.ls apply_826974 -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -apply_826974: + mov x17, x30 + bl check_errata_826974 + cbz x0, 1f mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB msr CPUACTLR_EL1, x1 - ret +1: + ret x17 endfunc errata_a57_826974_wa +func check_errata_826974 + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_826974 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #826977. * This applies only to revision <= r1p1 of Cortex A57. * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5 + * Shall clobber: x0-x17 * --------------------------------------------------- */ func errata_a57_826977_wa /* * Compare x0 against revision r1p1 */ - cmp x0, #0x11 - b.ls apply_826977 -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -apply_826977: + mov x17, x30 + bl check_errata_826977 + cbz x0, 1f mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE msr CPUACTLR_EL1, x1 - ret +1: + ret x17 endfunc errata_a57_826977_wa +func check_errata_826977 + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_826977 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #828024. * This applies only to revision <= r1p1 of Cortex A57. * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5 + * Shall clobber: x0-x17 * --------------------------------------------------- */ func errata_a57_828024_wa /* * Compare x0 against revision r1p1 */ - cmp x0, #0x11 - b.ls apply_828024 -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -apply_828024: + mov x17, x30 + bl check_errata_828024 + cbz x0, 1f mrs x1, CPUACTLR_EL1 /* * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 @@ -248,116 +249,116 @@ apply_828024: orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) msr CPUACTLR_EL1, x1 - ret +1: + ret x17 endfunc errata_a57_828024_wa +func check_errata_828024 + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_828024 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #829520. * This applies only to revision <= r1p2 of Cortex A57. * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5 + * Shall clobber: x0-x17 * --------------------------------------------------- */ func errata_a57_829520_wa /* * Compare x0 against revision r1p2 */ - cmp x0, #0x12 - b.ls apply_829520 -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -apply_829520: + mov x17, x30 + bl check_errata_829520 + cbz x0, 1f mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR msr CPUACTLR_EL1, x1 - ret +1: + ret x17 endfunc errata_a57_829520_wa +func check_errata_829520 + mov x1, #0x12 + b cpu_rev_var_ls +endfunc check_errata_829520 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #833471. * This applies only to revision <= r1p2 of Cortex A57. * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. - * Clobbers : x0 - x5 + * Shall clobber: x0-x17 * --------------------------------------------------- */ func errata_a57_833471_wa /* * Compare x0 against revision r1p2 */ - cmp x0, #0x12 - b.ls apply_833471 -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - b print_revision_warning -#else - ret -#endif -apply_833471: + mov x17, x30 + bl check_errata_833471 + cbz x0, 1f mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH msr CPUACTLR_EL1, x1 - ret +1: + ret x17 endfunc errata_a57_833471_wa +func check_errata_833471 + mov x1, #0x12 + b cpu_rev_var_ls +endfunc check_errata_833471 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. - * Clobbers: x0-x5, x15, x19, x30 + * Shall clobber: x0-x19 * ------------------------------------------------- */ func cortex_a57_reset_func mov x19, x30 - mrs x0, midr_el1 - - /* - * Extract the variant[20:23] and revision[0:3] from x0 - * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. - * First extract x0[16:23] to x15[0:7] and zero fill the rest. - * Then extract x0[0:3] into x15[0:3] retaining other bits. - */ - ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) - bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS + bl cpu_get_rev_var + mov x18, x0 #if ERRATA_A57_806969 - mov x0, x15 + mov x0, x18 bl errata_a57_806969_wa #endif #if ERRATA_A57_813420 - mov x0, x15 + mov x0, x18 bl errata_a57_813420_wa #endif #if A57_DISABLE_NON_TEMPORAL_HINT - mov x0, x15 + mov x0, x18 bl a57_disable_ldnp_overread #endif #if ERRATA_A57_826974 - mov x0, x15 + mov x0, x18 bl errata_a57_826974_wa #endif #if ERRATA_A57_826977 - mov x0, x15 + mov x0, x18 bl errata_a57_826977_wa #endif #if ERRATA_A57_828024 - mov x0, x15 + mov x0, x18 bl errata_a57_828024_wa #endif #if ERRATA_A57_829520 - mov x0, x15 + mov x0, x18 bl errata_a57_829520_wa #endif #if ERRATA_A57_833471 - mov x0, x15 + mov x0, x18 bl errata_a57_833471_wa #endif @@ -466,6 +467,35 @@ func cortex_a57_cluster_pwr_dwn b cortex_a57_disable_ext_debug endfunc cortex_a57_cluster_pwr_dwn +#if REPORT_ERRATA +/* + * Errata printing function for Cortex A57. Must follow AAPCS. + */ +func cortex_a57_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_A57_806969, cortex_a57, 806969 + report_errata ERRATA_A57_813420, cortex_a57, 813420 + report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ + disable_ldnp_overread + report_errata ERRATA_A57_826974, cortex_a57, 826974 + report_errata ERRATA_A57_826977, cortex_a57, 826977 + report_errata ERRATA_A57_828024, cortex_a57, 828024 + report_errata ERRATA_A57_829520, cortex_a57, 829520 + report_errata ERRATA_A57_833471, cortex_a57, 833471 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_a57_errata_report +#endif + /* --------------------------------------------- * This function provides cortex_a57 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 7365d35e..6a3669de 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -36,6 +36,7 @@ #endif #include <cpu_macros.S> #include <debug.h> +#include <errata_report.h> /* Reset fn is needed in BL at reset vector */ #if defined(IMAGE_BL1) || defined(IMAGE_BL31) @@ -199,30 +200,94 @@ error_exit: ret endfunc get_cpu_ops_ptr -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE -.section .rodata.rev_verbose_str, "aS" -rev_verbose_str: - .asciz "VERBOSE: Skipping CPU specific reset operation for non-matching CPU revision number.\n" +/* + * Extract CPU revision and variant, and combine them into a single numeric for + * easier comparison. + */ + .globl cpu_get_rev_var +func cpu_get_rev_var + mrs x1, midr_el1 /* - * This function prints the above warning message to the crash console. - * It should be called when a CPU specific operation is enabled in the - * build but doesn't apply to this CPU revision/part number. + * Extract the variant[23:20] and revision[3:0] from MIDR, and pack them + * as variant[7:4] and revision[3:0] of x0. * - * Clobber: x30, x0 - x5 + * First extract x1[23:16] to x0[7:0] and zero fill the rest. Then + * extract x1[3:0] into x0[3:0] retaining other bits. */ - .globl print_revision_warning -func print_revision_warning - mov x5, x30 - /* Ensure the console is initialized */ - bl plat_crash_console_init - /* Check if the console is initialized */ - cbz x0, 1f - /* The console is initialized */ - adr x4, rev_verbose_str - bl asm_print_str -1: - ret x5 -endfunc print_revision_warning -#endif + ubfx x0, x1, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) + bfxil x0, x1, #MIDR_REV_SHIFT, #MIDR_REV_BITS + ret +endfunc cpu_get_rev_var +/* + * Compare the CPU's revision-variant (x0) with a given value (x1), for errata + * application purposes. If the revision-variant is less than or same as a given + * value, indicates that errata applies; otherwise not. + */ + .globl cpu_rev_var_ls +func cpu_rev_var_ls + mov x2, #ERRATA_APPLIES + mov x3, #ERRATA_NOT_APPLIES + cmp x0, x1 + csel x0, x2, x3, ls + ret +endfunc cpu_rev_var_ls + +#if REPORT_ERRATA +/* + * void print_errata_status(void); + * + * Function to print errata status for CPUs of its class. Must be called only: + * + * - with MMU and data caches are enabled; + * - after cpu_ops have been initialized in per-CPU data. + */ + .globl print_errata_status +func print_errata_status +#ifdef IMAGE_BL1 + /* + * BL1 doesn't have per-CPU data. So retrieve the CPU operations + * directly. + */ + stp xzr, x30, [sp, #-16]! + bl get_cpu_ops_ptr + ldp xzr, x30, [sp], #16 + ldr x1, [x0, #CPU_ERRATA_FUNC] + cbnz x1, .Lprint +#else + /* + * Retrieve pointer to cpu_ops from per-CPU data, and further, the + * errata printing function. If it's non-NULL, jump to the function in + * turn. + */ + mrs x0, tpidr_el3 + ldr x1, [x0, #CPU_DATA_CPU_OPS_PTR] + ldr x0, [x1, #CPU_ERRATA_FUNC] + cbz x0, .Lnoprint + + /* + * Printing errata status requires atomically testing the printed flag. + */ + stp x8, x30, [sp, #-16]! + mov x8, x0 + + /* + * Load pointers to errata lock and printed flag. Call + * errata_needs_reporting to check whether this CPU needs to report + * errata status pertaining to its class. + */ + ldr x0, [x1, #CPU_ERRATA_LOCK] + ldr x1, [x1, #CPU_ERRATA_PRINTED] + bl errata_needs_reporting + mov x1, x8 + ldp x8, x30, [sp], #16 + cbnz x0, .Lprint +#endif +.Lnoprint: + ret +.Lprint: + /* Jump to errata reporting function for this CPU */ + br x1 +endfunc print_errata_status +#endif diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index 0b61440d..3e238a1c 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,6 +35,8 @@ #include <cpu_macros.S> #include <plat_macros.S> + .global denver_disable_dco + /* --------------------------------------------- * Disable debug interfaces * --------------------------------------------- @@ -111,22 +113,6 @@ func denver_core_pwr_dwn mov x19, x30 - /* ---------------------------------------------------- - * We enter the 'core power gated with ARM state not - * retained' power state during CPU power down. We let - * DCO know that we expect to enter this power state - * by writing to the ACTLR_EL1 register. - * ---------------------------------------------------- - */ - mov x0, #DENVER_CPU_STATE_POWER_DOWN - msr actlr_el1, x0 - - /* --------------------------------------------- - * Force DCO to be quiescent - * --------------------------------------------- - */ - bl denver_disable_dco - /* --------------------------------------------- * Force the debug interfaces to be quiescent * --------------------------------------------- @@ -163,7 +149,27 @@ func denver_cpu_reg_dump ret endfunc denver_cpu_reg_dump -declare_cpu_ops denver, DENVER_1_0_MIDR, \ +declare_cpu_ops denver, DENVER_MIDR_PN0, \ + denver_reset_func, \ + denver_core_pwr_dwn, \ + denver_cluster_pwr_dwn + +declare_cpu_ops denver, DENVER_MIDR_PN1, \ + denver_reset_func, \ + denver_core_pwr_dwn, \ + denver_cluster_pwr_dwn + +declare_cpu_ops denver, DENVER_MIDR_PN2, \ + denver_reset_func, \ + denver_core_pwr_dwn, \ + denver_cluster_pwr_dwn + +declare_cpu_ops denver, DENVER_MIDR_PN3, \ + denver_reset_func, \ + denver_core_pwr_dwn, \ + denver_cluster_pwr_dwn + +declare_cpu_ops denver, DENVER_MIDR_PN4, \ denver_reset_func, \ denver_core_pwr_dwn, \ denver_cluster_pwr_dwn diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c new file mode 100644 index 00000000..29b26c2e --- /dev/null +++ b/lib/cpus/errata_report.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* Runtime firmware routines to report errata status for the current CPU. */ + +#include <arch_helpers.h> +#include <assert.h> +#include <cpu_data.h> +#include <debug.h> +#include <errata_report.h> +#include <spinlock.h> +#include <utils.h> + +#ifdef IMAGE_BL1 +# define BL_STRING "BL1" +#elif defined(AARCH64) && defined(IMAGE_BL31) +# define BL_STRING "BL31" +#elif defined(AARCH32) && defined(IMAGE_BL32) +# define BL_STRING "BL32" +#else +# error This image should not be printing errata status +#endif + +/* Errata format: BL stage, CPU, errata ID, message */ +#define ERRATA_FORMAT "%s: %s: errata workaround for %s was %s\n" + +/* + * Returns whether errata needs to be reported. Passed arguments are private to + * a CPU type. + */ +int errata_needs_reporting(spinlock_t *lock, uint32_t *reported) +{ + int report_now; + + /* If already reported, return false. */ + if (*reported) + return 0; + + /* + * Acquire lock. Determine whether status needs reporting, and then mark + * report status to true. + */ + spin_lock(lock); + report_now = !(*reported); + if (report_now) + *reported = 1; + spin_unlock(lock); + + return report_now; +} + +/* + * Print errata status message. + * + * Unknown: WARN + * Missing: WARN + * Applied: INFO + * Not applied: VERBOSE + */ +void errata_print_msg(int status, const char *cpu, const char *id) +{ + /* Errata status strings */ + static const char *const errata_status_str[] = { + [ERRATA_NOT_APPLIES] = "not applied", + [ERRATA_APPLIES] = "applied", + [ERRATA_MISSING] = "missing!" + }; + static const char *const __unused bl_str = BL_STRING; + const char *msg __unused; + + + assert(status >= 0 && status < ARRAY_SIZE(errata_status_str)); + assert(cpu); + assert(id); + + msg = errata_status_str[status]; + + switch (status) { + case ERRATA_NOT_APPLIES: + VERBOSE(ERRATA_FORMAT, bl_str, cpu, id, msg); + break; + + case ERRATA_APPLIES: + INFO(ERRATA_FORMAT, bl_str, cpu, id, msg); + break; + + case ERRATA_MISSING: + WARN(ERRATA_FORMAT, bl_str, cpu, id, msg); + break; + + default: + WARN(ERRATA_FORMAT, bl_str, cpu, id, "unknown"); + break; + } +} diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index 51b77595..df22eaf5 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -38,6 +38,7 @@ #include <platform_def.h> #include <smcc_helpers.h> #include <string.h> +#include <utils.h> /******************************************************************************* * Context management library initialisation routine. This library is used by @@ -84,7 +85,7 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t security_state = GET_SECURITY_STATE(ep->h.attr); /* Clear any residual register values from the context */ - memset(ctx, 0, sizeof(*ctx)); + zeromem(ctx, sizeof(*ctx)); reg_ctx = get_regs_ctx(ctx); diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index e26950df..5cce8793 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -39,6 +39,7 @@ #include <platform_def.h> #include <smcc_helpers.h> #include <string.h> +#include <utils.h> /******************************************************************************* @@ -91,7 +92,7 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t security_state = GET_SECURITY_STATE(ep->h.attr); /* Clear any residual register values from the context */ - memset(ctx, 0, sizeof(*ctx)); + zeromem(ctx, sizeof(*ctx)); /* * Base the context SCR on the current value, adjust for entry point diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S index 1ca59123..bdc9ea0f 100644 --- a/lib/locks/exclusive/aarch64/spinlock.S +++ b/lib/locks/exclusive/aarch64/spinlock.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,7 +33,66 @@ .globl spin_lock .globl spin_unlock +#if (ARM_ARCH_MAJOR > 8) || ((ARM_ARCH_MAJOR == 8) && (ARM_ARCH_MINOR >= 1)) +/* + * When compiled for ARMv8.1 or later, choose spin locks based on Compare and + * Swap instruction. + */ +# define USE_CAS 1 + +/* + * Lock contenders using CAS, upon failing to acquire the lock, wait with the + * monitor in open state. Therefore, a normal store upon unlocking won't + * generate an SEV. Use explicit SEV instruction with CAS unlock. + */ +# define COND_SEV() sev + +#else + +# define USE_CAS 0 + +/* + * Lock contenders using exclusive pairs, upon failing to acquire the lock, wait + * with the monitor in exclusive state. A normal store upon unlocking will + * implicitly generate an envent; so, no explicit SEV with unlock is required. + */ +# define COND_SEV() + +#endif + +#if USE_CAS + + .arch armv8.1-a + +/* + * Acquire lock using Compare and Swap instruction. + * + * Compare for 0 with acquire semantics, and swap 1. Wait until CAS returns + * 0. + * + * void spin_lock(spinlock_t *lock); + */ +func spin_lock + mov w2, #1 + sevl +1: + wfe + mov w1, wzr + casa w1, w2, [x0] + cbnz w1, 1b + ret +endfunc spin_lock + + .arch armv8-a + +#else /* !USE_CAS */ + +/* + * Acquire lock using load-/store-exclusive instruction pair. + * + * void spin_lock(spinlock_t *lock); + */ func spin_lock mov w2, #1 sevl @@ -45,8 +104,17 @@ l2: ldaxr w1, [x0] ret endfunc spin_lock +#endif /* USE_CAS */ +/* + * Release lock previously acquired by spin_lock. + * + * Unconditionally write 0, and conditionally generate an event. + * + * void spin_unlock(spinlock_t *lock); + */ func spin_unlock stlr wzr, [x0] + COND_SEV() ret endfunc spin_unlock diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 68cdd6eb..9fdce498 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -37,6 +37,7 @@ #include <debug.h> #include <platform.h> #include <string.h> +#include <utils.h> #include "psci_private.h" /* @@ -622,7 +623,7 @@ static int psci_get_ns_ep_info(entry_point_info_t *ep, SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); ep->pc = entrypoint; - memset(&ep->args, 0, sizeof(ep->args)); + zeromem(&ep->args, sizeof(ep->args)); ep->args.arg0 = context_id; mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; @@ -659,7 +660,7 @@ static int psci_get_ns_ep_info(entry_point_info_t *ep, SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); ep->pc = entrypoint; - memset(&ep->args, 0, sizeof(ep->args)); + zeromem(&ep->args, sizeof(ep->args)); ep->args.arg0 = context_id; /* @@ -760,13 +761,7 @@ void psci_warmboot_entrypoint(void) cpu_idx); #if ENABLE_PSCI_STAT - /* - * Capture power up time-stamp. - * No cache maintenance is required as caches are off - * and writes are direct to the main memory. - */ - PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR, - PMF_NO_CACHE_MAINT); + plat_psci_stat_accounting_stop(&state_info); #endif psci_get_target_local_pwr_states(end_pwrlvl, &state_info); @@ -801,7 +796,7 @@ void psci_warmboot_entrypoint(void) * Since caches are now enabled, it's necessary to do cache * maintenance before reading that same data. */ - psci_stats_update_pwr_up(end_pwrlvl, &state_info, PMF_CACHE_MAINT); + psci_stats_update_pwr_up(end_pwrlvl, &state_info); #endif /* @@ -957,7 +952,7 @@ unsigned int psci_get_max_phys_off_afflvl(void) { psci_power_state_t state_info; - memset(&state_info, 0, sizeof(state_info)); + zeromem(&state_info, sizeof(state_info)); psci_get_target_local_pwr_states(PLAT_MAX_PWR_LVL, &state_info); return psci_find_target_suspend_lvl(&state_info); diff --git a/lib/psci/psci_lib.mk b/lib/psci/psci_lib.mk index 8daa8318..82736cdd 100644 --- a/lib/psci/psci_lib.mk +++ b/lib/psci/psci_lib.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -32,6 +32,7 @@ PSCI_LIB_SOURCES := lib/el3_runtime/cpu_data_array.c \ lib/el3_runtime/${ARCH}/cpu_data.S \ lib/el3_runtime/${ARCH}/context_mgmt.c \ lib/cpus/${ARCH}/cpu_helpers.S \ + lib/cpus/errata_report.c \ lib/locks/exclusive/${ARCH}/spinlock.S \ lib/psci/psci_off.c \ lib/psci/psci_on.c \ diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index 0a3a60ac..5e166b52 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -117,13 +117,7 @@ int psci_cpu_suspend(unsigned int power_state, psci_set_cpu_local_state(cpu_pd_state); #if ENABLE_PSCI_STAT - /* - * Capture time-stamp before CPU standby - * No cache maintenance is needed as caches - * are ON through out the CPU standby operation. - */ - PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, - PMF_NO_CACHE_MAINT); + plat_psci_stat_accounting_start(&state_info); #endif #if ENABLE_RUNTIME_INSTRUMENTATION @@ -144,13 +138,10 @@ int psci_cpu_suspend(unsigned int power_state, #endif #if ENABLE_PSCI_STAT - /* Capture time-stamp after CPU standby */ - PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR, - PMF_NO_CACHE_MAINT); + plat_psci_stat_accounting_stop(&state_info); /* Update PSCI stats */ - psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info, - PMF_NO_CACHE_MAINT); + psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); #endif return PSCI_E_SUCCESS; diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c index 897bf319..394aaa3b 100644 --- a/lib/psci/psci_off.c +++ b/lib/psci/psci_off.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -137,13 +137,7 @@ int psci_do_cpu_off(unsigned int end_pwrlvl) psci_plat_pm_ops->pwr_domain_off(&state_info); #if ENABLE_PSCI_STAT - /* - * Capture time-stamp while entering low power state. - * No cache maintenance needed because caches are off - * and writes are direct to main memory. - */ - PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, - PMF_NO_CACHE_MAINT); + plat_psci_stat_accounting_start(&state_info); #endif exit: diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h index 781b3b52..ca8291e4 100644 --- a/lib/psci/psci_private.h +++ b/lib/psci/psci_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,7 +35,6 @@ #include <bakery_lock.h> #include <bl_common.h> #include <cpu_data.h> -#include <pmf.h> #include <psci.h> #include <spinlock.h> @@ -106,15 +105,6 @@ #define is_cpu_standby_req(is_power_down_state, retn_lvl) \ (((!(is_power_down_state)) && ((retn_lvl) == 0)) ? 1 : 0) -/* Following are used as ID's to capture time-stamp */ -#define PSCI_STAT_ID_ENTER_LOW_PWR 0 -#define PSCI_STAT_ID_EXIT_LOW_PWR 1 -#define PSCI_STAT_TOTAL_IDS 2 - -/* Declare PMF service functions for PSCI */ -PMF_DECLARE_CAPTURE_TIMESTAMP(psci_svc) -PMF_DECLARE_GET_TIMESTAMP(psci_svc) - /******************************************************************************* * The following two data structures implement the power domain tree. The tree * is used to track the state of all the nodes i.e. power domain instances @@ -246,8 +236,7 @@ void __dead2 psci_system_reset(void); void psci_stats_update_pwr_down(unsigned int end_pwrlvl, const psci_power_state_t *state_info); void psci_stats_update_pwr_up(unsigned int end_pwrlvl, - const psci_power_state_t *state_info, - unsigned int flags); + const psci_power_state_t *state_info); u_register_t psci_stat_residency(u_register_t target_cpu, unsigned int power_state); u_register_t psci_stat_count(u_register_t target_cpu, diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c index cb8b77db..7327b92e 100644 --- a/lib/psci/psci_setup.c +++ b/lib/psci/psci_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,6 +34,7 @@ #include <bl_common.h> #include <context.h> #include <context_mgmt.h> +#include <errata_report.h> #include <platform.h> #include <stddef.h> #include "psci_private.h" @@ -287,6 +288,9 @@ void psci_arch_setup(void) /* Initialize the cpu_ops pointer. */ init_cpu_ops(); + + /* Having initialized cpu_ops, we can now print errata status */ + print_errata_status(); } /****************************************************************************** diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c index ecbe592b..d8034a5d 100644 --- a/lib/psci/psci_stat.c +++ b/lib/psci/psci_stat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -38,9 +38,6 @@ #define PLAT_MAX_PWR_LVL_STATES 2 #endif -/* Ticks elapsed in one second by a signal of 1 MHz */ -#define MHZ_TICKS_PER_SEC 1000000 - /* Following structure is used for PSCI STAT */ typedef struct psci_stat { u_register_t residency; @@ -62,27 +59,6 @@ static psci_stat_t psci_cpu_stat[PLATFORM_CORE_COUNT] static psci_stat_t psci_non_cpu_stat[PSCI_NUM_NON_CPU_PWR_DOMAINS] [PLAT_MAX_PWR_LVL_STATES]; -/* Register PMF PSCI service */ -PMF_REGISTER_SERVICE(psci_svc, PMF_PSCI_STAT_SVC_ID, - PSCI_STAT_TOTAL_IDS, PMF_STORE_ENABLE) - -/* The divisor to use to convert raw timestamp into microseconds */ -u_register_t residency_div; - -/* - * This macro calculates the stats residency in microseconds, - * taking in account the wrap around condition. - */ -#define calc_stat_residency(_pwrupts, _pwrdnts, _res) \ - do { \ - if (_pwrupts < _pwrdnts) \ - _res = UINT64_MAX - _pwrdnts + _pwrupts;\ - else \ - _res = _pwrupts - _pwrdnts; \ - /* Convert timestamp into microseconds */ \ - _res = _res/residency_div; \ - } while (0) - /* * This functions returns the index into the `psci_stat_t` array given the * local power state and power domain level. If the platform implements the @@ -150,44 +126,23 @@ void psci_stats_update_pwr_down(unsigned int end_pwrlvl, * It is called with caches enabled and locks acquired(for NON-CPU domain) ******************************************************************************/ void psci_stats_update_pwr_up(unsigned int end_pwrlvl, - const psci_power_state_t *state_info, - unsigned int flags) + const psci_power_state_t *state_info) { int parent_idx, cpu_idx = plat_my_core_pos(); int lvl, stat_idx; plat_local_state_t local_state; - unsigned long long pwrup_ts = 0, pwrdn_ts = 0; u_register_t residency; assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); assert(state_info); - /* Initialize the residency divisor if not already initialized */ - if (!residency_div) { - /* Pre-calculate divisor so that it can be directly used to - convert time-stamp into microseconds */ - residency_div = read_cntfrq_el0() / MHZ_TICKS_PER_SEC; - assert(residency_div); - } - - /* Get power down time-stamp for current CPU */ - PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, - cpu_idx, flags, pwrdn_ts); - - /* In the case of 1st power on just return */ - if (!pwrdn_ts) - return; - - /* Get power up time-stamp for current CPU */ - PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR, - cpu_idx, flags, pwrup_ts); - /* Get the index into the stats array */ local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL); - /* Calculate stats residency */ - calc_stat_residency(pwrup_ts, pwrdn_ts, residency); + /* Call into platform interface to calculate residency. */ + residency = plat_psci_stat_get_residency(PSCI_CPU_PWR_LVL, + state_info, cpu_idx); /* Update CPU stats. */ psci_cpu_stat[cpu_idx][stat_idx].residency += residency; @@ -207,10 +162,9 @@ void psci_stats_update_pwr_up(unsigned int end_pwrlvl, assert(last_cpu_in_non_cpu_pd[parent_idx] != -1); - /* Get power down time-stamp for last CPU */ - PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, - last_cpu_in_non_cpu_pd[parent_idx], - flags, pwrdn_ts); + /* Call into platform interface to calculate residency. */ + residency = plat_psci_stat_get_residency(lvl, state_info, + last_cpu_in_non_cpu_pd[parent_idx]); /* Initialize back to reset value */ last_cpu_in_non_cpu_pd[parent_idx] = -1; @@ -218,9 +172,6 @@ void psci_stats_update_pwr_up(unsigned int end_pwrlvl, /* Get the index into the stats array */ stat_idx = get_stat_idx(local_state, lvl); - /* Calculate stats residency */ - calc_stat_residency(pwrup_ts, pwrdn_ts, residency); - /* Update non cpu stats */ psci_non_cpu_stat[parent_idx][stat_idx].residency += residency; psci_non_cpu_stat[parent_idx][stat_idx].count++; diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c index dc2ab774..302116bd 100644 --- a/lib/psci/psci_suspend.c +++ b/lib/psci/psci_suspend.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -211,13 +211,7 @@ void psci_cpu_suspend_start(entry_point_info_t *ep, psci_plat_pm_ops->pwr_domain_suspend(state_info); #if ENABLE_PSCI_STAT - /* - * Capture time-stamp while entering low power state. - * No cache maintenance needed because caches are off - * and writes are direct to main memory. - */ - PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, - PMF_NO_CACHE_MAINT); + plat_psci_stat_accounting_start(state_info); #endif exit: @@ -257,6 +251,10 @@ exit: PMF_NO_CACHE_MAINT); #endif +#if ENABLE_PSCI_STAT + plat_psci_stat_accounting_start(state_info); +#endif + /* * We will reach here if only retention/standby states have been * requested at multiple power levels. This means that the cpu @@ -264,6 +262,11 @@ exit: */ wfi(); +#if ENABLE_PSCI_STAT + plat_psci_stat_accounting_stop(state_info); + psci_stats_update_pwr_up(end_pwrlvl, state_info); +#endif + #if ENABLE_RUNTIME_INSTRUMENTATION PMF_CAPTURE_TIMESTAMP(rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR, diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 2312d2c9..93db2d66 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -81,6 +81,16 @@ define assert_boolean $(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean)) endef +0-9 := 0 1 2 3 4 5 6 7 8 9 + +# Function to verify that a given option $(1) contains a numeric value +define assert_numeric +$(if $($(1)),,$(error $(1) must not be empty)) +$(eval __numeric := $($(1))) +$(foreach d,$(0-9),$(eval __numeric := $(subst $(d),,$(__numeric)))) +$(if $(__numeric),$(error $(1) must be numeric)) +endef + # IMG_LINKERFILE defines the linker script corresponding to a BL stage # $(1) = BL stage (2, 30, 31, 32, 33) define IMG_LINKERFILE diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index fc39819d..b47ea46e 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -44,6 +44,10 @@ ARCH := aarch64 # port can change this value if needed. ARM_CCI_PRODUCT_ID := 400 +# ARM Architecture major and minor versions: 8.0 by default. +ARM_ARCH_MAJOR := 8 +ARM_ARCH_MINOR := 0 + # Determine the version of ARM GIC architecture to use for interrupt management # in EL3. The platform port can change this value if needed. ARM_GIC_ARCH := 2 @@ -89,6 +93,9 @@ ENABLE_RUNTIME_INSTRUMENTATION := 0 # Build flag to treat usage of deprecated platform and framework APIs as error. ERROR_DEPRECATED := 0 +# Byte alignment that each component in FIP is aligned to +FIP_ALIGN := 0 + # Default FIP file name FIP_NAME := fip.bin diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index d0898adc..bf5e03b0 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -60,9 +60,9 @@ #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ /* No SCP in FVP */ -#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x0) +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) -#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000) +#define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* * Load address of BL33 for this platform port diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c index 202342af..70637d64 100644 --- a/plat/arm/board/juno/juno_security.c +++ b/plat/arm/board/juno/juno_security.c @@ -60,16 +60,34 @@ static void css_init_nic400(void) } /******************************************************************************* + * Initialize debug configuration. + ******************************************************************************/ +static void init_debug_cfg(void) +{ +#if !DEBUG + /* Set internal drive selection for SPIDEN. */ + mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET, + 1U << SPIDEN_SEL_SET_SHIFT); + + /* Drive SPIDEN LOW to disable invasive debug of secure state. */ + mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR, + 1U << SPIDEN_INT_CLR_SHIFT); +#endif +} + +/******************************************************************************* * Initialize the secure environment. ******************************************************************************/ void plat_arm_security_setup(void) { + /* Initialize debug configuration */ + init_debug_cfg(); /* Initialize the TrustZone Controller */ arm_tzc400_setup(); /* Do ARM CSS internal NIC setup */ css_init_nic400(); /* Do ARM CSS SoC security setup */ soc_css_security_setup(); - /* Initialize the SMMU SSD tables*/ + /* Initialize the SMMU SSD tables */ init_mmu401(); } diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 5f307080..007108d1 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -38,6 +38,7 @@ #include <plat_arm.h> #include <platform_def.h> #include <string.h> +#include <utils.h> /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); @@ -123,7 +124,7 @@ bl31_params_t *bl2_plat_get_bl31_params(void) * Initialise the memory for all the arguments that needs to * be passed to BL31 */ - memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); + zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); /* Assign memory for TF related information */ bl2_to_bl31_params = &bl31_params_mem.bl31_params; diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index c2f28f98..4628a43d 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -92,6 +92,7 @@ $(eval $(call add_define,ARM_BL31_IN_DRAM)) # Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms ENABLE_PSCI_STAT := 1 +ENABLE_PMF := 1 # On ARM platforms, separate the code and read-only data sections to allow # mapping the former as executable and the latter as execute-never. diff --git a/plat/arm/css/common/css_bl2_setup.c b/plat/arm/css/common/css_bl2_setup.c index 11ca3423..5361d897 100644 --- a/plat/arm/css/common/css_bl2_setup.c +++ b/plat/arm/css/common/css_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -98,7 +98,7 @@ void bl2_platform_setup(void) * - restoring the SCP boot configuration. */ VERBOSE("BL2: Restoring SCP reset data in Trusted SRAM\n"); - memset((void *) ARM_TRUSTED_SRAM_BASE, 0, 128); + zero_normalmem((void *)ARM_TRUSTED_SRAM_BASE, 128); mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config); } #endif /* EL3_PAYLOAD_BASE */ diff --git a/plat/arm/css/drivers/scpi/css_scpi.c b/plat/arm/css/drivers/scpi/css_scpi.c index f419abd0..65ae978f 100644 --- a/plat/arm/css/drivers/scpi/css_scpi.c +++ b/plat/arm/css/drivers/scpi/css_scpi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,6 +34,7 @@ #include <debug.h> #include <platform.h> #include <string.h> +#include <utils.h> #include "css_mhu.h" #include "css_scpi.h" @@ -204,7 +205,8 @@ int scpi_get_css_power_state(unsigned int mpidr, unsigned int *cpu_state_p, scpi_secure_message_start(); /* Populate request headers */ - cmd = memset(SCPI_CMD_HEADER_AP_TO_SCP, 0, sizeof(*cmd)); + zeromem(SCPI_CMD_HEADER_AP_TO_SCP, sizeof(*cmd)); + cmd = SCPI_CMD_HEADER_AP_TO_SCP; cmd->id = SCPI_CMD_GET_CSS_POWER_STATE; /* diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c index 3eb6886e..0e00faaf 100644 --- a/plat/common/plat_psci_common.c +++ b/plat/common/plat_psci_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,8 +31,125 @@ #include <arch.h> #include <assert.h> #include <platform.h> +#include <pmf.h> #include <psci.h> +#if ENABLE_PSCI_STAT && ENABLE_PMF +#pragma weak plat_psci_stat_accounting_start +#pragma weak plat_psci_stat_accounting_stop +#pragma weak plat_psci_stat_get_residency + +/* Ticks elapsed in one second by a signal of 1 MHz */ +#define MHZ_TICKS_PER_SEC 1000000 + +/* Following are used as ID's to capture time-stamp */ +#define PSCI_STAT_ID_ENTER_LOW_PWR 0 +#define PSCI_STAT_ID_EXIT_LOW_PWR 1 +#define PSCI_STAT_TOTAL_IDS 2 + +PMF_REGISTER_SERVICE(psci_svc, PMF_PSCI_STAT_SVC_ID, PSCI_STAT_TOTAL_IDS, + PMF_STORE_ENABLE) + +/* + * This function calculates the stats residency in microseconds, + * taking in account the wrap around condition. + */ +static u_register_t calc_stat_residency(unsigned long long pwrupts, + unsigned long long pwrdnts) +{ + /* The divisor to use to convert raw timestamp into microseconds. */ + u_register_t residency_div; + u_register_t res; + + /* + * Calculate divisor so that it can be directly used to + * convert time-stamp into microseconds. + */ + residency_div = read_cntfrq_el0() / MHZ_TICKS_PER_SEC; + assert(residency_div); + + if (pwrupts < pwrdnts) + res = UINT64_MAX - pwrdnts + pwrupts; + else + res = pwrupts - pwrdnts; + + return res / residency_div; +} + +/* + * Capture timestamp before entering a low power state. + * No cache maintenance is required when capturing the timestamp. + * Cache maintenance may be needed when reading these timestamps. + */ +void plat_psci_stat_accounting_start( + __unused const psci_power_state_t *state_info) +{ + assert(state_info); + PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, + PMF_NO_CACHE_MAINT); +} + +/* + * Capture timestamp after exiting a low power state. + * No cache maintenance is required when capturing the timestamp. + * Cache maintenance may be needed when reading these timestamps. + */ +void plat_psci_stat_accounting_stop( + __unused const psci_power_state_t *state_info) +{ + assert(state_info); + PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR, + PMF_NO_CACHE_MAINT); +} + +/* + * Calculate the residency for the given level and power state + * information. + */ +u_register_t plat_psci_stat_get_residency(unsigned int lvl, + const psci_power_state_t *state_info, + int last_cpu_idx) +{ + plat_local_state_t state; + unsigned long long pwrup_ts = 0, pwrdn_ts = 0; + unsigned int pmf_flags; + + assert(lvl >= PSCI_CPU_PWR_LVL && lvl <= PLAT_MAX_PWR_LVL); + assert(state_info); + assert(last_cpu_idx >= 0 && last_cpu_idx <= PLATFORM_CORE_COUNT); + + if (lvl == PSCI_CPU_PWR_LVL) + assert(last_cpu_idx == plat_my_core_pos()); + + /* + * If power down is requested, then timestamp capture will + * be with caches OFF. Hence we have to do cache maintenance + * when reading the timestamp. + */ + state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; + if (is_local_state_off(state)) { + pmf_flags = PMF_CACHE_MAINT; + } else { + assert(is_local_state_retn(state)); + pmf_flags = PMF_NO_CACHE_MAINT; + } + + PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, + PSCI_STAT_ID_ENTER_LOW_PWR, + last_cpu_idx, + pmf_flags, + pwrdn_ts); + + PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, + PSCI_STAT_ID_EXIT_LOW_PWR, + plat_my_core_pos(), + pmf_flags, + pwrup_ts); + + return calc_stat_residency(pwrup_ts, pwrdn_ts); +} +#endif /* ENABLE_PSCI_STAT && ENABLE_PMF */ + /* * The PSCI generic code uses this API to let the platform participate in state * coordination during a power management operation. It compares the platform diff --git a/plat/common/tbbr/plat_tbbr.c b/plat/common/tbbr/plat_tbbr.c index 475564a6..fde4d544 100644 --- a/plat/common/tbbr/plat_tbbr.c +++ b/plat/common/tbbr/plat_tbbr.c @@ -60,7 +60,7 @@ int plat_set_nv_ctr2(void *cookie, const auth_img_desc_t *img_desc, * has been signed with the ROT key. Non Trusted NV counter * updates are unconditional. */ - if (!trusted_nv_ctr || (trusted_nv_ctr && img_desc->parent == NULL)) + if (!trusted_nv_ctr || img_desc->parent == NULL) return plat_set_nv_ctr(cookie, nv_ctr); /* diff --git a/plat/mediatek/mt6795/bl31.ld.S b/plat/mediatek/mt6795/bl31.ld.S index 44510a75..472cd2e0 100644 --- a/plat/mediatek/mt6795/bl31.ld.S +++ b/plat/mediatek/mt6795/bl31.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -113,7 +113,8 @@ SECTIONS /* * The .bss section gets initialised to 0 at runtime. - * Its base address must be 16-byte aligned. + * Its base address should be 16-byte aligned for better performance of the + * zero-initialization code. */ .bss (NOLOAD) : ALIGN(16) { __BSS_START__ = .; diff --git a/plat/mediatek/mt8173/aarch64/plat_helpers.S b/plat/mediatek/mt8173/aarch64/plat_helpers.S index af3a4073..3347f55f 100644 --- a/plat/mediatek/mt8173/aarch64/plat_helpers.S +++ b/plat/mediatek/mt8173/aarch64/plat_helpers.S @@ -34,6 +34,7 @@ .globl plat_secondary_cold_boot_setup .globl plat_report_exception .globl platform_is_primary_cpu + .globl plat_my_core_pos .globl plat_crash_console_init .globl plat_crash_console_putc @@ -59,6 +60,22 @@ func platform_is_primary_cpu ret endfunc platform_is_primary_cpu +#if !ENABLE_PLAT_COMPAT + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void); + * + * result: CorePos = CoreId + (ClusterId << 2) + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_my_core_pos +#endif + /* --------------------------------------------- * int plat_crash_console_init(void) * Function to initialize the crash console diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index ef18d079..92c3494e 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -27,7 +27,6 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ -#include <arm_gic.h> #include <assert.h> #include <bl_common.h> #include <common_def.h> @@ -37,6 +36,7 @@ #include <mcucfg.h> #include <mmio.h> #include <mtcmos.h> +#include <plat_arm.h> #include <plat_private.h> #include <platform.h> #include <spm.h> @@ -159,11 +159,13 @@ void bl31_platform_setup(void) generic_delay_timer_init(); /* Initialize the gic cpu and distributor interfaces */ - plat_mt_gic_init(); - arm_gic_setup(); + plat_arm_gic_driver_init(); + plat_arm_gic_init(); +#if ENABLE_PLAT_COMPAT /* Topologies are best known to the platform. */ mt_setup_topology(); +#endif /* Initialize spm at boot time */ spm_boot_init(); diff --git a/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c b/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c index b89cd976..4cafd29e 100644 --- a/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c +++ b/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c @@ -27,6 +27,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ +#include <arch.h> #include <mmio.h> #include <mt8173_def.h> #include <platform.h> @@ -258,7 +259,9 @@ void spm_hotplug_on(unsigned long mpidr) { unsigned long linear_id; - linear_id = platform_get_core_pos(mpidr); + linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | + (mpidr & MPIDR_CPU_MASK); + spm_lock_get(); if (is_hotplug_ready() == 0) { spm_mcdi_wakeup_all_cores(); @@ -277,7 +280,9 @@ void spm_hotplug_off(unsigned long mpidr) { unsigned long linear_id; - linear_id = platform_get_core_pos(mpidr); + linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | + (mpidr & MPIDR_CPU_MASK); + spm_lock_get(); if (is_hotplug_ready() == 0) { spm_mcdi_wakeup_all_cores(); diff --git a/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c b/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c index d715735d..4d8422fc 100644 --- a/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c +++ b/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c @@ -511,7 +511,10 @@ void spm_mcdi_prepare_for_off_state(unsigned long mpidr, unsigned int afflvl) void spm_mcdi_finish_for_on_state(unsigned long mpidr, unsigned int afflvl) { - unsigned long linear_id = platform_get_core_pos(mpidr); + unsigned long linear_id; + + linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | + (mpidr & MPIDR_CPU_MASK); spm_lock_get(); spm_mcdi_clear_cputop_pwrctrl_for_cluster_on(mpidr); diff --git a/plat/mediatek/mt8173/include/mt8173_def.h b/plat/mediatek/mt8173/include/mt8173_def.h index 87e9c046..21c36b5e 100644 --- a/plat/mediatek/mt8173/include/mt8173_def.h +++ b/plat/mediatek/mt8173/include/mt8173_def.h @@ -126,4 +126,51 @@ #define MT_IRQ_SEC_SGI_6 14 #define MT_IRQ_SEC_SGI_7 15 +/* + * Macros for local power states in MTK platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define MTK_LOCAL_STATE_RUN 0 +/* Local power state for retention. Valid only for CPU power domains */ +#define MTK_LOCAL_STATE_RET 1 +/* Local power state for OFF/power-down. Valid for CPU and cluster power + * domains + */ +#define MTK_LOCAL_STATE_OFF 2 + +#if PSCI_EXTENDED_STATE_ID +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define MTK_LOCAL_PSTATE_WIDTH 4 +#define MTK_LOCAL_PSTATE_MASK ((1 << MTK_LOCAL_PSTATE_WIDTH) - 1) + +/* Macros to construct the composite power state */ + +/* Make composite power state parameter till power level 0 */ + +#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) +#else +#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) + +#endif /* __PSCI_EXTENDED_STATE_ID__ */ + +/* Make composite power state parameter till power level 1 */ +#define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << MTK_LOCAL_PSTATE_WIDTH) | \ + mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + +/* Make composite power state parameter till power level 2 */ +#define mtk_make_pwrstate_lvl2( \ + lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl2_state) << (MTK_LOCAL_PSTATE_WIDTH * 2)) | \ + mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) + + #endif /* __MT8173_DEF_H__ */ diff --git a/plat/mediatek/mt8173/include/plat_macros.S b/plat/mediatek/mt8173/include/plat_macros.S index 018a790a..f95fd5b4 100644 --- a/plat/mediatek/mt8173/include/plat_macros.S +++ b/plat/mediatek/mt8173/include/plat_macros.S @@ -29,7 +29,8 @@ */ #include <cci.h> -#include <gic_v2.h> +#include <gic_common.h> +#include <gicv2.h> #include <mt8173_def.h> .section .rodata.gic_reg_name, "aS" diff --git a/plat/mediatek/mt8173/include/plat_private.h b/plat/mediatek/mt8173/include/plat_private.h index ae50e449..9488b88b 100644 --- a/plat/mediatek/mt8173/include/plat_private.h +++ b/plat/mediatek/mt8173/include/plat_private.h @@ -45,9 +45,6 @@ void plat_cci_init(void); void plat_cci_enable(void); void plat_cci_disable(void); -/* Declarations for plat_mt_gic.c */ -void plat_mt_gic_init(void); - /* Declarations for plat_topology.c */ int mt_setup_topology(void); diff --git a/plat/mediatek/mt8173/include/platform_def.h b/plat/mediatek/mt8173/include/platform_def.h index 8f771e32..bb69920f 100644 --- a/plat/mediatek/mt8173/include/platform_def.h +++ b/plat/mediatek/mt8173/include/platform_def.h @@ -31,6 +31,8 @@ #ifndef __PLATFORM_DEF_H__ #define __PLATFORM_DEF_H__ +#include "mt8173_def.h" + /******************************************************************************* * Platform binary types for linking @@ -56,6 +58,11 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#if !ENABLE_PLAT_COMPAT +#define PLAT_MAX_PWR_LVL 2 +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 +#endif #define PLATFORM_SYSTEM_COUNT 1 #define PLATFORM_CLUSTER_COUNT 2 #define PLATFORM_CLUSTER0_CORE_COUNT 4 @@ -111,7 +118,8 @@ /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ -#define ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) #define MAX_XLAT_TABLES 4 #define MAX_MMAP_REGIONS 16 @@ -127,4 +135,19 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE + +#define PLAT_ARM_G1S_IRQS MT_IRQ_SEC_SGI_0, \ + MT_IRQ_SEC_SGI_1, \ + MT_IRQ_SEC_SGI_2, \ + MT_IRQ_SEC_SGI_3, \ + MT_IRQ_SEC_SGI_4, \ + MT_IRQ_SEC_SGI_5, \ + MT_IRQ_SEC_SGI_6, \ + MT_IRQ_SEC_SGI_7 + +#define PLAT_ARM_G0_IRQS + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/mediatek/mt8173/plat_pm.c b/plat/mediatek/mt8173/plat_pm.c index 6bb8a9b5..d727967e 100644 --- a/plat/mediatek/mt8173/plat_pm.c +++ b/plat/mediatek/mt8173/plat_pm.c @@ -29,17 +29,18 @@ */ #include <arch_helpers.h> -#include <arm_gic.h> #include <assert.h> #include <bakery_lock.h> #include <cci.h> #include <console.h> #include <debug.h> #include <errno.h> +#include <gicv2.h> #include <mcucfg.h> #include <mmio.h> #include <mt8173_def.h> #include <mt_cpuxgpt.h> /* generic_timer_backup() */ +#include <plat_arm.h> #include <plat_private.h> #include <power_tracer.h> #include <psci.h> @@ -49,6 +50,44 @@ #include <spm_mcdi.h> #include <spm_suspend.h> +#if !ENABLE_PLAT_COMPAT +#define MTK_PWR_LVL0 0 +#define MTK_PWR_LVL1 1 +#define MTK_PWR_LVL2 2 + +/* Macros to read the MTK power domain state */ +#define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0] +#define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1] +#define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ?\ + (state)->pwr_domain_state[MTK_PWR_LVL2] : 0) +#endif + +#if PSCI_EXTENDED_STATE_ID +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +const unsigned int mtk_pm_idle_states[] = { + /* State-id - 0x001 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN, + MTK_LOCAL_STATE_RET, MTK_PWR_LVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x002 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN, + MTK_LOCAL_STATE_OFF, MTK_PWR_LVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x022 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_OFF, + MTK_LOCAL_STATE_OFF, MTK_PWR_LVL1, PSTATE_TYPE_POWERDOWN), +#if PLAT_MAX_PWR_LVL > MTK_PWR_LVL1 + /* State-id - 0x222 */ + mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_OFF, MTK_LOCAL_STATE_OFF, + MTK_LOCAL_STATE_OFF, MTK_PWR_LVL2, PSTATE_TYPE_POWERDOWN), +#endif + 0, +}; +#endif + struct core_context { unsigned long timer_data[8]; unsigned int count; @@ -219,6 +258,7 @@ static void mt_platform_restore_context(unsigned long mpidr) mt_cpu_restore(mpidr); } +#if ENABLE_PLAT_COMPAT /******************************************************************************* * Private function which is used to determine if any platform actions * should be performed for the specified affinity instance given its @@ -270,11 +310,25 @@ static void plat_affinst_standby(unsigned int power_state) wfi(); } } +#else +static void plat_cpu_standby(plat_local_state_t cpu_state) +{ + unsigned int scr; + + scr = read_scr_el3(); + write_scr_el3(scr | SCR_IRQ_BIT); + isb(); + dsb(); + wfi(); + write_scr_el3(scr); +} +#endif /******************************************************************************* * MTK_platform handler called when an affinity instance is about to be turned * on. The level and mpidr determine the affinity instance. ******************************************************************************/ +#if ENABLE_PLAT_COMPAT static int plat_affinst_on(unsigned long mpidr, unsigned long sec_entrypoint, unsigned int afflvl, @@ -308,6 +362,32 @@ static int plat_affinst_on(unsigned long mpidr, return rc; } +#else +static uintptr_t secure_entrypoint; + +static int plat_power_domain_on(unsigned long mpidr) +{ + int rc = PSCI_E_SUCCESS; + unsigned long cpu_id; + unsigned long cluster_id; + uintptr_t rv; + + cpu_id = mpidr & MPIDR_CPU_MASK; + cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + if (cluster_id) + rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw; + else + rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw; + + mmio_write_32(rv, secure_entrypoint); + INFO("mt_on[%ld:%ld], entry %x\n", + cluster_id, cpu_id, mmio_read_32(rv)); + + spm_hotplug_on(mpidr); + return rc; +} +#endif /******************************************************************************* * MTK_platform handler called when an affinity instance is about to be turned @@ -321,6 +401,7 @@ static int plat_affinst_on(unsigned long mpidr, * dealt with. So do not write & read global variables across calls. It will be * wise to do flush a write to the global to prevent unpredictable results. ******************************************************************************/ +#if ENABLE_PLAT_COMPAT static void plat_affinst_off(unsigned int afflvl, unsigned int state) { unsigned long mpidr = read_mpidr_el1(); @@ -330,7 +411,7 @@ static void plat_affinst_off(unsigned int afflvl, unsigned int state) return; /* Prevent interrupts from spuriously waking up this cpu */ - arm_gic_cpuif_deactivate(); + gicv2_cpuif_disable(); spm_hotplug_off(mpidr); @@ -343,6 +424,26 @@ static void plat_affinst_off(unsigned int afflvl, unsigned int state) trace_power_flow(mpidr, CLUSTER_DOWN); } } +#else +static void plat_power_domain_off(const psci_power_state_t *state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Prevent interrupts from spuriously waking up this cpu */ + gicv2_cpuif_disable(); + + spm_hotplug_off(mpidr); + + trace_power_flow(mpidr, CPU_DOWN); + + if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) { + /* Disable coherency if this cluster is to be turned off */ + plat_cci_disable(); + + trace_power_flow(mpidr, CLUSTER_DOWN); + } +} +#endif /******************************************************************************* * MTK_platform handler called when an affinity instance is about to be @@ -356,6 +457,7 @@ static void plat_affinst_off(unsigned int afflvl, unsigned int state) * dealt with. So do not write & read global variables across calls. It will be * wise to do flush a write to the global to prevent unpredictable results. ******************************************************************************/ +#if ENABLE_PLAT_COMPAT static void plat_affinst_suspend(unsigned long sec_entrypoint, unsigned int afflvl, unsigned int state) @@ -396,9 +498,50 @@ static void plat_affinst_suspend(unsigned long sec_entrypoint, generic_timer_backup(); spm_system_suspend(); /* Prevent interrupts from spuriously waking up this cpu */ - arm_gic_cpuif_deactivate(); + gicv2_cpuif_disable(); + } +} +#else +static void plat_power_domain_suspend(const psci_power_state_t *state) +{ + unsigned long mpidr = read_mpidr_el1(); + unsigned long cluster_id; + unsigned long cpu_id; + uintptr_t rv; + + cpu_id = mpidr & MPIDR_CPU_MASK; + cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + if (cluster_id) + rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw; + else + rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw; + + mmio_write_32(rv, secure_entrypoint); + + if (MTK_SYSTEM_PWR_STATE(state) != MTK_LOCAL_STATE_OFF) { + spm_mcdi_prepare_for_off_state(mpidr, MTK_PWR_LVL0); + if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) + spm_mcdi_prepare_for_off_state(mpidr, MTK_PWR_LVL1); + } + + mt_platform_save_context(mpidr); + + /* Perform the common cluster specific operations */ + if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) { + /* Disable coherency if this cluster is to be turned off */ + plat_cci_disable(); + } + + if (MTK_SYSTEM_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) { + disable_scu(mpidr); + generic_timer_backup(); + spm_system_suspend(); + /* Prevent interrupts from spuriously waking up this cpu */ + gicv2_cpuif_disable(); } } +#endif /******************************************************************************* * MTK_platform handler called when an affinity instance has just been powered @@ -407,6 +550,7 @@ static void plat_affinst_suspend(unsigned long sec_entrypoint, * was turned off prior to wakeup and do what's necessary to setup it up * correctly. ******************************************************************************/ +#if ENABLE_PLAT_COMPAT static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state) { unsigned long mpidr = read_mpidr_el1(); @@ -423,16 +567,45 @@ static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state) } /* Enable the gic cpu interface */ - arm_gic_cpuif_setup(); - arm_gic_pcpu_distif_setup(); + gicv2_cpuif_enable(); + gicv2_pcpu_distif_init(); trace_power_flow(mpidr, CPU_UP); } +#else +void mtk_system_pwr_domain_resume(void); + +static void plat_power_domain_on_finish(const psci_power_state_t *state) +{ + unsigned long mpidr = read_mpidr_el1(); + + assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF); + + if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) && + (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) + mtk_system_pwr_domain_resume(); + + if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { + plat_cci_enable(); + trace_power_flow(mpidr, CLUSTER_UP); + } + + if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) && + (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) + return; + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); + gicv2_pcpu_distif_init(); + trace_power_flow(mpidr, CPU_UP); +} +#endif /******************************************************************************* * MTK_platform handler called when an affinity instance has just been powered * on after having been suspended earlier. The level and mpidr determine the * affinity instance. ******************************************************************************/ +#if ENABLE_PLAT_COMPAT static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state) { unsigned long mpidr = read_mpidr_el1(); @@ -443,8 +616,7 @@ static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state) if (afflvl >= MPIDR_AFFLVL2) { /* Enable the gic cpu interface */ - arm_gic_setup(); - arm_gic_cpuif_setup(); + plat_arm_gic_init(); spm_system_suspend_finish(); enable_scu(mpidr); } @@ -461,14 +633,56 @@ static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state) if (afflvl < MPIDR_AFFLVL2) spm_mcdi_finish_for_on_state(mpidr, afflvl); - arm_gic_pcpu_distif_setup(); + gicv2_pcpu_distif_init(); +} +#else +static void plat_power_domain_suspend_finish(const psci_power_state_t *state) +{ + unsigned long mpidr = read_mpidr_el1(); + + if (state->pwr_domain_state[MTK_PWR_LVL0] == MTK_LOCAL_STATE_RET) + return; + + if (MTK_SYSTEM_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) { + /* Enable the gic cpu interface */ + plat_arm_gic_init(); + spm_system_suspend_finish(); + enable_scu(mpidr); + } + + /* Perform the common cluster specific operations */ + if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) { + /* Enable coherency if this cluster was off */ + plat_cci_enable(); + } + + mt_platform_restore_context(mpidr); + + if (MTK_SYSTEM_PWR_STATE(state) != MTK_LOCAL_STATE_OFF) { + spm_mcdi_finish_for_on_state(mpidr, MTK_PWR_LVL0); + if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) + spm_mcdi_finish_for_on_state(mpidr, MTK_PWR_LVL1); + } + + gicv2_pcpu_distif_init(); } +#endif +#if ENABLE_PLAT_COMPAT static unsigned int plat_get_sys_suspend_power_state(void) { /* StateID: 0, StateType: 1(power down), PowerLevel: 2(system) */ return psci_make_powerstate(0, 1, 2); } +#else +static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + assert(PLAT_MAX_PWR_LVL >= 2); + + for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; +} +#endif /******************************************************************************* * MTK handlers to shutdown/reboot the system @@ -500,6 +714,94 @@ static void __dead2 plat_system_reset(void) panic(); } +#if !ENABLE_PLAT_COMPAT +#if !PSCI_EXTENDED_STATE_ID +static int plat_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pstate = psci_get_pstate_type(power_state); + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int i; + + assert(req_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on power level 0 + * Ignore any other power level. + */ + if (pwr_lvl != 0) + return PSCI_E_INVALID_PARAMS; + + req_state->pwr_domain_state[MTK_PWR_LVL0] = + MTK_LOCAL_STATE_RET; + } else { + for (i = 0; i <= pwr_lvl; i++) + req_state->pwr_domain_state[i] = + MTK_LOCAL_STATE_OFF; + } + + /* + * We expect the 'state id' to be zero. + */ + if (psci_get_pstate_id(power_state)) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} +#else +int plat_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state); + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; !!mtk_pm_idle_states[i]; i++) { + if (power_state == mtk_pm_idle_states[i]) + break; + } + + /* Return error if entry not found in the idle state array */ + if (!mtk_pm_idle_states[i]) + return PSCI_E_INVALID_PARAMS; + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + MTK_LOCAL_PSTATE_MASK; + state_id >>= MTK_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} +#endif + +void mtk_system_pwr_domain_resume(void) +{ + console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); + + /* Assert system power domain is available on the platform */ + assert(PLAT_MAX_PWR_LVL >= MTK_PWR_LVL2); + + plat_arm_gic_init(); +} +#endif + +#if ENABLE_PLAT_COMPAT /******************************************************************************* * Export the platform handlers to enable psci to invoke them ******************************************************************************/ @@ -524,3 +826,54 @@ int platform_setup_pm(const plat_pm_ops_t **plat_ops) *plat_ops = &plat_plat_pm_ops; return 0; } +#else +static const plat_psci_ops_t plat_plat_pm_ops = { + .cpu_standby = plat_cpu_standby, + .pwr_domain_on = plat_power_domain_on, + .pwr_domain_on_finish = plat_power_domain_on_finish, + .pwr_domain_off = plat_power_domain_off, + .pwr_domain_suspend = plat_power_domain_suspend, + .pwr_domain_suspend_finish = plat_power_domain_suspend_finish, + .system_off = plat_system_off, + .system_reset = plat_system_reset, + .validate_power_state = plat_validate_power_state, + .get_sys_suspend_power_state = plat_get_sys_suspend_power_state, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + *psci_ops = &plat_plat_pm_ops; + secure_entrypoint = sec_entrypoint; + return 0; +} + +/* + * The PSCI generic code uses this API to let the platform participate in state + * coordination during a power management operation. It compares the platform + * specific local power states requested by each cpu for a given power domain + * and returns the coordinated target power state that the domain should + * enter. A platform assigns a number to a local power state. This default + * implementation assumes that the platform assigns these numbers in order of + * increasing depth of the power state i.e. for two power states X & Y, if X < Y + * then X represents a shallower power state than Y. As a result, the + * coordinated target local power state for a power domain will be the minimum + * of the requested local power states. + */ +plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, + const plat_local_state_t *states, + unsigned int ncpu) +{ + plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; + + assert(ncpu); + + do { + temp = *states++; + if (temp < target) + target = temp; + } while (--ncpu); + + return target; +} +#endif diff --git a/plat/mediatek/mt8173/plat_topology.c b/plat/mediatek/mt8173/plat_topology.c index 96598b65..caab8e46 100644 --- a/plat/mediatek/mt8173/plat_topology.c +++ b/plat/mediatek/mt8173/plat_topology.c @@ -31,6 +31,7 @@ #include <platform_def.h> #include <psci.h> +#if ENABLE_PLAT_COMPAT unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr) { /* Report 1 (absent) instance at levels higher that the cluster level */ @@ -54,3 +55,55 @@ int mt_setup_topology(void) /* [TODO] Make topology configurable via SCC */ return 0; } +#else + +const unsigned char mtk_power_domain_tree_desc[] = { + /* No of root nodes */ + PLATFORM_SYSTEM_COUNT, + /* No of children for the root node */ + PLATFORM_CLUSTER_COUNT, + /* No of children for the first cluster node */ + PLATFORM_CLUSTER0_CORE_COUNT, + /* No of children for the second cluster node */ + PLATFORM_CLUSTER1_CORE_COUNT +}; + +/******************************************************************************* + * This function returns the MT8173 default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return mtk_power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + /* + * Validate cpu_id by checking whether it represents a CPU in + * one of the two clusters present on the platform. + */ + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return (cpu_id + (cluster_id * 4)); +} +#endif diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk index 54ca4759..e59125a5 100644 --- a/plat/mediatek/mt8173/platform.mk +++ b/plat/mediatek/mt8173/platform.mk @@ -33,6 +33,8 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT}/common/drivers/uart/ \ + -Iinclude/plat/arm/common \ + -Iinclude/plat/arm/common/aarch64 \ -I${MTK_PLAT_SOC}/drivers/crypt/ \ -I${MTK_PLAT_SOC}/drivers/mtcmos/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ @@ -44,12 +46,13 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ lib/xlat_tables/aarch64/xlat_tables.c \ plat/common/aarch64/plat_common.c \ - plat/common/plat_gic.c + plat/arm/common/arm_gicv2.c \ + plat/common/plat_gicv2.c BL31_SOURCES += drivers/arm/cci/cci.c \ - drivers/arm/gic/arm_gic.c \ - drivers/arm/gic/gic_v2.c \ - drivers/arm/gic/gic_v3.c \ + drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ drivers/console/aarch64/console.S \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ @@ -73,7 +76,6 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ ${MTK_PLAT_SOC}/drivers/spm/spm_mcdi.c \ ${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \ ${MTK_PLAT_SOC}/drivers/timer/mt_cpuxgpt.c \ - ${MTK_PLAT_SOC}/plat_mt_gic.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_sip_calls.c \ ${MTK_PLAT_SOC}/plat_topology.c \ diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 905c4c5f..6851b150 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -35,6 +35,22 @@ #include <cortex_a53.h> #include <tegra_def.h> +#define MIDR_PN_CORTEX_A57 0xD07 + +/******************************************************************************* + * Implementation defined ACTLR_EL3 bit definitions + ******************************************************************************/ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) +#define ACTLR_EL3_L2CTLR_BIT (1 << 4) +#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) +#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ + ACTLR_EL3_L2ECTLR_BIT | \ + ACTLR_EL3_L2CTLR_BIT | \ + ACTLR_EL3_CPUECTLR_BIT | \ + ACTLR_EL3_CPUACTLR_BIT) + /* Global functions */ .globl plat_is_my_cpu_primary .globl plat_my_core_pos @@ -50,6 +66,7 @@ .globl tegra_sec_entry_point .globl ns_image_entrypoint .globl tegra_bl31_phys_base + .globl tegra_console_base /* --------------------- * Common CPU init code @@ -57,7 +74,18 @@ */ .macro cpu_init_common -#if ENABLE_L2_DYNAMIC_RETENTION + /* ------------------------------------------------ + * We enable procesor retention and L2/CPUECTLR NS + * access for A57 CPUs only. + * ------------------------------------------------ + */ + mrs x0, midr_el1 + mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) + and x0, x0, x1 + lsr x0, x0, #MIDR_PN_SHIFT + cmp x0, #MIDR_PN_CORTEX_A57 + b.ne 1f + /* --------------------------- * Enable processor retention * --------------------------- @@ -68,18 +96,14 @@ orr x0, x0, x1 msr L2ECTLR_EL1, x0 isb -#endif -#if ENABLE_CPU_DYNAMIC_RETENTION mrs x0, CPUECTLR_EL1 mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK orr x0, x0, x1 msr CPUECTLR_EL1, x0 isb -#endif -#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS /* ------------------------------------------------------- * Enable L2 and CPU ECTLR RW access from non-secure world * ------------------------------------------------------- @@ -88,13 +112,12 @@ msr actlr_el3, x0 msr actlr_el2, x0 isb -#endif /* -------------------------------- * Enable the cycle count register * -------------------------------- */ - mrs x0, pmcr_el0 +1: mrs x0, pmcr_el0 ubfx x0, x0, #11, #5 // read PMCR.N field mov x1, #1 lsl x0, x1, x0 @@ -158,6 +181,20 @@ func plat_get_my_entrypoint endfunc plat_get_my_entrypoint /* ----------------------------------------------------- + * int platform_get_core_pos(int mpidr); + * + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func platform_get_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc platform_get_core_pos + + /* ----------------------------------------------------- * void plat_secondary_cold_boot_setup (void); * * This function performs any platform specific actions @@ -190,7 +227,8 @@ endfunc platform_mem_init * --------------------------------------------- */ func plat_crash_console_init - mov_imm x0, TEGRA_BOOT_UART_BASE + adr x0, tegra_console_base + ldr x0, [x0] mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ mov_imm x2, TEGRA_CONSOLE_BAUDRATE b console_core_init @@ -204,7 +242,8 @@ endfunc plat_crash_console_init * --------------------------------------------- */ func plat_crash_console_putc - mov_imm x1, TEGRA_BOOT_UART_BASE + adr x1, tegra_console_base + ldr x1, [x1] b console_core_putc endfunc plat_crash_console_putc @@ -366,3 +405,10 @@ ns_image_entrypoint: */ tegra_bl31_phys_base: .quad 0 + + /* -------------------------------------------------- + * UART controller base for console init + * -------------------------------------------------- + */ +tegra_console_base: + .quad 0 diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c index 40d1bab0..c4170504 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,14 +31,14 @@ #include <arch_helpers.h> #include <assert.h> #include <debug.h> -#include <mmio.h> #include <memctrl.h> +#include <memctrl_v1.h> +#include <mmio.h> #include <string.h> #include <tegra_def.h> +#include <utils.h> #include <xlat_tables.h> -extern void zeromem16(void *mem, unsigned int length); - #define TEGRA_GPU_RESET_REG_OFFSET 0x28c #define GPU_RESET_BIT (1 << 24) @@ -55,7 +55,7 @@ void tegra_memctrl_setup(void) * Setup the Memory controller to allow only secure accesses to * the TZDRAM carveout */ - INFO("Configuring SMMU\n"); + INFO("Tegra Memory Controller (v1)\n"); /* allow translations for all MC engines */ tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, @@ -90,6 +90,14 @@ void tegra_memctrl_setup(void) } /* + * Restore Memory Controller settings after "System Suspend" + */ +void tegra_memctrl_restore_settings(void) +{ + tegra_memctrl_setup(); +} + +/* * Secure the BL31 DRAM aperture. * * phys_base = physical base of TZDRAM aperture @@ -107,6 +115,20 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); } +/* + * Secure the BL31 TZRAM aperture. + * + * phys_base = physical base of TZRAM aperture + * size_in_bytes = size of aperture in bytes + */ +void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) +{ + /* + * The v1 hardware controller does not have any registers + * for setting up the on-chip TZRAM. + */ +} + static void tegra_clear_videomem(uintptr_t non_overlap_area_start, unsigned long long non_overlap_area_size) { @@ -114,13 +136,13 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start, * Perform cache maintenance to ensure that the non-overlapping area is * zeroed out. The first invalidation of this range ensures that * possible evictions of dirty cache lines do not interfere with the - * 'zeromem16' operation. Other CPUs could speculatively prefetch the + * 'zeromem' operation. Other CPUs could speculatively prefetch the * main memory contents of this area between the first invalidation and - * the 'zeromem16' operation. The second invalidation ensures that any + * the 'zeromem' operation. The second invalidation ensures that any * such cache lines are removed as well. */ inv_dcache_range(non_overlap_area_start, non_overlap_area_size); - zeromem16((void *)non_overlap_area_start, non_overlap_area_size); + zeromem((void *)non_overlap_area_start, non_overlap_area_size); inv_dcache_range(non_overlap_area_start, non_overlap_area_size); } diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 0fd7c821..72da4b3c 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -37,12 +37,14 @@ #include <cortex_a57.h> #include <cortex_a53.h> #include <debug.h> +#include <denver.h> #include <errno.h> #include <memctrl.h> #include <mmio.h> #include <platform.h> #include <platform_def.h> #include <stddef.h> +#include <tegra_def.h> #include <tegra_private.h> /******************************************************************************* @@ -54,6 +56,7 @@ extern unsigned long __RO_END__; extern unsigned long __BL31_END__; extern uint64_t tegra_bl31_phys_base; +extern uint64_t tegra_console_base; /* * The next 3 constants identify the extents of the code, RO data region and the @@ -110,28 +113,47 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, { plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)plat_params_from_bl2; +#if DEBUG + int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; +#endif /* - * Configure the UART port to be used as the console + * Copy BL3-3, BL3-2 entry point information. + * They are stored in Secure RAM, in BL2's address space. */ - console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ, - TEGRA_CONSOLE_BAUDRATE); + assert(from_bl2->bl33_ep_info); + bl33_image_ep_info = *from_bl2->bl33_ep_info; - /* Initialise crash console */ - plat_crash_console_init(); + if (from_bl2->bl32_ep_info) + bl32_image_ep_info = *from_bl2->bl32_ep_info; /* - * Copy BL3-3, BL3-2 entry point information. - * They are stored in Secure RAM, in BL2's address space. + * Parse platform specific parameters - TZDRAM aperture base and size */ - bl33_image_ep_info = *from_bl2->bl33_ep_info; - bl32_image_ep_info = *from_bl2->bl32_ep_info; + assert(plat_params); + plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; + plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; + plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; /* - * Parse platform specific parameters - TZDRAM aperture size + * Get the base address of the UART controller to be used for the + * console */ - if (plat_params) - plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; + assert(plat_params->uart_id); + tegra_console_base = plat_get_console_from_id(plat_params->uart_id); + + /* + * Configure the UART port to be used as the console + */ + assert(tegra_console_base); + console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, + TEGRA_CONSOLE_BAUDRATE); + + /* Initialise crash console */ + plat_crash_console_init(); + + INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? + "Denver" : "ARM", read_mpidr()); } /******************************************************************************* @@ -159,15 +181,33 @@ void bl31_platform_setup(void) /* * Do initial security configuration to allow DRAM/device access. */ - tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, plat_bl31_params_from_bl2.tzdram_size); + /* + * Set up the TZRAM memory aperture to allow only secure world + * access + */ + tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); + /* Set the next EL to be AArch64 */ tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; write_scr(tmp_reg); /* Initialize the gic cpu and distributor interfaces */ tegra_gic_setup(); + + INFO("BL3-1: Tegra platform setup complete\n"); +} + +/******************************************************************************* + * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit + ******************************************************************************/ +void bl31_plat_runtime_setup(void) +{ + /* Initialize the runtime console */ + console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, + TEGRA_CONSOLE_BAUDRATE); } /******************************************************************************* @@ -185,6 +225,7 @@ void bl31_plat_arch_setup(void) #if USE_COHERENT_MEM unsigned long coh_start, coh_size; #endif + plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); /* add memory regions */ mmap_add_region(total_base, total_base, @@ -194,6 +235,14 @@ void bl31_plat_arch_setup(void) ro_size, MT_MEMORY | MT_RO | MT_SECURE); + /* map TZDRAM used by BL31 as coherent memory */ + if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { + mmap_add_region(params_from_bl2->tzdram_base, + params_from_bl2->tzdram_base, + BL31_SIZE, + MT_DEVICE | MT_RW | MT_SECURE); + } + #if USE_COHERENT_MEM coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; @@ -215,6 +264,8 @@ void bl31_plat_arch_setup(void) /* enable the MMU */ enable_mmu_el3(0); + + INFO("BL3-1: Tegra: MMU enabled\n"); } /******************************************************************************* diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk index 3c07032d..c9e92557 100644 --- a/plat/nvidia/tegra/common/tegra_common.mk +++ b/plat/nvidia/tegra/common/tegra_common.mk @@ -54,9 +54,7 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \ plat/common/aarch64/platform_mp_stack.S \ plat/common/plat_psci_common.c \ ${COMMON_DIR}/aarch64/tegra_helpers.S \ - ${COMMON_DIR}/drivers/memctrl/memctrl.c \ ${COMMON_DIR}/drivers/pmc/pmc.c \ - ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ ${COMMON_DIR}/tegra_bl31_setup.c \ ${COMMON_DIR}/tegra_delay_timer.c \ ${COMMON_DIR}/tegra_gic.c \ diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index 6fb3e9c6..f5ef3e76 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -54,7 +54,9 @@ extern uint64_t tegra_sec_entry_point; #pragma weak tegra_soc_pwr_domain_on #pragma weak tegra_soc_pwr_domain_off #pragma weak tegra_soc_pwr_domain_on_finish +#pragma weak tegra_soc_pwr_domain_power_down_wfi #pragma weak tegra_soc_prepare_system_reset +#pragma weak tegra_soc_prepare_system_off int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) { @@ -76,11 +78,22 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) return PSCI_E_SUCCESS; } +int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) +{ + return PSCI_E_SUCCESS; +} + int tegra_soc_prepare_system_reset(void) { return PSCI_E_SUCCESS; } +__dead2 void tegra_soc_prepare_system_off(void) +{ + ERROR("Tegra System Off: operation not handled.\n"); + panic(); +} + /******************************************************************************* * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` * call to get the `power_state` parameter. This allows the platform to encode @@ -129,7 +142,7 @@ void tegra_pwr_domain_off(const psci_power_state_t *target_state) } /******************************************************************************* - * Handler called when called when a power domain is about to be suspended. The + * Handler called when a power domain is about to be suspended. The * target_state encodes the power state that each level should transition to. ******************************************************************************/ void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) @@ -141,6 +154,24 @@ void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) } /******************************************************************************* + * Handler called at the end of the power domain suspend sequence. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +__dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t + *target_state) +{ + /* call the chip's power down handler */ + tegra_soc_pwr_domain_power_down_wfi(target_state); + + /* enter power down state */ + wfi(); + + /* we can never reach here */ + ERROR("%s: operation not handled.\n", __func__); + panic(); +} + +/******************************************************************************* * Handler called when a power domain has just been powered on after * being turned off earlier. The target_state encodes the low power state that * each level has woken up from. @@ -161,20 +192,16 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) PSTATE_ID_SOC_POWERDN) { /* - * Lock scratch registers which hold the CPU vectors. - */ - tegra_pmc_lock_cpu_vectors(); - - /* - * SMMU configuration. + * Restore Memory Controller settings as it loses state + * during system suspend. */ - tegra_memctrl_setup(); + tegra_memctrl_restore_settings(); /* * Security configuration to allow DRAM/device access. */ plat_params = bl31_get_plat_params(); - tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + tegra_memctrl_tzdram_setup(plat_params->tzdram_base, plat_params->tzdram_size); } @@ -199,8 +226,9 @@ void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) ******************************************************************************/ __dead2 void tegra_system_off(void) { - ERROR("Tegra System Off: operation not handled.\n"); - panic(); + INFO("Powering down system...\n"); + + tegra_soc_prepare_system_off(); } /******************************************************************************* @@ -208,6 +236,8 @@ __dead2 void tegra_system_off(void) ******************************************************************************/ __dead2 void tegra_system_reset(void) { + INFO("Restarting system...\n"); + /* per-SoC system reset handler */ tegra_soc_prepare_system_reset(); @@ -223,13 +253,8 @@ __dead2 void tegra_system_reset(void) int32_t tegra_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) { - int pwr_lvl = psci_get_pstate_pwrlvl(power_state); - assert(req_state); - if (pwr_lvl > PLAT_MAX_PWR_LVL) - return PSCI_E_INVALID_PARAMS; - return tegra_soc_validate_power_state(power_state, req_state); } @@ -258,6 +283,7 @@ static const plat_psci_ops_t tegra_plat_psci_ops = { .pwr_domain_suspend = tegra_pwr_domain_suspend, .pwr_domain_on_finish = tegra_pwr_domain_on_finish, .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, + .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi, .system_off = tegra_system_off, .system_reset = tegra_system_reset, .validate_power_state = tegra_validate_power_state, diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c index de36a3c6..3bcd4418 100644 --- a/plat/nvidia/tegra/common/tegra_sip_calls.c +++ b/plat/nvidia/tegra/common/tegra_sip_calls.c @@ -32,28 +32,32 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> -#include <context_mgmt.h> #include <debug.h> #include <errno.h> #include <memctrl.h> #include <runtime_svc.h> #include <tegra_private.h> -#define NS_SWITCH_AARCH32 1 -#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT) - /******************************************************************************* - * Tegra SiP SMCs + * Common Tegra SiP SMCs ******************************************************************************/ #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 -#define TEGRA_SIP_AARCH_SWITCH 0x82000004 /******************************************************************************* - * SPSR settings for AARCH32/AARCH64 modes + * SoC specific SiP handler ******************************************************************************/ -#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \ - DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT) -#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS) +#pragma weak plat_sip_handler +int plat_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + return -ENOTSUP; +} /******************************************************************************* * This function is responsible for handling all SiP calls from the NS world @@ -75,6 +79,11 @@ uint64_t tegra_sip_handler(uint32_t smc_fid, if (!ns) SMC_RET1(handle, SMC_UNK); + /* Check if this is a SoC specific SiP */ + err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); + if (err == 0) + SMC_RET1(handle, err); + switch (smc_fid) { case TEGRA_SIP_NEW_VIDEOMEM_REGION: @@ -105,29 +114,6 @@ uint64_t tegra_sip_handler(uint32_t smc_fid, SMC_RET1(handle, 0); break; - case TEGRA_SIP_AARCH_SWITCH: - - /* clean up the high bits */ - x1 = (uint32_t)x1; - x2 = (uint32_t)x2; - - if (!x1 || x2 > NS_SWITCH_AARCH32) { - ERROR("%s: invalid parameters\n", __func__); - SMC_RET1(handle, SMC_UNK); - } - - /* x1 = ns entry point */ - cm_set_elr_spsr_el3(NON_SECURE, x1, - (x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64); - - /* switch NS world mode */ - cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2); - - INFO("CPU switched to AARCH%s mode\n", - (x2 == NS_SWITCH_AARCH32) ? "32" : "64"); - SMC_RET1(handle, 0); - break; - default: ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); break; diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h index 26c80576..a3f08755 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl.h +++ b/plat/nvidia/tegra/include/drivers/memctrl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,55 +31,10 @@ #ifndef __MEMCTRL_H__ #define __MEMCTRL_H__ -#include <mmio.h> -#include <tegra_def.h> - -/* SMMU registers */ -#define MC_SMMU_CONFIG_0 0x10 -#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 -#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 -#define MC_SMMU_TLB_CONFIG_0 0x14 -#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 -#define MC_SMMU_PTC_CONFIG_0 0x18 -#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f -#define MC_SMMU_TLB_FLUSH_0 0x30 -#define TLB_FLUSH_VA_MATCH_ALL 0 -#define TLB_FLUSH_ASID_MATCH_DISABLE 0 -#define TLB_FLUSH_ASID_MATCH_SHIFT 31 -#define MC_SMMU_TLB_FLUSH_ALL \ - (TLB_FLUSH_VA_MATCH_ALL | \ - (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) -#define MC_SMMU_PTC_FLUSH_0 0x34 -#define MC_SMMU_PTC_FLUSH_ALL 0 -#define MC_SMMU_ASID_SECURITY_0 0x38 -#define MC_SMMU_ASID_SECURITY 0 -#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 -#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c -#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 -#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 -#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 -#define MC_SMMU_TRANSLATION_ENABLE (~0) - -/* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 - -/* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c - -static inline uint32_t tegra_mc_read_32(uint32_t off) -{ - return mmio_read_32(TEGRA_MC_BASE + off); -} - -static inline void tegra_mc_write_32(uint32_t off, uint32_t val) -{ - mmio_write_32(TEGRA_MC_BASE + off, val); -} - void tegra_memctrl_setup(void); +void tegra_memctrl_restore_settings(void); void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); +void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes); void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); #endif /* __MEMCTRL_H__ */ diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v1.h b/plat/nvidia/tegra/include/drivers/memctrl_v1.h new file mode 100644 index 00000000..e44a9ea9 --- /dev/null +++ b/plat/nvidia/tegra/include/drivers/memctrl_v1.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MEMCTRLV1_H__ +#define __MEMCTRLV1_H__ + +#include <mmio.h> +#include <tegra_def.h> + +/* SMMU registers */ +#define MC_SMMU_CONFIG_0 0x10 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 +#define MC_SMMU_TLB_CONFIG_0 0x14 +#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 +#define MC_SMMU_PTC_CONFIG_0 0x18 +#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f +#define MC_SMMU_TLB_FLUSH_0 0x30 +#define TLB_FLUSH_VA_MATCH_ALL 0 +#define TLB_FLUSH_ASID_MATCH_DISABLE 0 +#define TLB_FLUSH_ASID_MATCH_SHIFT 31 +#define MC_SMMU_TLB_FLUSH_ALL \ + (TLB_FLUSH_VA_MATCH_ALL | \ + (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) +#define MC_SMMU_PTC_FLUSH_0 0x34 +#define MC_SMMU_PTC_FLUSH_ALL 0 +#define MC_SMMU_ASID_SECURITY_0 0x38 +#define MC_SMMU_ASID_SECURITY 0 +#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 +#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c +#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 +#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 +#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 +#define MC_SMMU_TRANSLATION_ENABLE (~0) + +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + +static inline uint32_t tegra_mc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_MC_BASE + off); +} + +static inline void tegra_mc_write_32(uint32_t off, uint32_t val) +{ + mmio_write_32(TEGRA_MC_BASE + off, val); +} + +#endif /* __MEMCTRLV1_H__ */ diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index cd06d93f..ad245e2f 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -53,12 +53,6 @@ PLATFORM_CLUSTER_COUNT + 1) /******************************************************************************* - * Platform power states - ******************************************************************************/ -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) - -/******************************************************************************* * Platform console related constants ******************************************************************************/ #define TEGRA_CONSOLE_BAUDRATE 115200 @@ -74,7 +68,7 @@ /******************************************************************************* * BL31 specific defines. ******************************************************************************/ -#define BL31_SIZE 0x20000 +#define BL31_SIZE 0x40000 #define BL31_BASE TZDRAM_BASE #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) @@ -84,8 +78,6 @@ * Platform specific page table and MMU setup constants ******************************************************************************/ #define ADDR_SPACE_SIZE (1ull << 32) -#define MAX_XLAT_TABLES 3 -#define MAX_MMAP_REGIONS 8 /******************************************************************************* * Some data must be aligned on the biggest cache line size in the platform. diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index 683c9038..318f4def 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -40,6 +40,15 @@ #define PSTATE_ID_SOC_POWERDN 0xD /******************************************************************************* + * Platform power states (used by PSCI framework) + * + * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID + * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID + ******************************************************************************/ +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) + +/******************************************************************************* * GIC memory map ******************************************************************************/ #define TEGRA_GICD_BASE 0x50041000 @@ -71,6 +80,15 @@ #define TEGRA_EVP_BASE 0x6000F000 /******************************************************************************* + * Tegra UART controller base addresses + ******************************************************************************/ +#define TEGRA_UARTA_BASE 0x70006000 +#define TEGRA_UARTB_BASE 0x70006040 +#define TEGRA_UARTC_BASE 0x70006200 +#define TEGRA_UARTD_BASE 0x70006300 +#define TEGRA_UARTE_BASE 0x70006400 + +/******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ #define TEGRA_PMC_BASE 0x7000E400 @@ -80,4 +98,10 @@ ******************************************************************************/ #define TEGRA_MC_BASE 0x70019000 +/******************************************************************************* + * Tegra TZRAM constants + ******************************************************************************/ +#define TEGRA_TZRAM_BASE 0x7C010000 +#define TEGRA_TZRAM_SIZE 0x10000 + #endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index 750e6e3f..ce85427e 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -48,18 +48,13 @@ #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN /******************************************************************************* - * Implementation defined ACTLR_EL3 bit definitions + * Platform power states (used by PSCI framework) + * + * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID + * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID ******************************************************************************/ -#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) -#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) -#define ACTLR_EL3_L2CTLR_BIT (1 << 4) -#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) -#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) -#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ - ACTLR_EL3_L2ECTLR_BIT | \ - ACTLR_EL3_L2CTLR_BIT | \ - ACTLR_EL3_CPUECTLR_BIT | \ - ACTLR_EL3_CPUACTLR_BIT) +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) /******************************************************************************* * GIC memory map @@ -110,6 +105,15 @@ #define TEGRA_EVP_BASE 0x6000F000 /******************************************************************************* + * Tegra UART controller base addresses + ******************************************************************************/ +#define TEGRA_UARTA_BASE 0x70006000 +#define TEGRA_UARTB_BASE 0x70006040 +#define TEGRA_UARTC_BASE 0x70006200 +#define TEGRA_UARTD_BASE 0x70006300 +#define TEGRA_UARTE_BASE 0x70006400 + +/******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ #define TEGRA_PMC_BASE 0x7000E400 @@ -119,4 +123,10 @@ ******************************************************************************/ #define TEGRA_MC_BASE 0x70019000 +/******************************************************************************* + * Tegra TZRAM constants + ******************************************************************************/ +#define TEGRA_TZRAM_BASE 0x7C010000 +#define TEGRA_TZRAM_SIZE 0x10000 + #endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index cf75d9f5..75416ec3 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -43,7 +43,12 @@ #define TEGRA_DRAM_END 0x27FFFFFFF typedef struct plat_params_from_bl2 { + /* TZ memory size */ uint64_t tzdram_size; + /* TZ memory base */ + uint64_t tzdram_base; + /* UART port ID */ + int uart_id; } plat_params_from_bl2_t; /* Declarations for plat_psci_handlers.c */ @@ -52,6 +57,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, /* Declarations for plat_setup.c */ const mmap_region_t *plat_get_mmio_map(void); +uint32_t plat_get_console_from_id(int id); /* Declarations for plat_secondary.c */ void plat_secondary_setup(void); diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk index cec7caff..756899cb 100644 --- a/plat/nvidia/tegra/platform.mk +++ b/plat/nvidia/tegra/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -30,6 +30,9 @@ SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC} +# Enable PSCI v1.0 extended state ID format +PSCI_EXTENDED_STATE_ID := 1 + # Disable the PSCI platform compatibility layer ENABLE_PLAT_COMPAT := 0 diff --git a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c index 48a2fbaa..f05f3d0e 100644 --- a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -59,36 +59,15 @@ static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; int32_t tegra_soc_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) { - int pwr_lvl = psci_get_pstate_pwrlvl(power_state); int state_id = psci_get_pstate_id(power_state); int cpu = read_mpidr() & MPIDR_CPU_MASK; - if (pwr_lvl > PLAT_MAX_PWR_LVL) - return PSCI_E_INVALID_PARAMS; - - /* Sanity check the requested afflvl */ - if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { - /* - * It's possible to enter standby only on affinity level 0 i.e. - * a cpu on Tegra. Ignore any other affinity level. - */ - if (pwr_lvl != MPIDR_AFFLVL0) - return PSCI_E_INVALID_PARAMS; - - /* power domain in standby state */ - req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE; - - return PSCI_E_SUCCESS; - } - /* * Sanity check the requested state id, power level and CPU number. * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU * i.e. CPU 0 */ - if ((pwr_lvl != PLAT_MAX_PWR_LVL) || - (state_id != PSTATE_ID_SOC_POWERDN) || - (cpu != 0)) { + if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) { ERROR("unsupported state id @ power level\n"); return PSCI_E_INVALID_PARAMS; } @@ -128,9 +107,26 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr) return PSCI_E_SUCCESS; } +int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + /* + * Lock scratch registers which hold the CPU vectors + */ + tegra_pmc_lock_cpu_vectors(); + + return PSCI_E_SUCCESS; +} + int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) { tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); + + /* Disable DCO operations */ + denver_disable_dco(); + + /* Power down the CPU */ + write_actlr_el1(DENVER_CPU_STATE_POWER_DOWN); + return PSCI_E_SUCCESS; } @@ -149,7 +145,10 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* Program FC to enter suspend state */ tegra_fc_cpu_powerdn(read_mpidr()); - /* Suspend DCO operations */ + /* Disable DCO operations */ + denver_disable_dco(); + + /* Program the suspend state ID */ write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]); return PSCI_E_SUCCESS; diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c index 0d664137..337a2c59 100644 --- a/plat/nvidia/tegra/soc/t132/plat_setup.c +++ b/plat/nvidia/tegra/soc/t132/plat_setup.c @@ -78,3 +78,31 @@ unsigned int plat_get_syscnt_freq2(void) { return 12000000; } + +/******************************************************************************* + * Maximum supported UART controllers + ******************************************************************************/ +#define TEGRA132_MAX_UART_PORTS 5 + +/******************************************************************************* + * This variable holds the UART port base addresses + ******************************************************************************/ +static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = { + 0, /* undefined - treated as an error case */ + TEGRA_UARTA_BASE, + TEGRA_UARTB_BASE, + TEGRA_UARTC_BASE, + TEGRA_UARTD_BASE, + TEGRA_UARTE_BASE, +}; + +/******************************************************************************* + * Retrieve the UART controller base to be used as the console + ******************************************************************************/ +uint32_t plat_get_console_from_id(int id) +{ + if (id > TEGRA132_MAX_UART_PORTS) + return 0; + + return tegra132_uart_addresses[id]; +} diff --git a/plat/nvidia/tegra/soc/t132/plat_sip_calls.c b/plat/nvidia/tegra/soc/t132/plat_sip_calls.c new file mode 100644 index 00000000..6c89944e --- /dev/null +++ b/plat/nvidia/tegra/soc/t132/plat_sip_calls.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <assert.h> +#include <bl_common.h> +#include <context_mgmt.h> +#include <debug.h> +#include <errno.h> +#include <tegra_private.h> + +#define NS_SWITCH_AARCH32 1 +#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT) + +/******************************************************************************* + * Tegra132 SiP SMCs + ******************************************************************************/ +#define TEGRA_SIP_AARCH_SWITCH 0x82000004 + +/******************************************************************************* + * SPSR settings for AARCH32/AARCH64 modes + ******************************************************************************/ +#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \ + DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT) +#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS) + +/******************************************************************************* + * This function is responsible for handling all T132 SiP calls + ******************************************************************************/ +int plat_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + switch (smc_fid) { + + case TEGRA_SIP_AARCH_SWITCH: + + /* clean up the high bits */ + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + + if (!x1 || x2 > NS_SWITCH_AARCH32) { + ERROR("%s: invalid parameters\n", __func__); + return -EINVAL; + } + + /* x1 = ns entry point */ + cm_set_elr_spsr_el3(NON_SECURE, x1, + (x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64); + + /* switch NS world mode */ + cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2); + + INFO("CPU switched to AARCH%s mode\n", + (x2 == NS_SWITCH_AARCH32) ? "32" : "64"); + return 0; + + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + break; + } + + return -ENOTSUP; +} diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk index 69d62964..6b9fce3b 100644 --- a/plat/nvidia/tegra/soc/t132/platform_t132.mk +++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk @@ -28,9 +28,6 @@ # POSSIBILITY OF SUCH DAMAGE. # -TEGRA_BOOT_UART_BASE := 0x70006300 -$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) - TZDRAM_BASE := 0xF5C00000 $(eval $(call add_define,TZDRAM_BASE)) @@ -40,7 +37,16 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) PLATFORM_MAX_CPUS_PER_CLUSTER := 2 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) +MAX_XLAT_TABLES := 3 +$(eval $(call add_define,MAX_XLAT_TABLES)) + +MAX_MMAP_REGIONS := 8 +$(eval $(call add_define,MAX_MMAP_REGIONS)) + BL31_SOURCES += lib/cpus/aarch64/denver.S \ + ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ + ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ ${SOC_DIR}/plat_psci_handlers.c \ + ${SOC_DIR}/plat_sip_calls.c \ ${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_secondary.c diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c index b184063d..95fb93fe 100644 --- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -58,39 +58,14 @@ static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; int32_t tegra_soc_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) { - int pwr_lvl = psci_get_pstate_pwrlvl(power_state); int state_id = psci_get_pstate_id(power_state); - if (pwr_lvl > PLAT_MAX_PWR_LVL) { - ERROR("%s: unsupported power_state (0x%x)\n", __func__, - power_state); - return PSCI_E_INVALID_PARAMS; - } - - /* Sanity check the requested afflvl */ - if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { - /* - * It's possible to enter standby only on affinity level 0 i.e. - * a cpu on Tegra. Ignore any other affinity level. - */ - if (pwr_lvl != MPIDR_AFFLVL0) - return PSCI_E_INVALID_PARAMS; - - /* power domain in standby state */ - req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE; - - return PSCI_E_SUCCESS; - } - /* Sanity check the requested state id */ switch (state_id) { case PSTATE_ID_CORE_POWERDN: /* * Core powerdown request only for afflvl 0 */ - if (pwr_lvl != MPIDR_AFFLVL0) - goto error; - req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; break; @@ -100,9 +75,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, /* * Cluster powerdown/idle request only for afflvl 1 */ - if (pwr_lvl != MPIDR_AFFLVL1) - goto error; - req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; @@ -112,9 +84,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, /* * System powerdown request only for afflvl 2 */ - if (pwr_lvl != PLAT_MAX_PWR_LVL) - goto error; - for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; @@ -129,10 +98,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, } return PSCI_E_SUCCESS; - -error: - ERROR("%s: unsupported state id (%d)\n", __func__, state_id); - return PSCI_E_INVALID_PARAMS; } int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) @@ -190,6 +155,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) PLAT_SYS_SUSPEND_STATE_ID) { /* + * Lock scratch registers which hold the CPU vectors + */ + tegra_pmc_lock_cpu_vectors(); + + /* * Enable WRAP to INCR burst type conversions for * incoming requests on the AXI slave ports. */ diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c index 70a55c69..246faf87 100644 --- a/plat/nvidia/tegra/soc/t210/plat_setup.c +++ b/plat/nvidia/tegra/soc/t210/plat_setup.c @@ -84,3 +84,31 @@ unsigned int plat_get_syscnt_freq2(void) { return 19200000; } + +/******************************************************************************* + * Maximum supported UART controllers + ******************************************************************************/ +#define TEGRA210_MAX_UART_PORTS 5 + +/******************************************************************************* + * This variable holds the UART port base addresses + ******************************************************************************/ +static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { + 0, /* undefined - treated as an error case */ + TEGRA_UARTA_BASE, + TEGRA_UARTB_BASE, + TEGRA_UARTC_BASE, + TEGRA_UARTD_BASE, + TEGRA_UARTE_BASE, +}; + +/******************************************************************************* + * Retrieve the UART controller base to be used as the console + ******************************************************************************/ +uint32_t plat_get_console_from_id(int id) +{ + if (id > TEGRA210_MAX_UART_PORTS) + return 0; + + return tegra210_uart_addresses[id]; +} diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk index 5001629d..2c908f9d 100644 --- a/plat/nvidia/tegra/soc/t210/platform_t210.mk +++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -28,32 +28,28 @@ # POSSIBILITY OF SUCH DAMAGE. # -TEGRA_BOOT_UART_BASE := 0x70006000 -$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) - TZDRAM_BASE := 0xFDC00000 $(eval $(call add_define,TZDRAM_BASE)) ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1 $(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT)) -ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1 -$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS)) - -ENABLE_L2_DYNAMIC_RETENTION := 1 -$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION)) - -ENABLE_CPU_DYNAMIC_RETENTION := 1 -$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION)) - PLATFORM_CLUSTER_COUNT := 2 $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) PLATFORM_MAX_CPUS_PER_CLUSTER := 4 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) +MAX_XLAT_TABLES := 3 +$(eval $(call add_define,MAX_XLAT_TABLES)) + +MAX_MMAP_REGIONS := 8 +$(eval $(call add_define,MAX_MMAP_REGIONS)) + BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ + ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ + ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ ${SOC_DIR}/plat_psci_handlers.c \ ${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_secondary.c diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c index dba3beeb..738d671a 100644 --- a/plat/qemu/qemu_bl2_setup.c +++ b/plat/qemu/qemu_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,7 +35,7 @@ #include <platform_def.h> #include "qemu_private.h" #include <string.h> - +#include <utils.h> /* * The next 2 constants identify the extents of the code & RO data region. @@ -91,7 +91,7 @@ bl31_params_t *bl2_plat_get_bl31_params(void) * Initialise the memory for all the arguments that needs to * be passed to BL3-1 */ - memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); + zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); /* Assign memory for TF related information */ bl2_to_bl31_params = &bl31_params_mem.bl31_params; diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h index b2234a65..9638aae3 100644 --- a/plat/rockchip/common/include/plat_private.h +++ b/plat/rockchip/common/include/plat_private.h @@ -44,6 +44,7 @@ extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; +extern uint32_t __sram_incbin_start, __sram_incbin_end; /****************************************************************************** * For rockchip socs pm ops diff --git a/plat/rockchip/common/pmusram/pmu_sram.c b/plat/rockchip/common/pmusram/pmu_sram.c index 120220ae..82d55ba8 100644 --- a/plat/rockchip/common/pmusram/pmu_sram.c +++ b/plat/rockchip/common/pmusram/pmu_sram.c @@ -62,6 +62,12 @@ void rockchip_plat_sram_mmu_el3(void) mmap_add_region((unsigned long)&__bl31_sram_data_start, (unsigned long)&__bl31_sram_data_start, sram_size, MT_MEMORY | MT_RW | MT_SECURE); + + /* sram.incbin size */ + sram_size = (char *)&__sram_incbin_end - (char *)&__sram_incbin_start; + mmap_add_region((unsigned long)&__sram_incbin_start, + (unsigned long)&__sram_incbin_start, + sram_size, MT_NON_CACHEABLE | MT_RW | MT_SECURE); #else /* TODO: Support other SoCs, Just support RK3399 now */ return; diff --git a/plat/rockchip/rk3399/drivers/dram/dcf_code.inc b/plat/rockchip/rk3399/drivers/dram/dcf_code.inc deleted file mode 100644 index 53196a02..00000000 --- a/plat/rockchip/rk3399/drivers/dram/dcf_code.inc +++ /dev/null @@ -1,364 +0,0 @@ - 0x0 , - 0x4f8c120c , - 0x0 , - 0x4f8c1210 , - 0x100000 , - 0x1f310019 , - 0x0 , - 0xb0000001 , - 0x58 , - 0xd0000000 , - 0x1300 , - 0x1f760329 , - 0x0 , - 0xb0000001 , - 0x40 , - 0xd0000000 , - 0xc , - 0x1f760371 , - 0x0 , - 0xb0000001 , - 0x28 , - 0xd0000000 , - 0x400000 , - 0x1f900009 , - 0x0 , - 0xb0000001 , - 0x10 , - 0xd0000000 , - 0x1 , - 0x4f8c120c , - 0x100000 , - 0x1f310019 , - 0x0 , - 0xb0000001 , - 0x58 , - 0xd0000000 , - 0x2c00 , - 0x1f760329 , - 0x0 , - 0xb0000001 , - 0x40 , - 0xd0000000 , - 0xc0 , - 0x1f760371 , - 0x0 , - 0xb0000001 , - 0x28 , - 0xd0000000 , - 0x400000 , - 0x1f8f0009 , - 0x0 , - 0xb0000001 , - 0x10 , - 0xd0000000 , - 0x1 , - 0x4f8c1210 , - 0x0 , - 0x4f8c1220 , - 0x0 , - 0x4f8c121c , - 0x0 , - 0xaf8c120d , - 0x108 , - 0xd0000000 , - 0x2000 , - 0x1f900009 , - 0x0 , - 0xa0000001 , - 0x30 , - 0xd0000000 , - 0x0 , - 0x4f8c1220 , - 0x0 , - 0x4f8c121c , - 0x0 , - 0x10000001 , - 0x0 , - 0xa0000001 , - 0xb0 , - 0xd0000000 , - 0x8000 , - 0x1f900009 , - 0x0 , - 0xa0000001 , - 0x30 , - 0xd0000000 , - 0x1 , - 0x4f8c1220 , - 0x1 , - 0x4f8c121c , - 0x0 , - 0x10000001 , - 0x0 , - 0xa0000001 , - 0x70 , - 0xd0000000 , - 0x4000 , - 0x1f900009 , - 0x0 , - 0xa0000001 , - 0x30 , - 0xd0000000 , - 0x0 , - 0x4f8c1220 , - 0x1 , - 0x4f8c121c , - 0x0 , - 0x10000001 , - 0x0 , - 0xa0000001 , - 0x30 , - 0xd0000000 , - 0x1000 , - 0x1f900009 , - 0x0 , - 0xa0000001 , - 0x18 , - 0xd0000000 , - 0x0 , - 0x4f8c1220 , - 0x1 , - 0x4f8c121c , - 0x0 , - 0x10000001 , - 0x0 , - 0xa0000001 , - 0x100 , - 0xd0000000 , - 0x0 , - 0xaf8c1211 , - 0xf0 , - 0xd0000000 , - 0x2000 , - 0x1f8f0009 , - 0x0 , - 0xa0000001 , - 0x30 , - 0xd0000000 , - 0x0 , - 0x4f8c1220 , - 0x0 , - 0x4f8c121c , - 0x0 , - 0x10000001 , - 0x0 , - 0xa0000001 , - 0xb0 , - 0xd0000000 , - 0x8000 , - 0x1f8f0009 , - 0x0 , - 0xa0000001 , - 0x30 , - 0xd0000000 , - 0x1 , - 0x4f8c1220 , - 0x1 , - 0x4f8c121c , - 0x0 , - 0x10000001 , - 0x0 , - 0xa0000001 , - 0x70 , - 0xd0000000 , - 0x4000 , - 0x1f8f0009 , - 0x0 , - 0xa0000001 , - 0x30 , - 0xd0000000 , - 0x0 , - 0x4f8c1220 , - 0x1 , - 0x4f8c121c , - 0x0 , - 0x10000001 , - 0x0 , - 0xa0000001 , - 0x30 , - 0xd0000000 , - 0x1000 , - 0x1f8f0009 , - 0x0 , - 0xa0000001 , - 0x18 , - 0xd0000000 , - 0x0 , - 0x4f8c1220 , - 0x1 , - 0x4f8c121c , - 0x0 , - 0xaf8c120d , - 0x40 , - 0xd0000000 , - 0x80008000 , - 0x7f900284 , - 0x1 , - 0x0 , - 0x8000 , - 0x1f90028d , - 0x0 , - 0x60000001 , - 0x0 , - 0x10000001 , - 0x0 , - 0xa0000001 , - 0x38 , - 0xd0000000 , - 0x0 , - 0xaf8c1211 , - 0x28 , - 0xd0000000 , - 0x80008000 , - 0x7f8f0284 , - 0x1 , - 0x0 , - 0x8000 , - 0x1f8f028d , - 0x0 , - 0x60000001 , - 0xffffffff , - 0x4f77e200 , - 0xffffffff , - 0x4f77e204 , - 0xffffffff , - 0x4f77e208 , - 0xffffffff , - 0x4f77e20c , - 0x70007000 , - 0x4f77e210 , - 0x3fffffff , - 0x7f750130 , - 0x0 , - 0x2f310061 , - 0xc0000 , - 0x20000001 , - 0x0 , - 0x4f310061 , - 0xc0000 , - 0x1f310065 , - 0xc0000 , - 0xb0000001 , - 0x10 , - 0xc0000000 , - 0x0 , - 0xaf8c121d , - 0x48 , - 0xd0000000 , - 0x0 , - 0xaf8c120d , - 0x18 , - 0xd0000000 , - 0x80000000 , - 0x2f90000d , - 0x0 , - 0x4f90000d , - 0x0 , - 0xaf8c1211 , - 0x18 , - 0xd0000000 , - 0x80000000 , - 0x2f90000d , - 0x0 , - 0x4f8f000d , - 0x0 , - 0x2f8c101d , - 0x350005 , - 0x20000001 , - 0x0 , - 0x4f620001 , - 0x1 , - 0x0 , - 0x4 , - 0x1f620011 , - 0x0 , - 0x60000001 , - 0x3000000 , - 0x7f76004c , - 0x18 , - 0x0 , - 0x10001 , - 0x7f76004c , - 0x0 , - 0x2f8c1005 , - 0x0 , - 0x4f760041 , - 0x0 , - 0x2f8c1009 , - 0x0 , - 0x4f760045 , - 0x10000 , - 0x7f76004c , - 0x18 , - 0x0 , - 0x1 , - 0x0 , - 0x80000000 , - 0x1f760049 , - 0x0 , - 0x60000001 , - 0x3000100 , - 0x7f76004c , - 0x3e8 , - 0x0 , - 0x20002 , - 0x4f620000 , - 0x1 , - 0x0 , - 0x1 , - 0x1f620011 , - 0x0 , - 0x60000001 , - 0x0 , - 0xaf8c121d , - 0x48 , - 0xd0000000 , - 0x0 , - 0xaf8c120d , - 0x18 , - 0xd0000000 , - 0x7fffffff , - 0x1f90000d , - 0x0 , - 0x4f90000d , - 0x0 , - 0xaf8c1211 , - 0x18 , - 0xd0000000 , - 0x7fffffff , - 0x1f90000d , - 0x0 , - 0x4f8f000d , - 0xfff3ffff , - 0x1f310061 , - 0x0 , - 0x7f310061 , - 0xc0000 , - 0x1f310065 , - 0x0 , - 0xb0000001 , - 0x10 , - 0xc0000000 , - 0x0 , - 0x7f750130 , - 0x1 , - 0x0 , - 0x1 , - 0x0 , - 0x1 , - 0x0 , - 0x1 , - 0x0 , - 0x1 , - 0x0 , - 0x1 , - 0x0 , - 0x1 , - 0x0 , - 0x1 , - 0x0 , - 0x1 , - 0x0 , - 0x0 , - 0xe0000000 , diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index 4fdd3894..f589a8ad 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -28,8 +28,10 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include <arch_helpers.h> #include <debug.h> #include <mmio.h> +#include <m0_ctl.h> #include <plat_private.h> #include "dfs.h" #include "dram.h" @@ -40,31 +42,14 @@ #include <delay_timer.h> -#define CTL_TRAINING (1) -#define PI_TRAINING (!CTL_TRAINING) - -#define EN_READ_GATE_TRAINING (1) -#define EN_CA_TRAINING (0) -#define EN_WRITE_LEVELING (0) -#define EN_READ_LEVELING (0) -#define EN_WDQ_LEVELING (0) - -#define ENPER_CS_TRAINING_FREQ (933) - -struct pll_div { - unsigned int mhz; - unsigned int refdiv; - unsigned int fbdiv; - unsigned int postdiv1; - unsigned int postdiv2; - unsigned int frac; - unsigned int freq; -}; +#define ENPER_CS_TRAINING_FREQ (666) +#define TDFI_LAT_THRESHOLD_FREQ (928) +#define PHY_DLL_BYPASS_FREQ (260) static const struct pll_div dpll_rates_table[] = { /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ - {.mhz = 933, .refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1}, + {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}, {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, @@ -78,128 +63,44 @@ static const struct pll_div dpll_rates_table[] = { struct rk3399_dram_status { uint32_t current_index; uint32_t index_freq[2]; + uint32_t boot_freq; uint32_t low_power_stat; struct timing_related_config timing_config; struct drv_odt_lp_config drv_odt_lp_cfg; }; -static struct rk3399_dram_status rk3399_dram_status; -static struct ddr_dts_config_timing dts_parameter = { - .available = 0 +struct rk3399_saved_status { + uint32_t freq; + uint32_t low_power_stat; + uint32_t odt; }; +static struct rk3399_dram_status rk3399_dram_status; +static struct rk3399_saved_status rk3399_suspend_status; +static uint32_t wrdqs_delay_val[2][2][4]; + static struct rk3399_sdram_default_config ddr3_default_config = { .bl = 8, .ap = 0, - .dramds = 40, - .dramodt = 120, .burst_ref_cnt = 1, .zqcsi = 0 }; -static struct drv_odt_lp_config ddr3_drv_odt_default_config = { - .ddr3_speed_bin = DDR3_DEFAULT, - .pd_idle = 0, - .sr_idle = 0, - .sr_mc_gate_idle = 0, - .srpd_lite_idle = 0, - .standby_idle = 0, - - .ddr3_dll_dis_freq = 300, - .phy_dll_dis_freq = 125, - .odt_dis_freq = 933, - - .dram_side_drv = 40, - .dram_side_dq_odt = 120, - .dram_side_ca_odt = 120, - - .phy_side_ca_drv = 40, - .phy_side_ck_cs_drv = 40, - .phy_side_dq_drv = 40, - .phy_side_odt = 240, -}; - static struct rk3399_sdram_default_config lpddr3_default_config = { .bl = 8, .ap = 0, - .dramds = 34, - .dramodt = 240, .burst_ref_cnt = 1, .zqcsi = 0 }; -static struct drv_odt_lp_config lpddr3_drv_odt_default_config = { - .ddr3_speed_bin = DDR3_DEFAULT, - .pd_idle = 0, - .sr_idle = 0, - .sr_mc_gate_idle = 0, - .srpd_lite_idle = 0, - .standby_idle = 0, - - .ddr3_dll_dis_freq = 300, - .phy_dll_dis_freq = 125, - .odt_dis_freq = 666, - - .dram_side_drv = 40, - .dram_side_dq_odt = 120, - .dram_side_ca_odt = 120, - - .phy_side_ca_drv = 40, - .phy_side_ck_cs_drv = 40, - .phy_side_dq_drv = 40, - .phy_side_odt = 240, -}; - static struct rk3399_sdram_default_config lpddr4_default_config = { .bl = 16, .ap = 0, - .dramds = 40, - .dramodt = 240, .caodt = 240, .burst_ref_cnt = 1, .zqcsi = 0 }; -static struct drv_odt_lp_config lpddr4_drv_odt_default_config = { - .ddr3_speed_bin = DDR3_DEFAULT, - .pd_idle = 0, - .sr_idle = 0, - .sr_mc_gate_idle = 0, - .srpd_lite_idle = 0, - .standby_idle = 0, - - .ddr3_dll_dis_freq = 300, - .phy_dll_dis_freq = 125, - .odt_dis_freq = 933, - - .dram_side_drv = 60, - .dram_side_dq_odt = 40, - .dram_side_ca_odt = 40, - - .phy_side_ca_drv = 40, - .phy_side_ck_cs_drv = 80, - .phy_side_dq_drv = 80, - .phy_side_odt = 60, -}; - -uint32_t dcf_code[] = { -#include "dcf_code.inc" -}; - -#define DCF_START_ADDR (SRAM_BASE + 0x1400) -#define DCF_PARAM_ADDR (SRAM_BASE + 0x1000) - -/* DCF_PAMET */ -#define PARAM_DRAM_FREQ (0) -#define PARAM_DPLL_CON0 (4) -#define PARAM_DPLL_CON1 (8) -#define PARAM_DPLL_CON2 (0xc) -#define PARAM_DPLL_CON3 (0x10) -#define PARAM_DPLL_CON4 (0x14) -#define PARAM_DPLL_CON5 (0x18) -/* equal to fn<<4 */ -#define PARAM_FREQ_SELECT (0x1c) - static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, uint8_t channel, uint8_t cs) { @@ -222,176 +123,79 @@ static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, return (cs_cap / die); } -static void drv_odt_lp_cfg_init(uint32_t dram_type, - struct ddr_dts_config_timing *dts_timing, +static void get_dram_drv_odt_val(uint32_t dram_type, struct drv_odt_lp_config *drv_config) { - if ((dts_timing) && (dts_timing->available)) { - drv_config->ddr3_speed_bin = dts_timing->ddr3_speed_bin; - drv_config->pd_idle = dts_timing->pd_idle; - drv_config->sr_idle = dts_timing->sr_idle; - drv_config->sr_mc_gate_idle = dts_timing->sr_mc_gate_idle; - drv_config->srpd_lite_idle = dts_timing->srpd_lite_idle; - drv_config->standby_idle = dts_timing->standby_idle; - drv_config->ddr3_dll_dis_freq = dts_timing->ddr3_dll_dis_freq; - drv_config->phy_dll_dis_freq = dts_timing->phy_dll_dis_freq; - } + uint32_t tmp; + uint32_t mr1_val, mr3_val, mr11_val; switch (dram_type) { case DDR3: - if ((dts_timing) && (dts_timing->available)) { - drv_config->odt_dis_freq = - dts_timing->ddr3_odt_dis_freq; - drv_config->dram_side_drv = dts_timing->ddr3_drv; - drv_config->dram_side_dq_odt = dts_timing->ddr3_odt; - drv_config->phy_side_ca_drv = - dts_timing->phy_ddr3_ca_drv; - drv_config->phy_side_ck_cs_drv = - dts_timing->phy_ddr3_ca_drv; - drv_config->phy_side_dq_drv = - dts_timing->phy_ddr3_dq_drv; - drv_config->phy_side_odt = dts_timing->phy_ddr3_odt; - } else { - memcpy(drv_config, &ddr3_drv_odt_default_config, - sizeof(struct drv_odt_lp_config)); - } + mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; + tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); + if (tmp) + drv_config->dram_side_drv = 34; + else + drv_config->dram_side_drv = 40; + tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | + ((mr1_val >> 7) & 1); + if (tmp == 0) + drv_config->dram_side_dq_odt = 0; + else if (tmp == 1) + drv_config->dram_side_dq_odt = 60; + else if (tmp == 3) + drv_config->dram_side_dq_odt = 40; + else + drv_config->dram_side_dq_odt = 120; break; case LPDDR3: - if ((dts_timing) && (dts_timing->available)) { - drv_config->odt_dis_freq = - dts_timing->lpddr3_odt_dis_freq; - drv_config->dram_side_drv = dts_timing->lpddr3_drv; - drv_config->dram_side_dq_odt = dts_timing->lpddr3_odt; - drv_config->phy_side_ca_drv = - dts_timing->phy_lpddr3_ca_drv; - drv_config->phy_side_ck_cs_drv = - dts_timing->phy_lpddr3_ca_drv; - drv_config->phy_side_dq_drv = - dts_timing->phy_lpddr3_dq_drv; - drv_config->phy_side_odt = dts_timing->phy_lpddr3_odt; - - } else { - memcpy(drv_config, &lpddr3_drv_odt_default_config, - sizeof(struct drv_odt_lp_config)); - } + mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; + mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; + if (mr3_val == 0xb) + drv_config->dram_side_drv = 3448; + else if (mr3_val == 0xa) + drv_config->dram_side_drv = 4048; + else if (mr3_val == 0x9) + drv_config->dram_side_drv = 3440; + else if (mr3_val == 0x4) + drv_config->dram_side_drv = 60; + else if (mr3_val == 0x3) + drv_config->dram_side_drv = 48; + else if (mr3_val == 0x2) + drv_config->dram_side_drv = 40; + else + drv_config->dram_side_drv = 34; + + if (mr11_val == 1) + drv_config->dram_side_dq_odt = 60; + else if (mr11_val == 2) + drv_config->dram_side_dq_odt = 120; + else if (mr11_val == 0) + drv_config->dram_side_dq_odt = 0; + else + drv_config->dram_side_dq_odt = 240; break; case LPDDR4: default: - if ((dts_timing) && (dts_timing->available)) { - drv_config->odt_dis_freq = - dts_timing->lpddr4_odt_dis_freq; - drv_config->dram_side_drv = dts_timing->lpddr4_drv; - drv_config->dram_side_dq_odt = - dts_timing->lpddr4_dq_odt; - drv_config->dram_side_ca_odt = - dts_timing->lpddr4_ca_odt; - drv_config->phy_side_ca_drv = - dts_timing->phy_lpddr4_ca_drv; - drv_config->phy_side_ck_cs_drv = - dts_timing->phy_lpddr4_ck_cs_drv; - drv_config->phy_side_dq_drv = - dts_timing->phy_lpddr4_dq_drv; - drv_config->phy_side_odt = dts_timing->phy_lpddr4_odt; - } else { - memcpy(drv_config, &lpddr4_drv_odt_default_config, - sizeof(struct drv_odt_lp_config)); - } - break; - } - - switch (drv_config->phy_side_ca_drv) { - case 240: - drv_config->phy_side_ca_drv = PHY_DRV_ODT_240; - break; - case 120: - drv_config->phy_side_ca_drv = PHY_DRV_ODT_120; - break; - case 80: - drv_config->phy_side_ca_drv = PHY_DRV_ODT_80; - break; - case 60: - drv_config->phy_side_ca_drv = PHY_DRV_ODT_60; - break; - case 48: - drv_config->phy_side_ca_drv = PHY_DRV_ODT_48; - break; - case 40: - drv_config->phy_side_ca_drv = PHY_DRV_ODT_40; - break; - default: - drv_config->phy_side_ca_drv = PHY_DRV_ODT_34_3; - break; - }; + mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; + mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; - switch (drv_config->phy_side_ck_cs_drv) { - case 240: - drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_240; - break; - case 120: - drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_120; - break; - case 80: - drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_80; - break; - case 60: - drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_60; - break; - case 48: - drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_48; - break; - case 40: - drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_40; - break; - default: - drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_34_3; - break; - } + if ((mr3_val == 0) || (mr3_val == 7)) + drv_config->dram_side_drv = 40; + else + drv_config->dram_side_drv = 240 / mr3_val; - switch (drv_config->phy_side_dq_drv) { - case 240: - drv_config->phy_side_dq_drv = PHY_DRV_ODT_240; - break; - case 120: - drv_config->phy_side_dq_drv = PHY_DRV_ODT_120; - break; - case 80: - drv_config->phy_side_dq_drv = PHY_DRV_ODT_80; - break; - case 60: - drv_config->phy_side_dq_drv = PHY_DRV_ODT_60; - break; - case 48: - drv_config->phy_side_dq_drv = PHY_DRV_ODT_48; - break; - case 40: - drv_config->phy_side_dq_drv = PHY_DRV_ODT_40; - break; - default: - drv_config->phy_side_dq_drv = PHY_DRV_ODT_34_3; - break; - } + tmp = mr11_val & 0x7; + if ((tmp == 7) || (tmp == 0)) + drv_config->dram_side_dq_odt = 0; + else + drv_config->dram_side_dq_odt = 240 / tmp; - switch (drv_config->phy_side_odt) { - case 240: - drv_config->phy_side_odt = PHY_DRV_ODT_240; - break; - case 120: - drv_config->phy_side_odt = PHY_DRV_ODT_120; - break; - case 80: - drv_config->phy_side_odt = PHY_DRV_ODT_80; - break; - case 60: - drv_config->phy_side_odt = PHY_DRV_ODT_60; - break; - case 48: - drv_config->phy_side_odt = PHY_DRV_ODT_48; - break; - case 40: - drv_config->phy_side_odt = PHY_DRV_ODT_40; - break; - default: - drv_config->phy_side_odt = PHY_DRV_ODT_34_3; + tmp = (mr11_val >> 4) & 0x7; + if ((tmp == 7) || (tmp == 0)) + drv_config->dram_side_ca_odt = 0; + else + drv_config->dram_side_ca_odt = 240 / tmp; break; } } @@ -403,8 +207,7 @@ static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, uint32_t i, j; for (i = 0; i < sdram_params->num_channels; i++) { - ptiming_config->dram_info[i].speed_rate = - drv_config->ddr3_speed_bin; + ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; for (j = 0; j < sdram_params->ch[i].rank; j++) { ptiming_config->dram_info[i].per_die_capability[j] = @@ -432,6 +235,7 @@ static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, ptiming_config->dramds = drv_config->dram_side_drv; ptiming_config->dramodt = drv_config->dram_side_dq_odt; ptiming_config->caodt = drv_config->dram_side_ca_odt; + ptiming_config->odt = (mmio_read_32(PHY_REG(0, 5)) >> 16) & 0x1; } struct lat_adj_pair { @@ -928,7 +732,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); - if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { + if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { if (tmp1 == 0) tmp = 0; else if (tmp1 < 5) @@ -941,7 +745,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ - if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && + if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && (pdram_timing->cl >= 5)) tmp = pdram_timing->cl - 5; else @@ -1178,7 +982,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); - if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { + if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { if (tmp1 == 0) tmp = 0; else if (tmp1 < 5) @@ -1192,7 +996,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24); /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ - if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && + if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && (pdram_timing->cl >= 5)) tmp = pdram_timing->cl - 5; else @@ -1201,6 +1005,33 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config } } +static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) +{ + uint32_t i, tmp; + + if (nmhz <= PHY_DLL_BYPASS_FREQ) + tmp = 0; + else + tmp = 1; + + for (i = 0; i < ch_cnt; i++) { + mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); + mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); + mmio_clrsetbits_32(CTL_REG(i, 70), 1 << 8, 1 << 8); + } +} + +static void gen_rk3399_disable_training(uint32_t ch_cnt) +{ + uint32_t i; + + for (i = 0; i < ch_cnt; i++) { + mmio_clrbits_32(CTL_REG(i, 305), 1 << 16); + mmio_clrbits_32(CTL_REG(i, 71), 1); + mmio_clrbits_32(CTL_REG(i, 70), 1 << 8); + } +} + static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, struct dram_timing_t *pdram_timing, uint32_t fn) @@ -1209,35 +1040,6 @@ static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, gen_rk3399_ctl_params_f0(timing_config, pdram_timing); else gen_rk3399_ctl_params_f1(timing_config, pdram_timing); - -#if CTL_TRAINING - uint32_t i, tmp0, tmp1; - - tmp0 = tmp1 = 0; -#if EN_READ_GATE_TRAINING - tmp1 = 1; -#endif - -#if EN_CA_TRAINING - tmp0 |= (1 << 8); -#endif - -#if EN_WRITE_LEVELING - tmp0 |= (1 << 16); -#endif - -#if EN_READ_LEVELING - tmp0 |= (1 << 24); -#endif - for (i = 0; i < timing_config->ch_cnt; i++) { - if (tmp0 | tmp1) - mmio_setbits_32(CTL_REG(i, 305), 1 << 16); - if (tmp0) - mmio_setbits_32(CTL_REG(i, 70), tmp0); - if (tmp1) - mmio_setbits_32(CTL_REG(i, 71), tmp1); - } -#endif } static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, @@ -1381,7 +1183,8 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16, pdram_timing->mr[2] << 16); /* PI_156 PI_TFC_F0:RW:0:10 */ - mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, pdram_timing->trfc); + mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, + pdram_timing->tfc_long); /* PI_158 PI_TWR_F0:RW:24:6 */ mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, pdram_timing->twr << 24); @@ -1452,7 +1255,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, - pdram_timing->cl * 2); + (pdram_timing->cl * 2) << 8); /* PI_47 PI_TREF_F1:RW:16:16 */ mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, pdram_timing->trefi << 16); @@ -1561,7 +1364,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); /* PI_156 PI_TFC_F1:RW:16:10 */ mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, - pdram_timing->trfc << 16); + pdram_timing->tfc_long << 16); /* PI_162 PI_TWR_F1:RW:8:6 */ mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, pdram_timing->twr << 8); @@ -1605,32 +1408,6 @@ static void gen_rk3399_pi_params(struct timing_related_config *timing_config, gen_rk3399_pi_params_f0(timing_config, pdram_timing); else gen_rk3399_pi_params_f1(timing_config, pdram_timing); - -#if PI_TRAINING - uint32_t i; - - for (i = 0; i < timing_config->ch_cnt; i++) { -#if EN_READ_GATE_TRAINING - mmio_clrsetbits_32(PI_REG(i, 80), 3 << 24, 2 << 24); -#endif - -#if EN_CA_TRAINING - mmio_clrsetbits_32(PI_REG(i, 100), 3 << 8, 2 << 8); -#endif - -#if EN_WRITE_LEVELING - mmio_clrsetbits_32(PI_REG(i, 60), 3 << 8, 2 << 8); -#endif - -#if EN_READ_LEVELING - mmio_clrsetbits_32(PI_REG(i, 80), 3 << 16, 2 << 16); -#endif - -#if EN_WDQ_LEVELING - mmio_clrsetbits_32(PI_REG(i, 124), 3 << 16, 2 << 16); -#endif - } -#endif } static void gen_rk3399_set_odt(uint32_t odt_en) @@ -1652,57 +1429,92 @@ static void gen_rk3399_set_odt(uint32_t odt_en) } } -static void gen_rk3399_set_ds_odt(struct timing_related_config *timing_config, - struct drv_odt_lp_config *drv_config) +static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, + uint32_t index, uint32_t dram_type) { - uint32_t i, drv_odt_val; + uint32_t sw_master_mode = 0; + uint32_t rddqs_gate_delay, rddqs_latency, total_delay; + uint32_t i; - for (i = 0; i < timing_config->ch_cnt; i++) { - if (timing_config->dram_type == LPDDR4) - drv_odt_val = drv_config->phy_side_odt | - (PHY_DRV_ODT_Hi_Z << 4) | - (drv_config->phy_side_dq_drv << 8) | - (drv_config->phy_side_dq_drv << 12); - else if (timing_config->dram_type == LPDDR3) - drv_odt_val = PHY_DRV_ODT_Hi_Z | - (drv_config->phy_side_odt << 4) | - (drv_config->phy_side_dq_drv << 8) | - (drv_config->phy_side_dq_drv << 12); - else - drv_odt_val = drv_config->phy_side_odt | - (drv_config->phy_side_odt << 4) | - (drv_config->phy_side_dq_drv << 8) | - (drv_config->phy_side_dq_drv << 12); - - /* DQ drv odt set */ - mmio_clrsetbits_32(PHY_REG(i, 6), 0xffffff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 134), 0xffffff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 262), 0xffffff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 390), 0xffffff, drv_odt_val); - /* DQS drv odt set */ - mmio_clrsetbits_32(PHY_REG(i, 7), 0xffffff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 135), 0xffffff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 263), 0xffffff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 391), 0xffffff, drv_odt_val); - - gen_rk3399_set_odt(timing_config->odt); - - /* CA drv set */ - drv_odt_val = drv_config->phy_side_ca_drv | - (drv_config->phy_side_ca_drv << 4); - mmio_clrsetbits_32(PHY_REG(i, 544), 0xff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 672), 0xff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 800), 0xff, drv_odt_val); - - mmio_clrsetbits_32(PHY_REG(i, 928), 0xff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 937), 0xff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 935), 0xff, drv_odt_val); - - drv_odt_val = drv_config->phy_side_ck_cs_drv | - (drv_config->phy_side_ck_cs_drv << 4); - mmio_clrsetbits_32(PHY_REG(i, 929), 0xff, drv_odt_val); - mmio_clrsetbits_32(PHY_REG(i, 939), 0xff, drv_odt_val); + if (dram_type == DDR3) + total_delay = PI_PAD_DELAY_PS_VALUE; + else if (dram_type == LPDDR3) + total_delay = PI_PAD_DELAY_PS_VALUE + 2500; + else + total_delay = PI_PAD_DELAY_PS_VALUE + 1500; + /* total_delay + 0.55tck */ + total_delay += (55 * 10000)/mhz; + rddqs_latency = total_delay * mhz / 1000000; + total_delay -= rddqs_latency * 1000000 / mhz; + rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000; + if (mhz <= PHY_DLL_BYPASS_FREQ) { + sw_master_mode = 0xc; + mmio_setbits_32(PHY_REG(ch, 514), 1); + mmio_setbits_32(PHY_REG(ch, 642), 1); + mmio_setbits_32(PHY_REG(ch, 770), 1); + + /* setting bypass mode slave delay */ + for (i = 0; i < 4; i++) { + /* wr dq delay = -180deg + (0x60 / 4) * 20ps */ + mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, + 0x4a0 << 8); + /* rd dqs/dq delay = (0x60 / 4) * 20ps */ + mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, + 0xa0); + /* rd rddqs_gate delay */ + mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, + rddqs_gate_delay); + mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, + rddqs_latency); + } + for (i = 0; i < 3; i++) + /* adr delay */ + mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), + 0x7ff << 16, 0x80 << 16); + + if ((mmio_read_32(PHY_REG(ch, 86)) & 0xc00) == 0) { + /* + * old status is normal mode, + * and saving the wrdqs slave delay + */ + for (i = 0; i < 4; i++) { + /* save and clear wr dqs slave delay */ + wrdqs_delay_val[ch][index][i] = 0x3ff & + (mmio_read_32(PHY_REG(ch, 63 + i * 128)) + >> 16); + mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), + 0x03ff << 16, 0 << 16); + /* + * in normal mode the cmd may delay 1cycle by + * wrlvl and in bypass mode making dqs also + * delay 1cycle. + */ + mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), + 0x07 << 8, 0x1 << 8); + } + } + } else if (mmio_read_32(PHY_REG(ch, 86)) & 0xc00) { + /* old status is bypass mode and restore wrlvl resume */ + for (i = 0; i < 4; i++) { + mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), + 0x03ff << 16, + (wrdqs_delay_val[ch][index][i] & + 0x3ff) << 16); + /* resume phy_write_path_lat_add */ + mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); + } } + + /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ + mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); + mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); + mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); + mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); + + /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ + mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); + mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); + mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); } static void gen_rk3399_phy_params(struct timing_related_config *timing_config, @@ -1745,15 +1557,7 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config, /* DENALI_PHY_911 13bits offset_0 */ /* PHY_LP4_BOOT_PLL_CTRL */ /* DENALI_PHY_919 13bits offset_0 */ - if (pdram_timing->mhz <= 150) - tmp = 3; - else if (pdram_timing->mhz <= 300) - tmp = 2; - else if (pdram_timing->mhz <= 600) - tmp = 1; - else - tmp = 0; - tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1); + tmp = (1 << 12) | (2 << 7) | (1 << 1); mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); @@ -1761,15 +1565,7 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config, /* DENALI_PHY_911 13bits offset_16 */ /* PHY_LP4_BOOT_PLL_CTRL_CA */ /* DENALI_PHY_919 13bits offset_16 */ - if (pdram_timing->mhz <= 150) - tmp = 3; - else if (pdram_timing->mhz <= 300) - tmp = 2; - else if (pdram_timing->mhz <= 600) - tmp = 1; - else - tmp = 0; - tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1); + tmp = (2 << 7) | (1 << 5) | (1 << 1); mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); @@ -1791,7 +1587,6 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config, break; } mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); - mmio_setbits_32(PHY_REG(i, 927), (1 << 22)); if (timing_config->dram_type == DDR3) { mem_delay_ps = 0; @@ -1812,12 +1607,6 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config, gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); gate_delay_frac_ps = gate_delay_ps % 1000; tmp = gate_delay_frac_ps * 0x200 / 1000; - /* PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY */ - /* DENALI_PHY_2/130/258/386 10bits offset_0 */ - mmio_clrsetbits_32(PHY_REG(i, 2), 0x2ff, tmp); - mmio_clrsetbits_32(PHY_REG(i, 130), 0x2ff, tmp); - mmio_clrsetbits_32(PHY_REG(i, 258), 0x2ff, tmp); - mmio_clrsetbits_32(PHY_REG(i, 386), 0x2ff, tmp); /* PHY_RDDQS_GATE_SLAVE_DELAY */ /* DENALI_PHY_77/205/333/461 10bits offset_16 */ mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); @@ -1832,12 +1621,6 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config, mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); - /* PHY_RDDQS_LATENCY_ADJUST */ - /* DENALI_PHY_78/206/334/462 4bits offset_0 */ - mmio_clrsetbits_32(PHY_REG(i, 78), 0xf, tmp); - mmio_clrsetbits_32(PHY_REG(i, 206), 0xf, tmp); - mmio_clrsetbits_32(PHY_REG(i, 334), 0xf, tmp); - mmio_clrsetbits_32(PHY_REG(i, 462), 0xf, tmp); /* PHY_GTLVL_LAT_ADJ_START */ /* DENALI_PHY_80/208/336/464 4bits offset_16 */ tmp = delay_frac_ps / 1000; @@ -1922,6 +1705,8 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config, mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); } + gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn, + timing_config->dram_type); } } @@ -1944,22 +1729,6 @@ static int to_get_clk_index(unsigned int mhz) return i; } -uint32_t rkclk_prepare_pll_timing(unsigned int mhz) -{ - unsigned int refdiv, postdiv1, fbdiv, postdiv2; - int index; - - index = to_get_clk_index(mhz); - refdiv = dpll_rates_table[index].refdiv; - fbdiv = dpll_rates_table[index].fbdiv; - postdiv1 = dpll_rates_table[index].postdiv1; - postdiv2 = dpll_rates_table[index].postdiv2; - mmio_write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(fbdiv)); - mmio_write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON1, - POSTDIV2(postdiv2) | POSTDIV1(postdiv1) | REFDIV(refdiv)); - return (24 * fbdiv) / refdiv / postdiv1 / postdiv2; -} - uint32_t ddr_get_rate(void) { uint32_t refdiv, postdiv1, fbdiv, postdiv2; @@ -2051,90 +1820,21 @@ void resume_low_power(uint32_t low_power) } } -static void wait_dcf_done(void) -{ - while ((mmio_read_32(DCF_BASE + DCF_DCF_ISR) & (DCF_DONE)) == 0) - continue; -} - -void clr_dcf_irq(void) +static void dram_low_power_config(void) { - /* clear dcf irq status */ - mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); -} - -static void enable_dcf(uint32_t dcf_addr) -{ - /* config DCF start addr */ - mmio_write_32(DCF_BASE + DCF_DCF_ADDR, dcf_addr); - /* wait dcf done */ - while (mmio_read_32(DCF_BASE + DCF_DCF_CTRL) & 1) - continue; - /* clear dcf irq status */ - mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); - /* DCF start */ - mmio_setbits_32(DCF_BASE + DCF_DCF_CTRL, DCF_START); -} - -void dcf_code_init(void) -{ - memcpy((void *)DCF_START_ADDR, (void *)dcf_code, sizeof(dcf_code)); - /* set dcf master secure */ - mmio_write_32(SGRF_BASE + 0xe01c, ((0x3 << 0) << 16) | (0 << 0)); - mmio_write_32(DCF_BASE + DCF_DCF_TOSET, 0x80000000); -} - -static void dcf_start(uint32_t freq, uint32_t index) -{ - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - (0x1 << (1 + 16)) | (1 << 1)); - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(11), - (0x1 << (0 + 16)) | (1 << 0)); - mmio_write_32(DCF_PARAM_ADDR + PARAM_FREQ_SELECT, index << 4); - - mmio_write_32(DCF_PARAM_ADDR + PARAM_DRAM_FREQ, freq); - - rkclk_prepare_pll_timing(freq); - udelay(10); - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - (0x1 << (1 + 16)) | (0 << 1)); - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(11), - (0x1 << (0 + 16)) | (0 << 0)); - udelay(10); - enable_dcf(DCF_START_ADDR); -} - -static void dram_low_power_config(struct drv_odt_lp_config *lp_config) -{ - uint32_t tmp, tmp1, i; + uint32_t tmp, i; uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; - uint32_t *low_power = &rk3399_dram_status.low_power_stat; - - if (dram_type == LPDDR4) - tmp = (lp_config->srpd_lite_idle << 16) | - lp_config->pd_idle; - else - tmp = lp_config->pd_idle; if (dram_type == DDR3) - tmp1 = (2 << 16) | (0x7 << 8) | 7; + tmp = (2 << 16) | (0x7 << 8); else - tmp1 = (3 << 16) | (0x7 << 8) | 7; + tmp = (3 << 16) | (0x7 << 8); - *low_power = 0; - - for (i = 0; i < ch_cnt; i++) { - mmio_write_32(CTL_REG(i, 102), tmp); - mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, - (lp_config->sr_mc_gate_idle << 8) | - lp_config->sr_idle); - mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp1); - *low_power |= (7 << (8 * i)); - } + for (i = 0; i < ch_cnt; i++) + mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); /* standby idle */ - mmio_write_32(CIC_BASE + CIC_IDLE_TH, lp_config->standby_idle); mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); if (ch_cnt == 2) { @@ -2142,36 +1842,22 @@ static void dram_low_power_config(struct drv_odt_lp_config *lp_config) (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); - if (lp_config->standby_idle) { - tmp = 0x002a002a; - *low_power |= (1 << 11); - } else - tmp = 0; - mmio_write_32(CIC_BASE + CIC_CTRL1, tmp); + mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); } mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); - if (lp_config->standby_idle) { - tmp = 0x00150015; - *low_power |= (1 << 3); - } else - tmp = 0; - mmio_write_32(CIC_BASE + CIC_CTRL1, tmp); + mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); } - -static void dram_related_init(struct ddr_dts_config_timing *dts_timing) +void dram_dfs_init(void) { - uint32_t trefi0, trefi1; - uint32_t i; - - dcf_code_init(); + uint32_t trefi0, trefi1, boot_freq; /* get sdram config for os reg */ - drv_odt_lp_cfg_init(sdram_config.dramtype, dts_timing, - &rk3399_dram_status.drv_odt_lp_cfg); + get_dram_drv_odt_val(sdram_config.dramtype, + &rk3399_dram_status.drv_odt_lp_cfg); sdram_timing_cfg_init(&rk3399_dram_status.timing_config, &sdram_config, &rk3399_dram_status.drv_odt_lp_cfg); @@ -2187,30 +1873,106 @@ static void dram_related_init(struct ddr_dts_config_timing *dts_timing) rk3399_dram_status.index_freq[0] /= 2; rk3399_dram_status.index_freq[1] /= 2; } - rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) - & 0x1] = 0; + boot_freq = + rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; + boot_freq = dpll_rates_table[to_get_clk_index(boot_freq)].mhz; + rk3399_dram_status.boot_freq = boot_freq; + rk3399_dram_status.index_freq[rk3399_dram_status.current_index] = + boot_freq; + rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) & + 0x1] = 0; + rk3399_dram_status.low_power_stat = 0; + /* + * following register decide if NOC stall the access request + * or return error when NOC being idled. when doing ddr frequency + * scaling in M0 or DCF, we need to make sure noc stall the access + * request, if return error cpu may data abort when ddr frequency + * changing. it don't need to set this register every times, + * so we init this register in function dram_dfs_init(). + */ + mmio_write_32(GRF_BASE + GRF_SOC_CON(0), 0xffffffff); + mmio_write_32(GRF_BASE + GRF_SOC_CON(1), 0xffffffff); + mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 0xffffffff); + mmio_write_32(GRF_BASE + GRF_SOC_CON(3), 0xffffffff); + mmio_write_32(GRF_BASE + GRF_SOC_CON(4), 0x70007000); - /* disable all training by ctl and pi */ - for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { - mmio_clrbits_32(CTL_REG(i, 70), (1 << 24) | - (1 << 16) | (1 << 8) | 1); - mmio_clrbits_32(CTL_REG(i, 71), 1); + /* Disable multicast */ + mmio_clrbits_32(PHY_REG(0, 896), 1); + mmio_clrbits_32(PHY_REG(1, 896), 1); + + dram_low_power_config(); +} + +/* + * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle + * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle + * arg2: bit0: if odt en + */ +uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) +{ + struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; + uint32_t *low_power = &rk3399_dram_status.low_power_stat; + uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; + + dram_type = rk3399_dram_status.timing_config.dram_type; + ch_count = rk3399_dram_status.timing_config.ch_cnt; + + lp_cfg->sr_idle = arg0 & 0xff; + lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; + lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; + lp_cfg->pd_idle = arg1 & 0xfff; + lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; + + rk3399_dram_status.timing_config.odt = arg2 & 0x1; + + exit_low_power(); + + *low_power = 0; - mmio_clrbits_32(PI_REG(i, 60), 0x3 << 8); - mmio_clrbits_32(PI_REG(i, 80), (0x3 << 24) | (0x3 << 16)); - mmio_clrbits_32(PI_REG(i, 100), 0x3 << 8); - mmio_clrbits_32(PI_REG(i, 124), 0x3 << 16); + /* pd_idle en */ + if (lp_cfg->pd_idle) + *low_power |= ((1 << 0) | (1 << 8)); + /* sr_idle en srpd_lite_idle */ + if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) + *low_power |= ((1 << 1) | (1 << 9)); + /* sr_mc_gate_idle */ + if (lp_cfg->sr_mc_gate_idle) + *low_power |= ((1 << 2) | (1 << 10)); + /* standbyidle */ + if (lp_cfg->standby_idle) { + if (rk3399_dram_status.timing_config.ch_cnt == 2) + *low_power |= ((1 << 3) | (1 << 11)); + else + *low_power |= (1 << 3); } - /* init drv odt */ - if (rk3399_dram_status.index_freq[rk3399_dram_status.current_index] < - rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) - rk3399_dram_status.timing_config.odt = 0; - else - rk3399_dram_status.timing_config.odt = 1; - gen_rk3399_set_ds_odt(&rk3399_dram_status.timing_config, - &rk3399_dram_status.drv_odt_lp_cfg); - dram_low_power_config(&rk3399_dram_status.drv_odt_lp_cfg); + pd_tmp = arg1; + if (dram_type != LPDDR4) + pd_tmp = arg1 & 0xfff; + sr_tmp = arg0 & 0xffff; + for (i = 0; i < ch_count; i++) { + mmio_write_32(CTL_REG(i, 102), pd_tmp); + mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); + } + mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); + + return 0; +} + +static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) +{ + /* set PARAM to M0_FUNC_DRAM */ + mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_DRAM); + + mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(pll_div.fbdiv)); + mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON1, + POSTDIV2(pll_div.postdiv2) | POSTDIV1(pll_div.postdiv1) | + REFDIV(pll_div.refdiv)); + + mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz); + + mmio_write_32(M0_PARAM_ADDR + PARAM_FREQ_SELECT, ddr_index << 4); + dmbst(); } static uint32_t prepare_ddr_timing(uint32_t mhz) @@ -2220,20 +1982,15 @@ static uint32_t prepare_ddr_timing(uint32_t mhz) rk3399_dram_status.timing_config.freq = mhz; - if (mhz < rk3399_dram_status.drv_odt_lp_cfg.ddr3_dll_dis_freq) + if (mhz < 300) rk3399_dram_status.timing_config.dllbp = 1; else rk3399_dram_status.timing_config.dllbp = 0; - if (mhz < rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) { - rk3399_dram_status.timing_config.odt = 0; - } else { - rk3399_dram_status.timing_config.odt = 1; + + if (rk3399_dram_status.timing_config.odt == 1) gen_rk3399_set_odt(1); - } index = (rk3399_dram_status.current_index + 1) & 0x1; - if (rk3399_dram_status.index_freq[index] == mhz) - goto out; /* * checking if having available gate traiing timing for @@ -2249,8 +2006,6 @@ static uint32_t prepare_ddr_timing(uint32_t mhz) &dram_timing, index); rk3399_dram_status.index_freq[index] = mhz; - -out: return index; } @@ -2271,33 +2026,39 @@ void print_dram_status_info(void) uint32_t ddr_set_rate(uint32_t hz) { - uint32_t low_power, index; + uint32_t low_power, index, ddr_index; uint32_t mhz = hz / (1000 * 1000); if (mhz == rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) - goto out; + return mhz; index = to_get_clk_index(mhz); mhz = dpll_rates_table[index].mhz; - low_power = exit_low_power(); - index = prepare_ddr_timing(mhz); - if (index > 1) + ddr_index = prepare_ddr_timing(mhz); + gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt, + mhz); + if (ddr_index > 1) goto out; - dcf_start(mhz, index); - wait_dcf_done(); + /* + * Make sure the clock is enabled. The M0 clocks should be on all of the + * time during S0. + */ + m0_configure_ddr(dpll_rates_table[index], ddr_index); + m0_start(); + m0_wait_done(); + m0_stop(); + if (rk3399_dram_status.timing_config.odt == 0) gen_rk3399_set_odt(0); - rk3399_dram_status.current_index = index; - - if (mhz < dts_parameter.auto_pd_dis_freq) - low_power |= rk3399_dram_status.low_power_stat; - + rk3399_dram_status.current_index = ddr_index; + low_power = rk3399_dram_status.low_power_stat; resume_low_power(low_power); out: + gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt); return mhz; } @@ -2311,29 +2072,56 @@ uint32_t ddr_round_rate(uint32_t hz) return dpll_rates_table[index].mhz * 1000 * 1000; } -uint32_t dts_timing_receive(uint32_t timing, uint32_t index) +void ddr_prepare_for_sys_suspend(void) { - uint32_t *p = (uint32_t *) &dts_parameter; - static uint32_t receive_nums; - - if (index < (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) { - p[index] = (uint32_t)timing; - receive_nums++; - } else { - dts_parameter.available = 0; - return -1; - } + uint32_t mhz = + rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; - /* receive all parameter */ - if (receive_nums == (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) { - dts_parameter.available = 1; - receive_nums = 0; - } + /* + * If we're not currently at the boot (assumed highest) frequency, we + * need to change frequencies to configure out current index. + */ + rk3399_suspend_status.freq = mhz; + exit_low_power(); + rk3399_suspend_status.low_power_stat = + rk3399_dram_status.low_power_stat; + rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt; + rk3399_dram_status.low_power_stat = 0; + rk3399_dram_status.timing_config.odt = 1; + if (mhz != rk3399_dram_status.boot_freq) + ddr_set_rate(rk3399_dram_status.boot_freq * 1000 * 1000); - return index; + /* + * This will configure the other index to be the same frequency as the + * current one. We retrain both indices on resume, so both have to be + * setup for the same frequency. + */ + prepare_ddr_timing(rk3399_dram_status.boot_freq); } -void ddr_dfs_init(void) +void ddr_prepare_for_sys_resume(void) { - dram_related_init(&dts_parameter); + /* Disable multicast */ + mmio_clrbits_32(PHY_REG(0, 896), 1); + mmio_clrbits_32(PHY_REG(1, 896), 1); + + /* The suspend code changes the current index, so reset it now. */ + rk3399_dram_status.current_index = + (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; + rk3399_dram_status.low_power_stat = + rk3399_suspend_status.low_power_stat; + rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt; + + /* + * Set the saved frequency from suspend if it's different than the + * current frequency. + */ + if (rk3399_suspend_status.freq != + rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) { + ddr_set_rate(rk3399_suspend_status.freq * 1000 * 1000); + return; + } + + gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt); + resume_low_power(rk3399_dram_status.low_power_stat); } diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.h b/plat/rockchip/rk3399/drivers/dram/dfs.h index 1da09032..3204ae74 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.h +++ b/plat/rockchip/rk3399/drivers/dram/dfs.h @@ -48,65 +48,25 @@ struct rk3399_sdram_default_config { unsigned char zqcsi; }; -struct ddr_dts_config_timing { - unsigned int ddr3_speed_bin; - unsigned int pd_idle; - unsigned int sr_idle; - unsigned int sr_mc_gate_idle; - unsigned int srpd_lite_idle; - unsigned int standby_idle; - unsigned int auto_pd_dis_freq; - unsigned int ddr3_dll_dis_freq; - unsigned int phy_dll_dis_freq; - unsigned int ddr3_odt_dis_freq; - unsigned int ddr3_drv; - unsigned int ddr3_odt; - unsigned int phy_ddr3_ca_drv; - unsigned int phy_ddr3_dq_drv; - unsigned int phy_ddr3_odt; - unsigned int lpddr3_odt_dis_freq; - unsigned int lpddr3_drv; - unsigned int lpddr3_odt; - unsigned int phy_lpddr3_ca_drv; - unsigned int phy_lpddr3_dq_drv; - unsigned int phy_lpddr3_odt; - unsigned int lpddr4_odt_dis_freq; - unsigned int lpddr4_drv; - unsigned int lpddr4_dq_odt; - unsigned int lpddr4_ca_odt; - unsigned int phy_lpddr4_ca_drv; - unsigned int phy_lpddr4_ck_cs_drv; - unsigned int phy_lpddr4_dq_drv; - unsigned int phy_lpddr4_odt; - uint32_t available; -}; - struct drv_odt_lp_config { - uint32_t ddr3_speed_bin; uint32_t pd_idle; uint32_t sr_idle; uint32_t sr_mc_gate_idle; uint32_t srpd_lite_idle; uint32_t standby_idle; - - uint32_t ddr3_dll_dis_freq;/* for ddr3 only */ - uint32_t phy_dll_dis_freq; - uint32_t odt_dis_freq; + uint32_t odt_en; uint32_t dram_side_drv; uint32_t dram_side_dq_odt; uint32_t dram_side_ca_odt; - - uint32_t phy_side_ca_drv; - uint32_t phy_side_ck_cs_drv; - uint32_t phy_side_dq_drv; - uint32_t phy_side_odt; }; -void ddr_dfs_init(void); uint32_t ddr_set_rate(uint32_t hz); uint32_t ddr_round_rate(uint32_t hz); uint32_t ddr_get_rate(void); -void clr_dcf_irq(void); -uint32_t dts_timing_receive(uint32_t timing, uint32_t index); +uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2); +void dram_dfs_init(void); +void ddr_prepare_for_sys_suspend(void); +void ddr_prepare_for_sys_resume(void); + #endif diff --git a/plat/rockchip/rk3399/drivers/dram/dram.c b/plat/rockchip/rk3399/drivers/dram/dram.c index 5f6f0fc3..1dfb3e5a 100644 --- a/plat/rockchip/rk3399/drivers/dram/dram.c +++ b/plat/rockchip/rk3399/drivers/dram/dram.c @@ -30,6 +30,7 @@ #include <dram.h> #include <plat_private.h> +#include <secure.h> #include <soc.h> #include <rk3399_def.h> diff --git a/plat/rockchip/rk3399/drivers/dram/dram.h b/plat/rockchip/rk3399/drivers/dram/dram.h index 44dfbbdc..571d51af 100644 --- a/plat/rockchip/rk3399/drivers/dram/dram.h +++ b/plat/rockchip/rk3399/drivers/dram/dram.h @@ -30,111 +30,11 @@ #ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__ #define __SOC_ROCKCHIP_RK3399_DRAM_H__ + +#include <dram_regs.h> #include <plat_private.h> #include <stdint.h> -#define CTL_BASE(ch) (0xffa80000 + (ch) * 0x8000) -#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) - -#define PI_OFFSET 0x800 -#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) -#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) - -#define PHY_OFFSET 0x2000 -#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET) -#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) - -#define MSCH_BASE(ch) (0xffa84000 + (ch) * 0x8000) -#define MSCH_ID_COREID 0x0 -#define MSCH_ID_REVISIONID 0x4 -#define MSCH_DEVICECONF 0x8 -#define MSCH_DEVICESIZE 0xc -#define MSCH_DDRTIMINGA0 0x10 -#define MSCH_DDRTIMINGB0 0x14 -#define MSCH_DDRTIMINGC0 0x18 -#define MSCH_DEVTODEV0 0x1c -#define MSCH_DDRMODE 0x110 -#define MSCH_AGINGX0 0x1000 - -#define CIC_CTRL0 0x0 -#define CIC_CTRL1 0x4 -#define CIC_IDLE_TH 0x8 -#define CIC_CG_WAIT_TH 0xc -#define CIC_STATUS0 0x10 -#define CIC_STATUS1 0x14 -#define CIC_CTRL2 0x18 -#define CIC_CTRL3 0x1c -#define CIC_CTRL4 0x20 - -/* DENALI_CTL_00 */ -#define START 1 - -/* DENALI_CTL_68 */ -#define PWRUP_SREFRESH_EXIT (1 << 16) - -/* DENALI_CTL_274 */ -#define MEM_RST_VALID 1 - -#define PHY_DRV_ODT_Hi_Z 0x0 -#define PHY_DRV_ODT_240 0x1 -#define PHY_DRV_ODT_120 0x8 -#define PHY_DRV_ODT_80 0x9 -#define PHY_DRV_ODT_60 0xc -#define PHY_DRV_ODT_48 0xd -#define PHY_DRV_ODT_40 0xe -#define PHY_DRV_ODT_34_3 0xf - -/* - * sys_reg bitfield struct - * [31] row_3_4_ch1 - * [30] row_3_4_ch0 - * [29:28] chinfo - * [27] rank_ch1 - * [26:25] col_ch1 - * [24] bk_ch1 - * [23:22] cs0_row_ch1 - * [21:20] cs1_row_ch1 - * [19:18] bw_ch1 - * [17:16] dbw_ch1; - * [15:13] ddrtype - * [12] channelnum - * [11] rank_ch0 - * [10:9] col_ch0 - * [8] bk_ch0 - * [7:6] cs0_row_ch0 - * [5:4] cs1_row_ch0 - * [3:2] bw_ch0 - * [1:0] dbw_ch0 - */ -#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) -#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) -#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) -#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) -#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) -#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) -#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) -#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) -#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) -#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) -#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) -#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3)) -#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16)) -#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1)) -#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16)) -#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3)) -#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16)) -#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3)) -#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16)) -#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3)) -#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16)) -#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3)) -#define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \ - (0x1f<<(10+16))|((n)<<10)) - -#define CTL_REG_NUM 332 -#define PHY_REG_NUM 959 -#define PI_REG_NUM 200 - enum { DDR3 = 3, LPDDR2 = 5, @@ -259,6 +159,7 @@ struct rk3399_sdram_params { struct rk3399_ddr_pctl_regs pctl_regs; struct rk3399_ddr_pi_regs pi_regs; struct rk3399_ddr_publ_regs phy_regs; + uint32_t rx_cal_dqs[2][4]; }; extern __sramdata struct rk3399_sdram_params sdram_config; diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c index fbf1d397..6288de43 100644 --- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c +++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,6 +31,7 @@ #include <string.h> #include <stdint.h> #include <dram.h> +#include <utils.h> #include "dram_spec_timing.h" static const uint8_t ddr3_cl_cwl[][7] = { @@ -228,7 +229,7 @@ static void ddr3_get_parameter(struct timing_related_config *timing_config, uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); uint32_t tmp; - memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); + zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); pdram_timing->mhz = nmhz; pdram_timing->al = 0; pdram_timing->bl = timing_config->bl; @@ -266,21 +267,24 @@ static void ddr3_get_parameter(struct timing_related_config *timing_config, break; } - switch (timing_config->dramodt) { - case 60: - pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; - break; - case 40: - pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; - break; - case 120: - pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; - break; - case 0: - default: + if (timing_config->odt) + switch (timing_config->dramodt) { + case 60: + pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; + break; + case 40: + pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; + break; + case 120: + pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; + break; + case 0: + default: + pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; + break; + } + else pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; - break; - } pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); pdram_timing->mr[3] = 0; @@ -441,7 +445,7 @@ static void lpddr2_get_parameter(struct timing_related_config *timing_config, uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; - memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); + zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); pdram_timing->mhz = nmhz; pdram_timing->al = 0; pdram_timing->bl = timing_config->bl; @@ -663,6 +667,9 @@ static void lpddr2_get_parameter(struct timing_related_config *timing_config, #define LPDDR3_TADR (20) /* ns */ #define LPDDR3_TMRZ (3) /* ns */ +/* FSP */ +#define LPDDR3_TFC_LONG (250) /* ns */ + /* * Description: depend on input parameter "timing_config", * and calculate all lpddr3 @@ -678,7 +685,7 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config, uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; - memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); + zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); pdram_timing->mhz = nmhz; pdram_timing->al = 0; pdram_timing->bl = timing_config->bl; @@ -750,18 +757,21 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config, break; } pdram_timing->mr[0] = 0; - switch (timing_config->dramodt) { - case 60: - pdram_timing->mr11 = LPDDR3_ODT_60; - break; - case 120: - pdram_timing->mr11 = LPDDR3_ODT_120; - break; - case 240: - default: - pdram_timing->mr11 = LPDDR3_ODT_240; - break; - } + if (timing_config->odt) + switch (timing_config->dramodt) { + case 60: + pdram_timing->mr11 = LPDDR3_ODT_60; + break; + case 120: + pdram_timing->mr11 = LPDDR3_ODT_120; + break; + case 240: + default: + pdram_timing->mr11 = LPDDR3_ODT_240; + break; + } + else + pdram_timing->mr11 = LPDDR3_ODT_DIS; pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000; pdram_timing->tinit2 = LPDDR3_TINIT2; @@ -873,6 +883,9 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config, pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000; pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000; pdram_timing->tcacd = pdram_timing->tadr + 2; + + /* FSP */ + pdram_timing->tfc_long = (LPDDR3_TFC_LONG * nmhz + 999) / 1000; } #define LPDDR4_TINIT1 (200000) /* 200us */ @@ -968,7 +981,7 @@ static void lpddr4_get_parameter(struct timing_related_config *timing_config, uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp; - memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); + zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); pdram_timing->mhz = nmhz; pdram_timing->al = 0; pdram_timing->bl = timing_config->bl; @@ -1112,47 +1125,52 @@ static void lpddr4_get_parameter(struct timing_related_config *timing_config, break; } pdram_timing->mr[0] = 0; - switch (timing_config->dramodt) { - case 240: - tmp = LPDDR4_DQODT_240; - break; - case 120: - tmp = LPDDR4_DQODT_120; - break; - case 80: - tmp = LPDDR4_DQODT_80; - break; - case 60: - tmp = LPDDR4_DQODT_60; - break; - case 48: - tmp = LPDDR4_DQODT_48; - break; - case 40: - default: - tmp = LPDDR4_DQODT_40; - break; - } - switch (timing_config->caodt) { - case 240: - pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; - break; - case 120: - pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; - break; - case 80: - pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; - break; - case 60: - pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; - break; - case 48: - pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; - break; - case 40: - default: - pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; - break; + if (timing_config->odt) { + switch (timing_config->dramodt) { + case 240: + tmp = LPDDR4_DQODT_240; + break; + case 120: + tmp = LPDDR4_DQODT_120; + break; + case 80: + tmp = LPDDR4_DQODT_80; + break; + case 60: + tmp = LPDDR4_DQODT_60; + break; + case 48: + tmp = LPDDR4_DQODT_48; + break; + case 40: + default: + tmp = LPDDR4_DQODT_40; + break; + } + + switch (timing_config->caodt) { + case 240: + pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; + break; + case 120: + pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; + break; + case 80: + pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; + break; + case 60: + pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; + break; + case 48: + pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; + break; + case 40: + default: + pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; + break; + } + } else { + pdram_timing->mr11 = LPDDR4_CAODT_DIS | tmp; } pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000; diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c index f408d676..42cbf987 100644 --- a/plat/rockchip/rk3399/drivers/dram/suspend.c +++ b/plat/rockchip/rk3399/drivers/dram/suspend.c @@ -34,6 +34,7 @@ #include <dram.h> #include <pmu_regs.h> #include <rk3399_def.h> +#include <secure.h> #include <soc.h> #include <suspend.h> @@ -571,14 +572,15 @@ static __sramfunc void pctl_cfg(uint32_t ch, sram_regcpy(PHY_REG(ch, 768), (uintptr_t)¶ms_phy[768], 38); } -static __sramfunc int dram_switch_to_phy_index1( +static __sramfunc int dram_switch_to_next_index( struct rk3399_sdram_params *sdram_params) { uint32_t ch, ch_count; + uint32_t fn = ((mmio_read_32(CTL_REG(0, 111)) >> 16) + 1) & 0x1; mmio_write_32(CIC_BASE + CIC_CTRL0, (((0x3 << 4) | (1 << 2) | 1) << 16) | - (1 << 4) | (1 << 2) | 1); + (fn << 4) | (1 << 2) | 1); while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2))) ; @@ -591,7 +593,7 @@ static __sramfunc int dram_switch_to_phy_index1( /* LPDDR4 f2 cann't do training, all training will fail */ for (ch = 0; ch < ch_count; ch++) { mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, - 1 << 8); + fn << 8); /* data_training failed */ if (data_training(ch, sdram_params, PI_FULL_TRAINING)) @@ -609,6 +611,7 @@ static __sramfunc int pctl_start(uint32_t channel_mask, struct rk3399_sdram_params *sdram_params) { uint32_t count; + uint32_t byte; mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); @@ -640,6 +643,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask, } mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); + + /* Restore the PHY_RX_CAL_DQS value */ + for (byte = 0; byte < 4; byte++) + mmio_clrsetbits_32(PHY_REG(0, 57 + 128 * byte), + 0xfff << 16, + sdram_params->rx_cal_dqs[0][byte]); } if (channel_mask & (1 << 1)) { count = 0; @@ -653,6 +662,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask, } mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); + + /* Restore the PHY_RX_CAL_DQS value */ + for (byte = 0; byte < 4; byte++) + mmio_clrsetbits_32(PHY_REG(1, 57 + 128 * byte), + 0xfff << 16, + sdram_params->rx_cal_dqs[1][byte]); } return 0; @@ -665,7 +680,7 @@ void dmc_save(void) uint32_t *params_pi; uint32_t *params_phy; uint32_t refdiv, postdiv2, postdiv1, fbdiv; - uint32_t tmp; + uint32_t tmp, ch, byte; params_ctl = sdram_params->pctl_regs.denali_ctl; params_pi = sdram_params->pi_regs.denali_pi; @@ -705,6 +720,12 @@ void dmc_save(void) sram_regcpy((uintptr_t)¶ms_phy[768], PHY_REG(0, 768), 38); sram_regcpy((uintptr_t)¶ms_phy[896], PHY_REG(0, 896), 63); + for (ch = 0; ch < sdram_params->num_channels; ch++) { + for (byte = 0; byte < 4; byte++) + sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) & + mmio_read_32(PHY_REG(ch, 57 + byte * 128)); + } + /* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */ params_phy[957] &= ~(0x3 << 24); params_phy[957] |= 1 << 24; @@ -754,5 +775,5 @@ retry: dram_all_config(sdram_params); /* Switch to index 1 and prepare for DDR frequency switch. */ - dram_switch_to_phy_index1(sdram_params); + dram_switch_to_next_index(sdram_params); } diff --git a/plat/rockchip/rk3399/drivers/m0/Makefile b/plat/rockchip/rk3399/drivers/m0/Makefile index c9454fe6..b2dac4a8 100644 --- a/plat/rockchip/rk3399/drivers/m0/Makefile +++ b/plat/rockchip/rk3399/drivers/m0/Makefile @@ -46,32 +46,29 @@ export Q .SUFFIXES: -INCLUDES += -Iinclude/ +INCLUDES += -Iinclude/ \ + -I../../include/shared/ # NOTE: Add C source files here C_SOURCES := src/startup.c \ - src/main.c + src/main.c \ + src/suspend.c \ + src/dram.c \ + src/stopwatch.c # Flags definition -CFLAGS := -g -ASFLAGS := -g -Wa,--gdwarf-2 - -ASFLAGS += -mcpu=$(ARCH) -mthumb -Wall -ffunction-sections -O3 -CFLAGS += -mcpu=$(ARCH) -mthumb -Wall -ffunction-sections -O3 - -LDFLAGS := -mcpu=$(ARCH) -mthumb -g -nostartfiles -nostdlib -O3 -LDFLAGS += -Wl,--gc-sections -Wl,--build-id=none +COMMON_FLAGS := -g -mcpu=$(ARCH) -mthumb -Wall -O3 -nostdlib -mfloat-abi=soft +CFLAGS := -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-common +ASFLAGS := -Wa,--gdwarf-2 +LDFLAGS := -Wl,--gc-sections -Wl,--build-id=none # Cross tool CC := ${M0_CROSS_COMPILE}gcc CPP := ${M0_CROSS_COMPILE}cpp -AS := ${M0_CROSS_COMPILE}gcc AR := ${M0_CROSS_COMPILE}ar -LD := ${M0_CROSS_COMPILE}ld OC := ${M0_CROSS_COMPILE}objcopy OD := ${M0_CROSS_COMPILE}objdump NM := ${M0_CROSS_COMPILE}nm -PP := ${M0_CROSS_COMPILE}gcc -E ${CFLAGS} # NOTE: The line continuation '\' is required in the next define otherwise we # end up with a line-feed characer at the end of the last c filename. @@ -83,10 +80,11 @@ endef SOURCES := $(C_SOURCES) OBJS := $(addprefix $(BUILD)/,$(call SOURCES_TO_OBJS,$(SOURCES))) -LINKERFILE := src/rk3399m0.ld +LINKERFILE := $(BUILD)/$(PLAT_M0).ld MAPFILE := $(BUILD)/$(PLAT_M0).map ELF := $(BUILD)/$(PLAT_M0).elf BIN := $(BUILD)/$(PLAT_M0).bin +LINKERFILE_SRC := src/$(PLAT_M0).ld.S # Function definition related compilation define MAKE_C @@ -95,7 +93,7 @@ $(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) $(OBJ) : $(2) @echo " CC $$<" - $$(Q)$$(CC) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@ + $$(Q)$$(CC) $$(COMMON_FLAGS) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@ endef define MAKE_S @@ -103,7 +101,7 @@ $(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2)))) $(OBJ) : $(2) @echo " AS $$<" - $$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@ + $$(Q)$$(CC) -x assembler-with-cpp $$(COMMON_FLAGS) $$(ASFLAGS) -c $$< -o $$@ endef define MAKE_OBJS @@ -118,13 +116,15 @@ define MAKE_OBJS $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN))) endef -.PHONY: all -all: $(BIN) +.DEFAULT_GOAL := $(BIN) + +$(LINKERFILE): $(LINKERFILE_SRC) + $(CC) $(COMMON_FLAGS) $(INCLUDES) -P -E -D__LINKER__ -MMD -MF $@.d -MT $@ -o $@ $< +-include $(LINKERFILE).d $(ELF) : $(OBJS) $(LINKERFILE) @echo " LD $@" - $(Q)$(CC) -o $@ $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) \ - $(OBJS) + $(Q)$(CC) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) $(OBJS) $(BIN) : $(ELF) @echo " BIN $@" diff --git a/plat/rockchip/rk3399/drivers/pmu/rk3399m0.h b/plat/rockchip/rk3399/drivers/m0/include/addressmap.h index 78b350a2..715d8c16 100644 --- a/plat/rockchip/rk3399/drivers/pmu/rk3399m0.h +++ b/plat/rockchip/rk3399/drivers/m0/include/addressmap.h @@ -28,13 +28,12 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __RK3399M0_H__ -#define __RK3399M0_H__ +#ifndef __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__ +#define __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__ -/* pmu_fw.c */ -extern char rk3399m0_bin[]; -extern char rk3399m0_bin_end[]; +#include <addressmap_shared.h> -#define M0_BINCODE_BASE ((uintptr_t)rk3399m0_bin) +/* Registers base address for M0 */ +#define MMIO_BASE 0x40000000 -#endif /* __RK3399M0_H__ */ +#endif /* __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__ */ diff --git a/plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h b/plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h index 7ea40fac..b6ea3e88 100644 --- a/plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h +++ b/plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h @@ -31,11 +31,28 @@ #ifndef __RK3399_MCU_H__ #define __RK3399_MCU_H__ -#define readl(c) ({unsigned int __v = \ +#include <addressmap.h> + +typedef unsigned int uint32_t; + +#define mmio_read_32(c) ({unsigned int __v = \ (*(volatile unsigned int *)(c)); __v; }) -#define writel(v, c) ((*(volatile unsigned int *) (c)) = (v)) +#define mmio_write_32(c, v) ((*(volatile unsigned int *)(c)) = (v)) + +#define mmio_clrbits_32(addr, clear) \ + mmio_write_32(addr, (mmio_read_32(addr) & ~(clear))) +#define mmio_setbits_32(addr, set) \ + mmio_write_32(addr, (mmio_read_32(addr)) | (set)) +#define mmio_clrsetbits_32(addr, clear, set) \ + mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set)) + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#define MCU_BASE 0x40000000 -#define PMU_BASE (MCU_BASE + 0x07310000) +void handle_suspend(void); +void handle_dram(void); +void stopwatch_init_usecs_expire(unsigned int usecs); +int stopwatch_expired(void); +void stopwatch_reset(void); #endif /* __RK3399_MCU_H__ */ diff --git a/plat/rockchip/rk3399/drivers/m0/src/dram.c b/plat/rockchip/rk3399/drivers/m0/src/dram.c new file mode 100644 index 00000000..bd46843b --- /dev/null +++ b/plat/rockchip/rk3399/drivers/m0/src/dram.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dram_regs.h> +#include <m0_param.h> +#include <pmu_bits.h> +#include <pmu_regs.h> +#include "misc_regs.h" +#include "rk3399_mcu.h" + +static uint32_t gatedis_con0; + +static void idle_port(void) +{ + gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); + mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff); + + mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, + (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); + while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & + ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) != + ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) + continue; +} + +static void deidle_port(void) +{ + mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, + (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); + while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & + ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) + continue; + + /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ + mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0); +} + +static void ddr_set_pll(void) +{ + mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); + + mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); + mmio_write_32(CRU_BASE + CRU_DPLL_CON0, + mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); + mmio_write_32(CRU_BASE + CRU_DPLL_CON1, + mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); + mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); + + while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) + continue; + + mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); +} + +void handle_dram(void) +{ + mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); + mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); + idle_port(); + + mmio_write_32(CIC_BASE + CIC_CTRL0, + (((0x3 << 4) | (1 << 2) | 1) << 16) | + (1 << 2) | 1 | + mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); + while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0) + continue; + + ddr_set_pll(); + mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); + while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0) + continue; + + deidle_port(); + mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); + mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); +} diff --git a/plat/rockchip/rk3399/drivers/m0/src/main.c b/plat/rockchip/rk3399/drivers/m0/src/main.c index 2e583c70..95659c4e 100644 --- a/plat/rockchip/rk3399/drivers/m0/src/main.c +++ b/plat/rockchip/rk3399/drivers/m0/src/main.c @@ -28,44 +28,24 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include <m0_param.h> #include "rk3399_mcu.h" -#define PMU_PWRMODE_CON 0x20 -#define PMU_POWER_ST 0x78 - -#define M0_SCR 0xe000ed10 /* System Control Register (SCR) */ - -#define SCR_SLEEPDEEP_SHIFT (1 << 2) - -static void system_wakeup(void) +__attribute__((noreturn)) void main(void) { - unsigned int status_value; - unsigned int mode_con; - - while (1) { - status_value = readl(PMU_BASE + PMU_POWER_ST); - if (status_value) { - mode_con = readl(PMU_BASE + PMU_PWRMODE_CON); - writel(mode_con & (~0x01), - PMU_BASE + PMU_PWRMODE_CON); - return; - } + switch (mmio_read_32(PARAM_ADDR + PARAM_M0_FUNC)) { + case M0_FUNC_SUSPEND: + handle_suspend(); + break; + case M0_FUNC_DRAM: + handle_dram(); + break; + default: + break; } -} -int main(void) -{ - unsigned int reg_src; - - system_wakeup(); - - reg_src = readl(M0_SCR); - - /* m0 enter deep sleep mode */ - writel(reg_src | SCR_SLEEPDEEP_SHIFT, M0_SCR); + mmio_write_32(PARAM_ADDR + PARAM_M0_DONE, M0_DONE_FLAG); for (;;) - __asm volatile("wfi"); - - return 0; + __asm__ volatile ("wfi"); } diff --git a/plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld b/plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld.S index 0b7b124d..cb224f09 100644 --- a/plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld +++ b/plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld.S @@ -28,12 +28,16 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include <m0_param.h> + OUTPUT_FORMAT("elf32-littlearm") SECTIONS { .m0_bin 0 : { KEEP(*(.isr_vector)) ASSERT(. == 0xc0, "ISR vector has the wrong size."); + ASSERT(. == PARAM_ADDR, "M0 params should go right behind ISR table."); + . += PARAM_M0_SIZE; *(.text*) *(.rodata*) *(.data*) diff --git a/plat/rockchip/rk3399/drivers/m0/src/stopwatch.c b/plat/rockchip/rk3399/drivers/m0/src/stopwatch.c new file mode 100644 index 00000000..4f4a961d --- /dev/null +++ b/plat/rockchip/rk3399/drivers/m0/src/stopwatch.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <m0_param.h> +#include "rk3399_mcu.h" + +/* use 24MHz SysTick */ +#define US_TO_CYCLE(US) (US * 24) + +#define SYST_CST 0xe000e010 +/* enable counter */ +#define ENABLE (1 << 0) +/* count down to 0 does not cause SysTick exception to pend */ +#define TICKINT (1 << 1) +/* core clock used for SysTick */ +#define CLKSOURCE (1 << 2) + +#define COUNTFLAG (1 << 16) +#define SYST_RVR 0xe000e014 +#define MAX_VALUE 0xffffff +#define MAX_USECS (MAX_VALUE / US_TO_CYCLE(1)) +#define SYST_CVR 0xe000e018 +#define SYST_CALIB 0xe000e01c + +unsigned int remaining_usecs; + +static inline void stopwatch_set_usecs(void) +{ + unsigned int cycle; + unsigned int usecs = MIN(MAX_USECS, remaining_usecs); + + remaining_usecs -= usecs; + cycle = US_TO_CYCLE(usecs); + mmio_write_32(SYST_RVR, cycle); + mmio_write_32(SYST_CVR, 0); + + mmio_write_32(SYST_CST, ENABLE | TICKINT | CLKSOURCE); +} + +void stopwatch_init_usecs_expire(unsigned int usecs) +{ + /* + * Enter an inifite loop if the stopwatch is in use. This will allow the + * state to be analyzed with a debugger. + */ + if (mmio_read_32(SYST_CST) & ENABLE) + while (1) + ; + + remaining_usecs = usecs; + stopwatch_set_usecs(); +} + +int stopwatch_expired(void) +{ + int val = mmio_read_32(SYST_CST); + if ((val & COUNTFLAG) || !(val & ENABLE)) { + if (!remaining_usecs) + return 1; + + stopwatch_set_usecs(); + } + + return 0; +} + +void stopwatch_reset(void) +{ + mmio_clrbits_32(SYST_CST, ENABLE); + remaining_usecs = 0; +} diff --git a/plat/rockchip/rk3399/drivers/m0/src/suspend.c b/plat/rockchip/rk3399/drivers/m0/src/suspend.c new file mode 100644 index 00000000..71be71d7 --- /dev/null +++ b/plat/rockchip/rk3399/drivers/m0/src/suspend.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <pmu_regs.h> +#include "rk3399_mcu.h" + +#define M0_SCR 0xe000ed10 /* System Control Register (SCR) */ + +#define SCR_SLEEPDEEP_SHIFT (1 << 2) + +void handle_suspend(void) +{ + unsigned int status_value; + + while (1) { + status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); + if (status_value) { + mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01); + return; + } + } + + /* m0 enter deep sleep mode */ + mmio_setbits_32(M0_SCR, SCR_SLEEPDEEP_SHIFT); +} diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c new file mode 100644 index 00000000..6bdd04b7 --- /dev/null +++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch_helpers.h> +#include <assert.h> +#include <debug.h> +#include <delay_timer.h> +#include <mmio.h> +#include <m0_ctl.h> +#include <plat_private.h> +#include <rk3399_def.h> +#include <secure.h> +#include <soc.h> + +void m0_init(void) +{ + /* secure config for M0 */ + mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12)); + + /* set the execute address for M0 */ + mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), + BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff, + 0xffff, 0)); + mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), + BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf, + 0xf, 0)); + + /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ + mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02); + + /* + * To switch the parent to xin24M and div == 1, + * + * We need to close most of the PLLs and clocks except the OSC 24MHz + * durning suspend, and this should be enough to supplies the ddrfreq, + * For the simple handle, we just keep the fixed 24MHz to supply the + * suspend and ddrfreq directly. + */ + mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, + BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); + + mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); +} + +void m0_start(void) +{ + /* enable clocks for M0 */ + mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, + BITS_WITH_WMASK(0x0, 0xf, 0)); + + /* clean the PARAM_M0_DONE flag, mean that M0 will start working */ + mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0); + dmbst(); + + mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, + BITS_WITH_WMASK(0x0, 0x4, 0)); + + udelay(5); + /* start M0 */ + mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, + BITS_WITH_WMASK(0x0, 0x20, 0)); + dmbst(); +} + +void m0_stop(void) +{ + /* stop M0 */ + mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, + BITS_WITH_WMASK(0x24, 0x24, 0)); + + /* disable clocks for M0 */ + mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, + BITS_WITH_WMASK(0xf, 0xf, 0)); +} + +void m0_wait_done(void) +{ + do { + /* + * Don't starve the M0 for access to SRAM, so delay before + * reading the PARAM_M0_DONE value again. + */ + udelay(5); + dsb(); + } while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG); + + /* + * Let the M0 settle into WFI before we leave. This is so we don't reset + * the M0 in a bad spot which can cause problems with the M0. + */ + udelay(10); + dsb(); +} diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h new file mode 100644 index 00000000..c21caab1 --- /dev/null +++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __M0_CTL_H__ +#define __M0_CTL_H__ + +#include <m0_param.h> + +#define M0_BINCODE_BASE ((uintptr_t)rk3399m0_bin) +#define M0_PARAM_ADDR (M0_BINCODE_BASE + PARAM_ADDR) + +/* pmu_fw.c */ +extern char rk3399m0_bin[]; +extern char rk3399m0_bin_end[]; + +extern void m0_init(void); +extern void m0_start(void); +extern void m0_stop(void); +extern void m0_wait_done(void); +#endif /* __M0_CTL_H__ */ diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 05ca7fdd..e04d4744 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -33,21 +33,23 @@ #include <bakery_lock.h> #include <debug.h> #include <delay_timer.h> +#include <dfs.h> #include <errno.h> #include <gpio.h> #include <mmio.h> +#include <m0_ctl.h> #include <platform.h> #include <platform_def.h> #include <plat_params.h> #include <plat_private.h> #include <rk3399_def.h> #include <pmu_sram.h> +#include <secure.h> #include <soc.h> #include <pmu.h> #include <pmu_com.h> #include <pwm.h> #include <bl31.h> -#include <rk3399m0.h> #include <suspend.h> DEFINE_BAKERY_LOCK(rockchip_pd_lock); @@ -1065,36 +1067,10 @@ static void resume_gpio(void) } } -static void m0_clock_init(void) +static void m0_configure_suspend(void) { - /* enable clocks for M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, - BITS_WITH_WMASK(0x0, 0x2f, 0)); - - /* switch the parent to xin24M and div == 1 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, - BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); - - /* start M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, - BITS_WITH_WMASK(0x0, 0x24, 0)); - - /* gating disable for M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(1)); -} - -static void m0_reset(void) -{ - /* stop M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, - BITS_WITH_WMASK(0x24, 0x24, 0)); - - /* recover gating bit for M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, WMSK_BIT(1)); - - /* disable clocks for M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, - BITS_WITH_WMASK(0x2f, 0x2f, 0)); + /* set PARAM to M0_FUNC_SUSPEND */ + mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_SUSPEND); } static int sys_pwr_domain_suspend(void) @@ -1102,6 +1078,7 @@ static int sys_pwr_domain_suspend(void) uint32_t wait_cnt = 0; uint32_t status = 0; + ddr_prepare_for_sys_suspend(); dmc_save(); pmu_scu_b_pwrdn(); @@ -1117,11 +1094,12 @@ static int sys_pwr_domain_suspend(void) sys_slp_config(); - m0_clock_init(); + m0_configure_suspend(); + m0_start(); pmu_sgrf_rst_hld(); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); @@ -1173,7 +1151,7 @@ static int sys_pwr_domain_resume(void) udelay(300); enable_dvfs_plls(); - secure_watchdog_restore(); + secure_watchdog_enable(); /* restore clk_ddrc_bpll_src_en gate */ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), @@ -1189,7 +1167,7 @@ static int sys_pwr_domain_resume(void) mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff); mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); @@ -1241,8 +1219,9 @@ static int sys_pwr_domain_resume(void) BIT(PMU_CLR_GIC)); plat_rockchip_gic_cpuif_enable(); + m0_stop(); - m0_reset(); + ddr_prepare_for_sys_resume(); return 0; } @@ -1328,7 +1307,7 @@ void plat_rockchip_pmu_init(void) psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; /* config cpu's warm boot address */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE); diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h index 22c8c637..08d55a86 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.h +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h @@ -31,6 +31,7 @@ #ifndef __PMU_H__ #define __PMU_H__ +#include <pmu_bits.h> #include <pmu_regs.h> #include <soc.h> @@ -67,693 +68,6 @@ enum pmu_core_pwrst_shift { #define CKECK_WFI_MSK 0x10 #define CKECK_WFEI_MSK 0x11 -enum pmu_powerdomain_id { - PD_CPUL0 = 0, - PD_CPUL1, - PD_CPUL2, - PD_CPUL3, - PD_CPUB0, - PD_CPUB1, - PD_SCUL, - PD_SCUB, - PD_TCPD0, - PD_TCPD1, - PD_CCI, - PD_PERILP, - PD_PERIHP, - PD_CENTER, - PD_VIO, - PD_GPU, - PD_VCODEC, - PD_VDU, - PD_RGA, - PD_IEP, - PD_VO, - PD_ISP0 = 22, - PD_ISP1, - PD_HDCP, - PD_GMAC, - PD_EMMC, - PD_USB3, - PD_EDP, - PD_GIC, - PD_SD, - PD_SDIOAUDIO, - PD_END -}; - -enum powerdomain_state { - PMU_POWER_ON = 0, - PMU_POWER_OFF, -}; - -enum pmu_bus_id { - BUS_ID_GPU = 0, - BUS_ID_PERILP, - BUS_ID_PERIHP, - BUS_ID_VCODEC, - BUS_ID_VDU, - BUS_ID_RGA, - BUS_ID_IEP, - BUS_ID_VOPB, - BUS_ID_VOPL, - BUS_ID_ISP0, - BUS_ID_ISP1, - BUS_ID_HDCP, - BUS_ID_USB3, - BUS_ID_PERILPM0, - BUS_ID_CENTER, - BUS_ID_CCIM0, - BUS_ID_CCIM1, - BUS_ID_VIO, - BUS_ID_MSCH0, - BUS_ID_MSCH1, - BUS_ID_ALIVE, - BUS_ID_PMU, - BUS_ID_EDP, - BUS_ID_GMAC, - BUS_ID_EMMC, - BUS_ID_CENTER1, - BUS_ID_PMUM0, - BUS_ID_GIC, - BUS_ID_SD, - BUS_ID_SDIOAUDIO, -}; - -enum pmu_bus_state { - BUS_ACTIVE, - BUS_IDLE, -}; - -/* pmu_cpuapm bit */ -enum pmu_cores_pm_by_wfi { - core_pm_en = 0, - core_pm_int_wakeup_en, - core_pm_resv, - core_pm_sft_wakeup_en -}; - -enum pmu_wkup_cfg0 { - PMU_GPIO0A_POSE_WKUP_EN = 0, - PMU_GPIO0B_POSE_WKUP_EN = 8, - PMU_GPIO0C_POSE_WKUP_EN = 16, - PMU_GPIO0D_POSE_WKUP_EN = 24, -}; - -enum pmu_wkup_cfg1 { - PMU_GPIO0A_NEGEDGE_WKUP_EN = 0, - PMU_GPIO0B_NEGEDGE_WKUP_EN = 7, - PMU_GPIO0C_NEGEDGE_WKUP_EN = 16, - PMU_GPIO0D_NEGEDGE_WKUP_EN = 24, -}; - -enum pmu_wkup_cfg2 { - PMU_GPIO1A_POSE_WKUP_EN = 0, - PMU_GPIO1B_POSE_WKUP_EN = 7, - PMU_GPIO1C_POSE_WKUP_EN = 16, - PMU_GPIO1D_POSE_WKUP_EN = 24, -}; - -enum pmu_wkup_cfg3 { - PMU_GPIO1A_NEGEDGE_WKUP_EN = 0, - PMU_GPIO1B_NEGEDGE_WKUP_EN = 7, - PMU_GPIO1C_NEGEDGE_WKUP_EN = 16, - PMU_GPIO1D_NEGEDGE_WKUP_EN = 24, -}; - -/* pmu_wkup_cfg4 */ -enum pmu_wkup_cfg4 { - PMU_CLUSTER_L_WKUP_EN = 0, - PMU_CLUSTER_B_WKUP_EN, - PMU_GPIO_WKUP_EN, - PMU_SDIO_WKUP_EN, - - PMU_SDMMC_WKUP_EN, - PMU_TIMER_WKUP_EN = 6, - PMU_USBDEV_WKUP_EN, - - PMU_SFT_WKUP_EN, - PMU_M0_WDT_WKUP_EN, - PMU_TIMEOUT_WKUP_EN, - PMU_PWM_WKUP_EN, - - PMU_PCIE_WKUP_EN = 13, -}; - -enum pmu_pwrdn_con { - PMU_A53_L0_PWRDWN_EN = 0, - PMU_A53_L1_PWRDWN_EN, - PMU_A53_L2_PWRDWN_EN, - PMU_A53_L3_PWRDWN_EN, - - PMU_A72_B0_PWRDWN_EN, - PMU_A72_B1_PWRDWN_EN, - PMU_SCU_L_PWRDWN_EN, - PMU_SCU_B_PWRDWN_EN, - - PMU_TCPD0_PWRDWN_EN, - PMU_TCPD1_PWRDWN_EN, - PMU_CCI_PWRDWN_EN, - PMU_PERILP_PWRDWN_EN, - - PMU_PERIHP_PWRDWN_EN, - PMU_CENTER_PWRDWN_EN, - PMU_VIO_PWRDWN_EN, - PMU_GPU_PWRDWN_EN, - - PMU_VCODEC_PWRDWN_EN, - PMU_VDU_PWRDWN_EN, - PMU_RGA_PWRDWN_EN, - PMU_IEP_PWRDWN_EN, - - PMU_VO_PWRDWN_EN, - PMU_ISP0_PWRDWN_EN = 22, - PMU_ISP1_PWRDWN_EN, - - PMU_HDCP_PWRDWN_EN, - PMU_GMAC_PWRDWN_EN, - PMU_EMMC_PWRDWN_EN, - PMU_USB3_PWRDWN_EN, - - PMU_EDP_PWRDWN_EN, - PMU_GIC_PWRDWN_EN, - PMU_SD_PWRDWN_EN, - PMU_SDIOAUDIO_PWRDWN_EN, -}; - -enum pmu_pwrdn_st { - PMU_A53_L0_PWRDWN_ST = 0, - PMU_A53_L1_PWRDWN_ST, - PMU_A53_L2_PWRDWN_ST, - PMU_A53_L3_PWRDWN_ST, - - PMU_A72_B0_PWRDWN_ST, - PMU_A72_B1_PWRDWN_ST, - PMU_SCU_L_PWRDWN_ST, - PMU_SCU_B_PWRDWN_ST, - - PMU_TCPD0_PWRDWN_ST, - PMU_TCPD1_PWRDWN_ST, - PMU_CCI_PWRDWN_ST, - PMU_PERILP_PWRDWN_ST, - - PMU_PERIHP_PWRDWN_ST, - PMU_CENTER_PWRDWN_ST, - PMU_VIO_PWRDWN_ST, - PMU_GPU_PWRDWN_ST, - - PMU_VCODEC_PWRDWN_ST, - PMU_VDU_PWRDWN_ST, - PMU_RGA_PWRDWN_ST, - PMU_IEP_PWRDWN_ST, - - PMU_VO_PWRDWN_ST, - PMU_ISP0_PWRDWN_ST = 22, - PMU_ISP1_PWRDWN_ST, - - PMU_HDCP_PWRDWN_ST, - PMU_GMAC_PWRDWN_ST, - PMU_EMMC_PWRDWN_ST, - PMU_USB3_PWRDWN_ST, - - PMU_EDP_PWRDWN_ST, - PMU_GIC_PWRDWN_ST, - PMU_SD_PWRDWN_ST, - PMU_SDIOAUDIO_PWRDWN_ST, - -}; - -enum pmu_pll_con { - PMU_PLL_PD_CFG = 0, - PMU_SFT_PLL_PD = 8, -}; - -enum pmu_pwermode_con { - PMU_PWR_MODE_EN = 0, - PMU_WKUP_RST_EN, - PMU_INPUT_CLAMP_EN, - PMU_OSC_DIS, - - PMU_ALIVE_USE_LF, - PMU_PMU_USE_LF, - PMU_POWER_OFF_REQ_CFG, - PMU_CHIP_PD_EN, - - PMU_PLL_PD_EN, - PMU_CPU0_PD_EN, - PMU_L2_FLUSH_EN, - PMU_L2_IDLE_EN, - - PMU_SCU_PD_EN, - PMU_CCI_PD_EN, - PMU_PERILP_PD_EN, - PMU_CENTER_PD_EN, - - PMU_SREF0_ENTER_EN, - PMU_DDRC0_GATING_EN, - PMU_DDRIO0_RET_EN, - PMU_DDRIO0_RET_DE_REQ, - - PMU_SREF1_ENTER_EN, - PMU_DDRC1_GATING_EN, - PMU_DDRIO1_RET_EN, - PMU_DDRIO1_RET_DE_REQ, - - PMU_CLK_CENTER_SRC_GATE_EN = 26, - PMU_CLK_PERILP_SRC_GATE_EN, - - PMU_CLK_CORE_SRC_GATE_EN, - PMU_DDRIO_RET_HW_DE_REQ, - PMU_SLP_OUTPUT_CFG, - PMU_MAIN_CLUSTER, -}; - -enum pmu_sft_con { - PMU_WKUP_SFT = 0, - PMU_INPUT_CLAMP_CFG, - PMU_OSC_DIS_CFG, - PMU_PMU_LF_EN_CFG, - - PMU_ALIVE_LF_EN_CFG, - PMU_24M_EN_CFG, - PMU_DBG_PWRUP_L0_CFG, - PMU_WKUP_SFT_M0, - - PMU_DDRCTL0_C_SYSREQ_CFG, - PMU_DDR0_IO_RET_CFG, - - PMU_DDRCTL1_C_SYSREQ_CFG = 12, - PMU_DDR1_IO_RET_CFG, - DBG_PWRUP_B0_CFG = 15, - - DBG_NOPWERDWN_L0_EN, - DBG_NOPWERDWN_L1_EN, - DBG_NOPWERDWN_L2_EN, - DBG_NOPWERDWN_L3_EN, - - DBG_PWRUP_REQ_L_EN = 20, - CLUSTER_L_CLK_SRC_GATING_CFG, - L2_FLUSH_REQ_CLUSTER_L, - ACINACTM_CLUSTER_L_CFG, - - DBG_NO_PWERDWN_B0_EN, - DBG_NO_PWERDWN_B1_EN, - - DBG_PWRUP_REQ_B_EN = 28, - CLUSTER_B_CLK_SRC_GATING_CFG, - L2_FLUSH_REQ_CLUSTER_B, - ACINACTM_CLUSTER_B_CFG, -}; - -enum pmu_int_con { - PMU_PMU_INT_EN = 0, - PMU_PWRMD_WKUP_INT_EN, - PMU_WKUP_GPIO0_NEG_INT_EN, - PMU_WKUP_GPIO0_POS_INT_EN, - PMU_WKUP_GPIO1_NEG_INT_EN, - PMU_WKUP_GPIO1_POS_INT_EN, -}; - -enum pmu_int_st { - PMU_PWRMD_WKUP_INT_ST = 1, - PMU_WKUP_GPIO0_NEG_INT_ST, - PMU_WKUP_GPIO0_POS_INT_ST, - PMU_WKUP_GPIO1_NEG_INT_ST, - PMU_WKUP_GPIO1_POS_INT_ST, -}; - -enum pmu_gpio0_pos_int_con { - PMU_GPIO0A_POS_INT_EN = 0, - PMU_GPIO0B_POS_INT_EN = 8, - PMU_GPIO0C_POS_INT_EN = 16, - PMU_GPIO0D_POS_INT_EN = 24, -}; - -enum pmu_gpio0_neg_int_con { - PMU_GPIO0A_NEG_INT_EN = 0, - PMU_GPIO0B_NEG_INT_EN = 8, - PMU_GPIO0C_NEG_INT_EN = 16, - PMU_GPIO0D_NEG_INT_EN = 24, -}; - -enum pmu_gpio1_pos_int_con { - PMU_GPIO1A_POS_INT_EN = 0, - PMU_GPIO1B_POS_INT_EN = 8, - PMU_GPIO1C_POS_INT_EN = 16, - PMU_GPIO1D_POS_INT_EN = 24, -}; - -enum pmu_gpio1_neg_int_con { - PMU_GPIO1A_NEG_INT_EN = 0, - PMU_GPIO1B_NEG_INT_EN = 8, - PMU_GPIO1C_NEG_INT_EN = 16, - PMU_GPIO1D_NEG_INT_EN = 24, -}; - -enum pmu_gpio0_pos_int_st { - PMU_GPIO0A_POS_INT_ST = 0, - PMU_GPIO0B_POS_INT_ST = 8, - PMU_GPIO0C_POS_INT_ST = 16, - PMU_GPIO0D_POS_INT_ST = 24, -}; - -enum pmu_gpio0_neg_int_st { - PMU_GPIO0A_NEG_INT_ST = 0, - PMU_GPIO0B_NEG_INT_ST = 8, - PMU_GPIO0C_NEG_INT_ST = 16, - PMU_GPIO0D_NEG_INT_ST = 24, -}; - -enum pmu_gpio1_pos_int_st { - PMU_GPIO1A_POS_INT_ST = 0, - PMU_GPIO1B_POS_INT_ST = 8, - PMU_GPIO1C_POS_INT_ST = 16, - PMU_GPIO1D_POS_INT_ST = 24, -}; - -enum pmu_gpio1_neg_int_st { - PMU_GPIO1A_NEG_INT_ST = 0, - PMU_GPIO1B_NEG_INT_ST = 8, - PMU_GPIO1C_NEG_INT_ST = 16, - PMU_GPIO1D_NEG_INT_ST = 24, -}; - -/* pmu power down configure register 0x0050 */ -enum pmu_pwrdn_inten { - PMU_A53_L0_PWR_SWITCH_INT_EN = 0, - PMU_A53_L1_PWR_SWITCH_INT_EN, - PMU_A53_L2_PWR_SWITCH_INT_EN, - PMU_A53_L3_PWR_SWITCH_INT_EN, - - PMU_A72_B0_PWR_SWITCH_INT_EN, - PMU_A72_B1_PWR_SWITCH_INT_EN, - PMU_SCU_L_PWR_SWITCH_INT_EN, - PMU_SCU_B_PWR_SWITCH_INT_EN, - - PMU_TCPD0_PWR_SWITCH_INT_EN, - PMU_TCPD1_PWR_SWITCH_INT_EN, - PMU_CCI_PWR_SWITCH_INT_EN, - PMU_PERILP_PWR_SWITCH_INT_EN, - - PMU_PERIHP_PWR_SWITCH_INT_EN, - PMU_CENTER_PWR_SWITCH_INT_EN, - PMU_VIO_PWR_SWITCH_INT_EN, - PMU_GPU_PWR_SWITCH_INT_EN, - - PMU_VCODEC_PWR_SWITCH_INT_EN, - PMU_VDU_PWR_SWITCH_INT_EN, - PMU_RGA_PWR_SWITCH_INT_EN, - PMU_IEP_PWR_SWITCH_INT_EN, - - PMU_VO_PWR_SWITCH_INT_EN, - PMU_ISP0_PWR_SWITCH_INT_EN = 22, - PMU_ISP1_PWR_SWITCH_INT_EN, - - PMU_HDCP_PWR_SWITCH_INT_EN, - PMU_GMAC_PWR_SWITCH_INT_EN, - PMU_EMMC_PWR_SWITCH_INT_EN, - PMU_USB3_PWR_SWITCH_INT_EN, - - PMU_EDP_PWR_SWITCH_INT_EN, - PMU_GIC_PWR_SWITCH_INT_EN, - PMU_SD_PWR_SWITCH_INT_EN, - PMU_SDIOAUDIO_PWR_SWITCH_INT_EN, -}; - -enum pmu_wkup_status { - PMU_WKUP_BY_CLSTER_L_INT = 0, - PMU_WKUP_BY_CLSTER_b_INT, - PMU_WKUP_BY_GPIO_INT, - PMU_WKUP_BY_SDIO_DET, - - PMU_WKUP_BY_SDMMC_DET, - PMU_WKUP_BY_TIMER = 6, - PMU_WKUP_BY_USBDEV_DET, - - PMU_WKUP_BY_M0_SFT, - PMU_WKUP_BY_M0_WDT_INT, - PMU_WKUP_BY_TIMEOUT, - PMU_WKUP_BY_PWM, - - PMU_WKUP_BY_PCIE = 13, -}; - -enum pmu_bus_clr { - PMU_CLR_GPU = 0, - PMU_CLR_PERILP, - PMU_CLR_PERIHP, - PMU_CLR_VCODEC, - - PMU_CLR_VDU, - PMU_CLR_RGA, - PMU_CLR_IEP, - PMU_CLR_VOPB, - - PMU_CLR_VOPL, - PMU_CLR_ISP0, - PMU_CLR_ISP1, - PMU_CLR_HDCP, - - PMU_CLR_USB3, - PMU_CLR_PERILPM0, - PMU_CLR_CENTER, - PMU_CLR_CCIM1, - - PMU_CLR_CCIM0, - PMU_CLR_VIO, - PMU_CLR_MSCH0, - PMU_CLR_MSCH1, - - PMU_CLR_ALIVE, - PMU_CLR_PMU, - PMU_CLR_EDP, - PMU_CLR_GMAC, - - PMU_CLR_EMMC, - PMU_CLR_CENTER1, - PMU_CLR_PMUM0, - PMU_CLR_GIC, - - PMU_CLR_SD, - PMU_CLR_SDIOAUDIO, -}; - -/* PMU bus idle request register */ -enum pmu_bus_idle_req { - PMU_IDLE_REQ_GPU = 0, - PMU_IDLE_REQ_PERILP, - PMU_IDLE_REQ_PERIHP, - PMU_IDLE_REQ_VCODEC, - - PMU_IDLE_REQ_VDU, - PMU_IDLE_REQ_RGA, - PMU_IDLE_REQ_IEP, - PMU_IDLE_REQ_VOPB, - - PMU_IDLE_REQ_VOPL, - PMU_IDLE_REQ_ISP0, - PMU_IDLE_REQ_ISP1, - PMU_IDLE_REQ_HDCP, - - PMU_IDLE_REQ_USB3, - PMU_IDLE_REQ_PERILPM0, - PMU_IDLE_REQ_CENTER, - PMU_IDLE_REQ_CCIM0, - - PMU_IDLE_REQ_CCIM1, - PMU_IDLE_REQ_VIO, - PMU_IDLE_REQ_MSCH0, - PMU_IDLE_REQ_MSCH1, - - PMU_IDLE_REQ_ALIVE, - PMU_IDLE_REQ_PMU, - PMU_IDLE_REQ_EDP, - PMU_IDLE_REQ_GMAC, - - PMU_IDLE_REQ_EMMC, - PMU_IDLE_REQ_CENTER1, - PMU_IDLE_REQ_PMUM0, - PMU_IDLE_REQ_GIC, - - PMU_IDLE_REQ_SD, - PMU_IDLE_REQ_SDIOAUDIO, -}; - -/* pmu bus idle status register */ -enum pmu_bus_idle_st { - PMU_IDLE_ST_GPU = 0, - PMU_IDLE_ST_PERILP, - PMU_IDLE_ST_PERIHP, - PMU_IDLE_ST_VCODEC, - - PMU_IDLE_ST_VDU, - PMU_IDLE_ST_RGA, - PMU_IDLE_ST_IEP, - PMU_IDLE_ST_VOPB, - - PMU_IDLE_ST_VOPL, - PMU_IDLE_ST_ISP0, - PMU_IDLE_ST_ISP1, - PMU_IDLE_ST_HDCP, - - PMU_IDLE_ST_USB3, - PMU_IDLE_ST_PERILPM0, - PMU_IDLE_ST_CENTER, - PMU_IDLE_ST_CCIM0, - - PMU_IDLE_ST_CCIM1, - PMU_IDLE_ST_VIO, - PMU_IDLE_ST_MSCH0, - PMU_IDLE_ST_MSCH1, - - PMU_IDLE_ST_ALIVE, - PMU_IDLE_ST_PMU, - PMU_IDLE_ST_EDP, - PMU_IDLE_ST_GMAC, - - PMU_IDLE_ST_EMMC, - PMU_IDLE_ST_CENTER1, - PMU_IDLE_ST_PMUM0, - PMU_IDLE_ST_GIC, - - PMU_IDLE_ST_SD, - PMU_IDLE_ST_SDIOAUDIO, -}; - -enum pmu_bus_idle_ack { - PMU_IDLE_ACK_GPU = 0, - PMU_IDLE_ACK_PERILP, - PMU_IDLE_ACK_PERIHP, - PMU_IDLE_ACK_VCODEC, - - PMU_IDLE_ACK_VDU, - PMU_IDLE_ACK_RGA, - PMU_IDLE_ACK_IEP, - PMU_IDLE_ACK_VOPB, - - PMU_IDLE_ACK_VOPL, - PMU_IDLE_ACK_ISP0, - PMU_IDLE_ACK_ISP1, - PMU_IDLE_ACK_HDCP, - - PMU_IDLE_ACK_USB3, - PMU_IDLE_ACK_PERILPM0, - PMU_IDLE_ACK_CENTER, - PMU_IDLE_ACK_CCIM0, - - PMU_IDLE_ACK_CCIM1, - PMU_IDLE_ACK_VIO, - PMU_IDLE_ACK_MSCH0, - PMU_IDLE_ACK_MSCH1, - - PMU_IDLE_ACK_ALIVE, - PMU_IDLE_ACK_PMU, - PMU_IDLE_ACK_EDP, - PMU_IDLE_ACK_GMAC, - - PMU_IDLE_ACK_EMMC, - PMU_IDLE_ACK_CENTER1, - PMU_IDLE_ACK_PMUM0, - PMU_IDLE_ACK_GIC, - - PMU_IDLE_ACK_SD, - PMU_IDLE_ACK_SDIOAUDIO, -}; - -enum pmu_cci500_con { - PMU_PREQ_CCI500_CFG_SW = 0, - PMU_CLR_PREQ_CCI500_HW, - PMU_PSTATE_CCI500_0, - PMU_PSTATE_CCI500_1, - - PMU_PSTATE_CCI500_2, - PMU_QREQ_CCI500_CFG_SW, - PMU_CLR_QREQ_CCI500_HW, - PMU_QGATING_CCI500_CFG, - - PMU_PREQ_CCI500_CFG_SW_WMSK = 16, - PMU_CLR_PREQ_CCI500_HW_WMSK, - PMU_PSTATE_CCI500_0_WMSK, - PMU_PSTATE_CCI500_1_WMSK, - - PMU_PSTATE_CCI500_2_WMSK, - PMU_QREQ_CCI500_CFG_SW_WMSK, - PMU_CLR_QREQ_CCI500_HW_WMSK, - PMU_QGATING_CCI500_CFG_WMSK, -}; - -enum pmu_adb400_con { - PMU_PWRDWN_REQ_CXCS_SW = 0, - PMU_PWRDWN_REQ_CORE_L_SW, - PMU_PWRDWN_REQ_CORE_L_2GIC_SW, - PMU_PWRDWN_REQ_GIC2_CORE_L_SW, - - PMU_PWRDWN_REQ_CORE_B_SW, - PMU_PWRDWN_REQ_CORE_B_2GIC_SW, - PMU_PWRDWN_REQ_GIC2_CORE_B_SW, - - PMU_CLR_CXCS_HW = 8, - PMU_CLR_CORE_L_HW, - PMU_CLR_CORE_L_2GIC_HW, - PMU_CLR_GIC2_CORE_L_HW, - - PMU_CLR_CORE_B_HW, - PMU_CLR_CORE_B_2GIC_HW, - PMU_CLR_GIC2_CORE_B_HW, - - PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16, - PMU_PWRDWN_REQ_CORE_L_SW_WMSK, - PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK, - PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK, - - PMU_PWRDWN_REQ_CORE_B_SW_WMSK, - PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK, - PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK, - - PMU_CLR_CXCS_HW_WMSK = 24, - PMU_CLR_CORE_L_HW_WMSK, - PMU_CLR_CORE_L_2GIC_HW_WMSK, - PMU_CLR_GIC2_CORE_L_HW_WMSK, - - PMU_CLR_CORE_B_HW_WMSK, - PMU_CLR_CORE_B_2GIC_HW_WMSK, - PMU_CLR_GIC2_CORE_B_HW_WMSK, -}; - -enum pmu_adb400_st { - PMU_PWRDWN_REQ_CXCS_SW_ST = 0, - PMU_PWRDWN_REQ_CORE_L_SW_ST, - PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST, - PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST, - - PMU_PWRDWN_REQ_CORE_B_SW_ST, - PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST, - PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST, - - PMU_CLR_CXCS_HW_ST = 8, - PMU_CLR_CORE_L_HW_ST, - PMU_CLR_CORE_L_2GIC_HW_ST, - PMU_CLR_GIC2_CORE_L_HW_ST, - - PMU_CLR_CORE_B_HW_ST, - PMU_CLR_CORE_B_2GIC_HW_ST, - PMU_CLR_GIC2_CORE_B_HW_ST, -}; - -enum pmu_pwrdn_con1 { - PMU_VD_SCU_L_PWRDN_EN = 0, - PMU_VD_SCU_B_PWRDN_EN, - PMU_VD_CENTER_PWRDN_EN, -}; - -enum pmu_core_pwr_st { - L2_FLUSHDONE_CLUSTER_L = 0, - STANDBY_BY_WFIL2_CLUSTER_L, - - L2_FLUSHDONE_CLUSTER_B = 10, - STANDBY_BY_WFIL2_CLUSTER_B, -}; - /* Specific features required */ #define AP_PWROFF 0x0a diff --git a/plat/rockchip/rk3399/drivers/secure/secure.c b/plat/rockchip/rk3399/drivers/secure/secure.c new file mode 100644 index 00000000..d3c8cb8a --- /dev/null +++ b/plat/rockchip/rk3399/drivers/secure/secure.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch_helpers.h> +#include <assert.h> +#include <debug.h> +#include <delay_timer.h> +#include <plat_private.h> +#include <secure.h> +#include <soc.h> + +static void sgrf_ddr_rgn_global_bypass(uint32_t bypass) +{ + if (bypass) + /* set bypass (non-secure regions) for whole ddr regions */ + mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), + SGRF_DDR_RGN_BYPS); + else + /* cancel bypass for whole ddr regions */ + mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), + SGRF_DDR_RGN_NO_BYPS); +} + +/** + * There are 8 + 1 regions for DDR secure control: + * DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB + * DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7 + * + * DDR_RGN_0 - start address of the RGN0 + * DDR_RGN_8 - end address of the RGN0 + * DDR_RGN_1 - start address of the RGN1 + * DDR_RGN_9 - end address of the RGN1 + * ... + * DDR_RGN_7 - start address of the RGN7 + * DDR_RGN_15 - end address of the RGN7 + * DDR_RGN_16 - bit 0 ~ 7 is bitmap for RGN0~7 secure,0: disable, 1: enable + * bit 8 is setting for RGNx, the rest of the memory and region + * which excludes RGN0~7, 0: disable, 1: enable + * bit 9, the global secure configuration via bypass, 0: disable + * bypass, 1: enable bypass + * + * @rgn - the DDR regions 0 ~ 7 which are can be configured. + * The @st_mb and @ed_mb indicate the start and end addresses for which to set + * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the + * address range 0x0 ~ 0xfffff is secure. + * + * For example, if we would like to set the range [0, 32MB) is security via + * DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31. + */ +static void sgrf_ddr_rgn_config(uint32_t rgn, + uintptr_t st, uintptr_t ed) +{ + uintptr_t st_mb, ed_mb; + + assert(rgn <= 7); + assert(st < ed); + + /* check aligned 1MB */ + assert(st % SIZE_M(1) == 0); + assert(ed % SIZE_M(1) == 0); + + st_mb = st / SIZE_M(1); + ed_mb = ed / SIZE_M(1); + + /* set ddr region addr start */ + mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn), + BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0)); + + /* set ddr region addr end */ + mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8), + BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0)); + + mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), + BIT_WITH_WMSK(rgn)); +} + +void secure_watchdog_disable(void) +{ + /** + * Disable CA53 and CM0 wdt pclk + * BIT[8]: ca53 wdt pclk, 0: enable 1: disable + * BIT[10]: cm0 wdt pclk, 0: enable 1: disable + */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), + BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) | + BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT)); +} + +void secure_watchdog_enable(void) +{ + /** + * Enable CA53 and CM0 wdt pclk + * BIT[8]: ca53 wdt pclk, 0: enable 1: disable + * BIT[10]: cm0 wdt pclk, 0: enable 1: disable + */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), + WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) | + WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT)); +} + +void secure_timer_init(void) +{ + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); + + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); + + /* auto reload & enable the timer */ + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, + TIMER_EN | TIMER_FMODE); +} + +void secure_sgrf_init(void) +{ + /* security config for master */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), + REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), + REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), + REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); + + /* security config for slave */ + mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), + SGRF_PMU_SLV_S_CFGED | + SGRF_PMU_SLV_CRYPTO1_NS); + mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), + SGRF_SLV_S_WMSK | SGRF_PMUSRAM_S); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), + SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), + SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), + SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), + SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), + SGRF_SLV_S_WMSK | SGRF_INTSRAM_S); +} + +void secure_sgrf_ddr_rgn_init(void) +{ + sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE); + sgrf_ddr_rgn_global_bypass(0); +} diff --git a/plat/rockchip/rk3399/drivers/secure/secure.h b/plat/rockchip/rk3399/drivers/secure/secure.h new file mode 100644 index 00000000..12a875c8 --- /dev/null +++ b/plat/rockchip/rk3399/drivers/secure/secure.h @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ +#define __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ + +/************************************************** + * sgrf reg, offset + **************************************************/ +#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) +#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) +#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) +#define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\ + (n < 8 ? SGRF_SOC_CON3_7(n) :\ + SGRF_SOC_CON8_15(n))) + +#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) +#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) +#define SGRF_DDRRGN_CON0_16(n) ((n) * 4) +#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) + +/* All of master in ns */ +#define SGRF_SOC_ALLMST_NS 0xffff + +/* security config for slave */ +#define SGRF_SLV_S_WMSK 0xffff0000 +#define SGRF_SLV_S_ALL_NS 0x0 + +/* security config pmu slave ip */ +/* All of slaves is ns */ +#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) +/* slaves secure attr is configed */ +#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) +#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) + +#define SGRF_PMUSRAM_S BIT(8) + +#define SGRF_INTSRAM_S BIT(13) + +/* ddr region */ +#define SGRF_DDR_RGN_0_16_WMSK 0x0fff /* DDR RGN 0~16 size mask */ + +#define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */ +#define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */ + +/* All security of the DDR RGNs are bypass */ +#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) +/* All security of the DDR RGNs are not bypass */ +#define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(9) + +/* The MST access the ddr rgn n with secure attribution */ +#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) +/* bits[16:8]*/ +#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) + +#define SGRF_PMU_CON0 0x0c100 +#define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4) + +/************************************************** + * secure timer + **************************************************/ +/* chanal0~5 */ +#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) +/* chanal6~11 */ +#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) + + /* low 32 bits */ +#define TIMER_END_COUNT0 0x00 + /* high 32 bits */ +#define TIMER_END_COUNT1 0x04 + +#define TIMER_CURRENT_VALUE0 0x08 +#define TIMER_CURRENT_VALUE1 0x0C + + /* low 32 bits */ +#define TIMER_INIT_COUNT0 0x10 + /* high 32 bits */ +#define TIMER_INIT_COUNT1 0x14 + +#define TIMER_INTSTATUS 0x18 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 + +#define TIMER_FMODE (0x0 << 1) +#define TIMER_RMODE (0x1 << 1) + +/************************************************** + * secure WDT + **************************************************/ +#define PCLK_WDT_CA53_GATE_SHIFT 8 +#define PCLK_WDT_CM0_GATE_SHIFT 10 + +/* export secure operating APIs */ +void secure_watchdog_disable(void); +void secure_watchdog_enable(void); +void secure_timer_init(void); +void secure_sgrf_init(void); +void secure_sgrf_ddr_rgn_init(void); + +#endif /* __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ */ diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c index c769b73b..ec5470e4 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.c +++ b/plat/rockchip/rk3399/drivers/soc/soc.c @@ -29,19 +29,22 @@ */ #include <arch_helpers.h> +#include <assert.h> #include <debug.h> #include <delay_timer.h> +#include <dfs.h> +#include <dram.h> #include <mmio.h> +#include <m0_ctl.h> #include <platform_def.h> #include <plat_private.h> -#include <dram.h> #include <rk3399_def.h> -#include <rk3399m0.h> +#include <secure.h> #include <soc.h> /* Table of regions to map using the MMU. */ const mmap_region_t plat_rk_mmap[] = { - MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE, + MAP_REGION_FLAT(DEV_RNG0_BASE, DEV_RNG0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE), @@ -61,158 +64,8 @@ const unsigned char rockchip_power_domain_tree_desc[] = { PLATFORM_CLUSTER1_CORE_COUNT }; -void secure_timer_init(void) -{ - mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); - mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); - - mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); - mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); - - /* auto reload & enable the timer */ - mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, - TIMER_EN | TIMER_FMODE); -} - -void sgrf_init(void) -{ - /* security config for master */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), - SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), - SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), - SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); - - /* security config for slave */ - mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), - SGRF_PMU_SLV_S_CFGED | - SGRF_PMU_SLV_CRYPTO1_NS); - mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), - SGRF_PMU_SLV_CON1_CFG); - mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), - SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); - mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), - SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); - mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), - SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); - mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), - SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); - mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), - SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); - - /* security config for ddr memery */ - mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), - SGRF_DDR_RGN_BYPS); -} - -static void dma_secure_cfg(uint32_t secure) -{ - if (secure) { - /* rgn0 secure for dmac0 and dmac1 */ - mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), - SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ - SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ - ); - - /* set dmac0 boot, under secure state */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), - SGRF_DMAC_CFG_S); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), - SGRF_DMAC_CFG_S); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), - SGRF_DMAC_CFG_S); - - /* dmac0 soft reset */ - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - CRU_DMAC0_RST); - udelay(5); - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - CRU_DMAC0_RST_RLS); - - /* set dmac1 boot, under secure state */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), - SGRF_DMAC_CFG_S); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), - SGRF_DMAC_CFG_S); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), - SGRF_DMAC_CFG_S); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), - SGRF_DMAC_CFG_S); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), - SGRF_DMAC_CFG_S); - - /* dmac1 soft reset */ - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - CRU_DMAC1_RST); - udelay(5); - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - CRU_DMAC1_RST_RLS); - } else { - /* rgn non-secure for dmac0 and dmac1 */ - mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), - DMAC1_RGN_NS | DMAC0_RGN_NS); - - /* set dmac0 boot, under non-secure state */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), - DMAC0_BOOT_CFG_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), - DMAC0_BOOT_PERIPH_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), - DMAC0_BOOT_ADDR_NS); - - /* dmac0 soft reset */ - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - CRU_DMAC0_RST); - udelay(5); - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - CRU_DMAC0_RST_RLS); - - /* set dmac1 boot, under non-secure state */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), - DMAC1_BOOT_CFG_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), - DMAC1_BOOT_PERIPH_L_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), - DMAC1_BOOT_ADDR_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), - DMAC1_BOOT_PERIPH_H_NS); - mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), - DMAC1_BOOT_IRQ_NS); - - /* dmac1 soft reset */ - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - CRU_DMAC1_RST); - udelay(5); - mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), - CRU_DMAC1_RST_RLS); - } -} - -/* pll suspend */ -struct deepsleep_data_s slp_data; - -void secure_watchdog_disable(void) -{ - slp_data.sgrf_con[3] = mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(3)); - - /* disable CA53 wdt pclk */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3), - BITS_WITH_WMASK(WDT_CA53_DIS, WDT_CA53_1BIT_MASK, - PCLK_WDT_CA53_GATE_SHIFT)); - /* disable CM0 wdt pclk */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3), - BITS_WITH_WMASK(WDT_CM0_DIS, WDT_CM0_1BIT_MASK, - PCLK_WDT_CM0_GATE_SHIFT)); -} - -void secure_watchdog_restore(void) -{ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3), - slp_data.sgrf_con[3] | - WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) | - WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT)); -} +/* sleep data for pll suspend */ +static struct deepsleep_data_s slp_data; static void set_pll_slow_mode(uint32_t pll_id) { @@ -433,7 +286,7 @@ void soc_global_soft_reset_init(void) CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK); } -void __dead2 soc_global_soft_reset(void) +void __dead2 soc_global_soft_reset(void) { set_pll_slow_mode(VPLL_ID); set_pll_slow_mode(NPLL_ID); @@ -455,27 +308,14 @@ void __dead2 soc_global_soft_reset(void) ; } -static void soc_m0_init(void) -{ - /* secure config for pmu M0 */ - mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); - - /* set the execute address for M0 */ - mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), - BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff, - 0xffff, 0)); - mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), - BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf, - 0xf, 0)); -} - void plat_rockchip_soc_init(void) { secure_timer_init(); - dma_secure_cfg(0); - sgrf_init(); + secure_sgrf_init(); + secure_sgrf_ddr_rgn_init(); soc_global_soft_reset_init(); plat_rockchip_gpio_init(); - soc_m0_init(); + m0_init(); dram_init(); + dram_dfs_init(); } diff --git a/plat/rockchip/rk3399/drivers/soc/soc.h b/plat/rockchip/rk3399/drivers/soc/soc.h index 28590f2b..da16adbf 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.h +++ b/plat/rockchip/rk3399/drivers/soc/soc.h @@ -75,7 +75,6 @@ #define REG_SOC_WMSK 0xffff0000 #define CLK_GATE_MASK 0x01 -#define SGRF_SOC_COUNT 0x17 #define PMUCRU_GATE_COUNT 0x03 #define CRU_GATE_COUNT 0x23 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) @@ -108,13 +107,20 @@ enum glb_sft_reset { PMU_RST_NOT_BY_SFT = BIT(3), }; +struct pll_div { + uint32_t mhz; + uint32_t refdiv; + uint32_t fbdiv; + uint32_t postdiv1; + uint32_t postdiv2; + uint32_t frac; + uint32_t freq; +}; + struct deepsleep_data_s { uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; - uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT]; - uint32_t cru_clksel_con[CRU_CLKSEL_COUNT]; uint32_t cru_gate_con[CRU_GATE_COUNT]; uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT]; - uint32_t sgrf_con[SGRF_SOC_COUNT]; }; /************************************************** @@ -147,50 +153,6 @@ struct deepsleep_data_s { #define CYCL_32K_CNT_MS(ms) (ms * 32) /************************************************** - * secure timer - **************************************************/ - -/* chanal0~5 */ -#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) -/* chanal6~11 */ -#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) - - /* low 32 bits */ -#define TIMER_END_COUNT0 0x00 - /* high 32 bits */ -#define TIMER_END_COUNT1 0x04 - -#define TIMER_CURRENT_VALUE0 0x08 -#define TIMER_CURRENT_VALUE1 0x0C - - /* low 32 bits */ -#define TIMER_INIT_COUNT0 0x10 - /* high 32 bits */ -#define TIMER_INIT_COUNT1 0x14 - -#define TIMER_INTSTATUS 0x18 -#define TIMER_CONTROL_REG 0x1c - -#define TIMER_EN 0x1 - -#define TIMER_FMODE (0x0 << 1) -#define TIMER_RMODE (0x1 << 1) - -/************************************************** - * secure WDT - **************************************************/ -#define WDT_CM0_EN 0x0 -#define WDT_CM0_DIS 0x1 -#define WDT_CA53_EN 0x0 -#define WDT_CA53_DIS 0x1 - -#define PCLK_WDT_CA53_GATE_SHIFT 8 -#define PCLK_WDT_CM0_GATE_SHIFT 10 - -#define WDT_CA53_1BIT_MASK 0x1 -#define WDT_CM0_1BIT_MASK 0x1 - -/************************************************** * cru reg, offset **************************************************/ #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) @@ -231,63 +193,6 @@ struct deepsleep_data_s { #define PCLK_GPIO0_GATE_SHIFT 3 #define PCLK_GPIO1_GATE_SHIFT 4 -/************************************************** - * sgrf reg, offset - **************************************************/ -#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) -#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) -#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) -#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) -#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) -#define SGRF_DDRRGN_CON0_16(n) ((n) * 4) -#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) - -/* security config for master */ -#define SGRF_SOC_CON_WMSK 0xffff0000 -/* All of master in ns */ -#define SGRF_SOC_ALLMST_NS 0xffff - -/* security config for slave */ -#define SGRF_SLV_S_WMSK 0xffff0000 -#define SGRF_SLV_S_ALL_NS 0x0 - -/* security config pmu slave ip */ -/* All of slaves is ns */ -#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) -/* slaves secure attr is configed */ -#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) -#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) - -#define SGRF_PMUSRAM_S BIT(8) - -#define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \ - SGRF_PMUSRAM_S) -/* ddr region */ -#define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */ -#define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */ -#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */ - -/* The MST access the ddr rgn n with secure attribution */ -#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) -/* bits[16:8]*/ -#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) - -/* dmac to periph s or ns*/ -#define SGRF_DMAC_CFG_S 0xffff0000 - -#define DMAC1_RGN_NS 0xff000000 -#define DMAC0_RGN_NS 0x00ff0000 - -#define DMAC0_BOOT_CFG_NS 0xfffffff8 -#define DMAC0_BOOT_PERIPH_NS 0xffff0fff -#define DMAC0_BOOT_ADDR_NS 0xffff0000 - -#define DMAC1_BOOT_CFG_NS 0xffff0008 -#define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff -#define DMAC1_BOOT_ADDR_NS 0xffff0000 -#define DMAC1_BOOT_PERIPH_H_NS 0xffffffff -#define DMAC1_BOOT_IRQ_NS 0xffffffff - #define CPU_BOOT_ADDR_WMASK 0xffff0000 #define CPU_BOOT_ADDR_ALIGN 16 @@ -312,17 +217,13 @@ struct deepsleep_data_s { #define GRF_DDRC0_CON1 0xe384 #define GRF_DDRC1_CON0 0xe388 #define GRF_DDRC1_CON1 0xe38c +#define GRF_SOC_CON_BASE 0xe200 +#define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4) #define PMUCRU_CLKSEL_CON0 0x0080 #define PMUCRU_CLKGATE_CON2 0x0108 #define PMUCRU_SOFTRST_CON0 0x0110 #define PMUCRU_GATEDIS_CON0 0x0130 - -#define SGRF_SOC_CON6 0x0e018 -#define SGRF_PERILP_CON0 0x08100 -#define SGRF_PERILP_CON(n) (SGRF_PERILP_CON0 + (n) * 4) -#define SGRF_PMU_CON0 0x0c100 -#define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4) #define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4) /* @@ -346,10 +247,8 @@ static inline void pmu_sgrf_rst_hld(void) CRU_PMU_SGRF_RST_HOLD); } -/* funciton*/ +/* export related and operating SoC APIs */ void __dead2 soc_global_soft_reset(void); -void secure_watchdog_disable(); -void secure_watchdog_restore(); void disable_dvfs_plls(void); void disable_nodvfs_plls(void); void enable_dvfs_plls(void); @@ -360,5 +259,5 @@ void restore_dpll(void); void clk_gate_con_save(void); void clk_gate_con_disable(void); void clk_gate_con_restore(void); -void sgrf_init(void); + #endif /* __SOC_H__ */ diff --git a/plat/rockchip/rk3399/include/addressmap.h b/plat/rockchip/rk3399/include/addressmap.h new file mode 100644 index 00000000..da514e7e --- /dev/null +++ b/plat/rockchip/rk3399/include/addressmap.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__ +#define __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__ + +#include <addressmap_shared.h> + +/* Registers base address */ +#define MMIO_BASE 0xF8000000 + +/* Aggregate of all devices in the first GB */ +#define DEV_RNG0_BASE MMIO_BASE +#define DEV_RNG0_SIZE SIZE_M(125) + +#endif /* __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__ */ diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h index 5ccc5323..da0bb180 100644 --- a/plat/rockchip/rk3399/include/platform_def.h +++ b/plat/rockchip/rk3399/include/platform_def.h @@ -32,6 +32,7 @@ #define __PLATFORM_DEF_H__ #include <arch.h> +#include <bl31_param.h> #include <common_def.h> #include <rk3399_def.h> @@ -89,22 +90,6 @@ #define PLAT_MAX_OFF_STATE 2 /******************************************************************************* - * Platform memory map related constants - ******************************************************************************/ -/* TF txet, ro, rw, Size: 512KB */ -#define TZRAM_BASE (0x0) -#define TZRAM_SIZE (0x80000) - -/******************************************************************************* - * BL31 specific defines. - ******************************************************************************/ -/* - * Put BL3-1 at the top of the Trusted RAM - */ -#define BL31_BASE (TZRAM_BASE + 0x10000) -#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) - -/******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ #define ADDR_SPACE_SIZE (1ull << 32) @@ -138,7 +123,7 @@ #define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS #define PLAT_RK_G0_IRQS RK3399_G0_IRQS -#define PLAT_RK_UART_BASE RK3399_UART2_BASE +#define PLAT_RK_UART_BASE UART2_BASE #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE diff --git a/plat/rockchip/rk3399/include/shared/addressmap_shared.h b/plat/rockchip/rk3399/include/shared/addressmap_shared.h new file mode 100644 index 00000000..7f6c075c --- /dev/null +++ b/plat/rockchip/rk3399/include/shared/addressmap_shared.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ +#define __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ + +#define SIZE_K(n) ((n) * 1024) +#define SIZE_M(n) ((n) * 1024 * 1024) + +/* + * The parts of the shared defined registers address with AP and M0, + * let's note and mark the previous defines like this: + */ +#define GIC500_BASE (MMIO_BASE + 0x06E00000) +#define UART0_BASE (MMIO_BASE + 0x07180000) +#define UART1_BASE (MMIO_BASE + 0x07190000) +#define UART2_BASE (MMIO_BASE + 0x071A0000) +#define UART3_BASE (MMIO_BASE + 0x071B0000) + +#define PMU_BASE (MMIO_BASE + 0x07310000) +#define PMUGRF_BASE (MMIO_BASE + 0x07320000) +#define SGRF_BASE (MMIO_BASE + 0x07330000) +#define PMUSRAM_BASE (MMIO_BASE + 0x073B0000) +#define PWM_BASE (MMIO_BASE + 0x07420000) + +#define CIC_BASE (MMIO_BASE + 0x07620000) +#define PD_BUS0_BASE (MMIO_BASE + 0x07650000) +#define DCF_BASE (MMIO_BASE + 0x076A0000) +#define GPIO0_BASE (MMIO_BASE + 0x07720000) +#define GPIO1_BASE (MMIO_BASE + 0x07730000) +#define PMUCRU_BASE (MMIO_BASE + 0x07750000) +#define CRU_BASE (MMIO_BASE + 0x07760000) +#define GRF_BASE (MMIO_BASE + 0x07770000) +#define GPIO2_BASE (MMIO_BASE + 0x07780000) +#define GPIO3_BASE (MMIO_BASE + 0x07788000) +#define GPIO4_BASE (MMIO_BASE + 0x07790000) +#define STIME_BASE (MMIO_BASE + 0x07860000) +#define SRAM_BASE (MMIO_BASE + 0x078C0000) +#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000) +#define DDRC0_BASE (MMIO_BASE + 0x07A80000) +#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x07A84000) +#define DDRC1_BASE (MMIO_BASE + 0x07A88000) +#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x07A8C000) +#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x07A90000) +#define CCI500_BASE (MMIO_BASE + 0x07B00000) +#define COLD_BOOT_BASE (MMIO_BASE + 0x07FF0000) + +/* Registers size */ +#define GIC500_SIZE SIZE_M(2) +#define UART0_SIZE SIZE_K(64) +#define UART1_SIZE SIZE_K(64) +#define UART2_SIZE SIZE_K(64) +#define UART3_SIZE SIZE_K(64) +#define PMU_SIZE SIZE_K(64) +#define PMUGRF_SIZE SIZE_K(64) +#define SGRF_SIZE SIZE_K(64) +#define PMUSRAM_SIZE SIZE_K(64) +#define PMUSRAM_RSIZE SIZE_K(8) +#define PWM_SIZE SIZE_K(64) +#define CIC_SIZE SIZE_K(4) +#define DCF_SIZE SIZE_K(4) +#define GPIO0_SIZE SIZE_K(64) +#define GPIO1_SIZE SIZE_K(64) +#define PMUCRU_SIZE SIZE_K(64) +#define CRU_SIZE SIZE_K(64) +#define GRF_SIZE SIZE_K(64) +#define GPIO2_SIZE SIZE_K(32) +#define GPIO3_SIZE SIZE_K(32) +#define GPIO4_SIZE SIZE_K(32) +#define STIME_SIZE SIZE_K(64) +#define SRAM_SIZE SIZE_K(192) +#define SERVICE_NOC_0_SIZE SIZE_K(192) +#define DDRC0_SIZE SIZE_K(32) +#define SERVICE_NOC_1_SIZE SIZE_K(16) +#define DDRC1_SIZE SIZE_K(32) +#define SERVICE_NOC_2_SIZE SIZE_K(16) +#define SERVICE_NOC_3_SIZE SIZE_K(448) +#define CCI500_SIZE SIZE_M(1) +#define PD_BUS0_SIZE SIZE_K(448) + +/* DDR Registers address */ +#define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000) +#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) + +#define PI_OFFSET 0x800 +#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) +#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) + +#define PHY_OFFSET 0x2000 +#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET) +#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) + +#define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000) + +#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ */ diff --git a/plat/rockchip/rk3399/include/shared/bl31_param.h b/plat/rockchip/rk3399/include/shared/bl31_param.h new file mode 100644 index 00000000..fd53af4b --- /dev/null +++ b/plat/rockchip/rk3399/include/shared/bl31_param.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_ROCKCHIP_RK3399_INCLUDE_SHARED_BL31_PARAM_H__ +#define __PLAT_ROCKCHIP_RK3399_INCLUDE_SHARED_BL31_PARAM_H__ + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +/* TF text, ro, rw, Size: 1MB */ +#define TZRAM_BASE (0x0) +#define TZRAM_SIZE (0x100000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted RAM + */ +#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +#endif /*__PLAT_ROCKCHIP_RK3399_INCLUDE_SHARED_BL31_PARAM_H__*/ diff --git a/plat/rockchip/rk3399/include/shared/dram_regs.h b/plat/rockchip/rk3399/include/shared/dram_regs.h new file mode 100644 index 00000000..21af8a5d --- /dev/null +++ b/plat/rockchip/rk3399/include/shared/dram_regs.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DRAM_REGS_H__ +#define __DRAM_REGS_H__ + +#define CTL_REG_NUM 332 +#define PHY_REG_NUM 959 +#define PI_REG_NUM 200 + +#define MSCH_ID_COREID 0x0 +#define MSCH_ID_REVISIONID 0x4 +#define MSCH_DEVICECONF 0x8 +#define MSCH_DEVICESIZE 0xc +#define MSCH_DDRTIMINGA0 0x10 +#define MSCH_DDRTIMINGB0 0x14 +#define MSCH_DDRTIMINGC0 0x18 +#define MSCH_DEVTODEV0 0x1c +#define MSCH_DDRMODE 0x110 +#define MSCH_AGINGX0 0x1000 + +#define CIC_CTRL0 0x0 +#define CIC_CTRL1 0x4 +#define CIC_IDLE_TH 0x8 +#define CIC_CG_WAIT_TH 0xc +#define CIC_STATUS0 0x10 +#define CIC_STATUS1 0x14 +#define CIC_CTRL2 0x18 +#define CIC_CTRL3 0x1c +#define CIC_CTRL4 0x20 + +/* DENALI_CTL_00 */ +#define START 1 + +/* DENALI_CTL_68 */ +#define PWRUP_SREFRESH_EXIT (1 << 16) + +/* DENALI_CTL_274 */ +#define MEM_RST_VALID 1 + +#define PHY_DRV_ODT_Hi_Z 0x0 +#define PHY_DRV_ODT_240 0x1 +#define PHY_DRV_ODT_120 0x8 +#define PHY_DRV_ODT_80 0x9 +#define PHY_DRV_ODT_60 0xc +#define PHY_DRV_ODT_48 0xd +#define PHY_DRV_ODT_40 0xe +#define PHY_DRV_ODT_34_3 0xf + +/* + * sys_reg bitfield struct + * [31] row_3_4_ch1 + * [30] row_3_4_ch0 + * [29:28] chinfo + * [27] rank_ch1 + * [26:25] col_ch1 + * [24] bk_ch1 + * [23:22] cs0_row_ch1 + * [21:20] cs1_row_ch1 + * [19:18] bw_ch1 + * [17:16] dbw_ch1; + * [15:13] ddrtype + * [12] channelnum + * [11] rank_ch0 + * [10:9] col_ch0 + * [8] bk_ch0 + * [7:6] cs0_row_ch0 + * [5:4] cs1_row_ch0 + * [3:2] bw_ch0 + * [1:0] dbw_ch0 + */ +#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) +#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) +#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) +#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) +#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) +#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) +#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) +#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) +#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) +#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) +#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) +#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3)) +#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16)) +#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1)) +#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16)) +#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3)) +#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16)) +#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3)) +#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16)) +#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3)) +#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16)) +#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3)) +#define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \ + (0x1f<<(10+16))|((n)<<10)) + +#endif /* __DRAM_REGS_H__ */ diff --git a/plat/rockchip/rk3399/include/shared/m0_param.h b/plat/rockchip/rk3399/include/shared/m0_param.h new file mode 100644 index 00000000..46755e1e --- /dev/null +++ b/plat/rockchip/rk3399/include/shared/m0_param.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __M0_PARAM_H__ +#define __M0_PARAM_H__ + +#ifndef __LINKER__ +enum { + M0_FUNC_SUSPEND = 0, + M0_FUNC_DRAM = 1, +}; +#endif /* __LINKER__ */ + +#define PARAM_ADDR 0xc0 + +#define PARAM_M0_FUNC 0x00 +#define PARAM_DRAM_FREQ 0x04 +#define PARAM_DPLL_CON0 0x08 +#define PARAM_DPLL_CON1 0x0c +#define PARAM_DPLL_CON2 0x10 +#define PARAM_DPLL_CON3 0x14 +#define PARAM_DPLL_CON4 0x18 +#define PARAM_DPLL_CON5 0x1c +#define PARAM_FREQ_SELECT 0x20 +#define PARAM_M0_DONE 0x24 +#define PARAM_M0_SIZE 0x28 +#define M0_DONE_FLAG 0xf59ec39a + +#endif /*__M0_PARAM_H__*/ diff --git a/plat/rockchip/rk3399/include/shared/misc_regs.h b/plat/rockchip/rk3399/include/shared/misc_regs.h new file mode 100644 index 00000000..3e0a3623 --- /dev/null +++ b/plat/rockchip/rk3399/include/shared/misc_regs.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ +#define __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ + +/* CRU */ +#define CRU_DPLL_CON0 0x40 +#define CRU_DPLL_CON1 0x44 +#define CRU_DPLL_CON2 0x48 +#define CRU_DPLL_CON3 0x4c +#define CRU_DPLL_CON4 0x50 +#define CRU_DPLL_CON5 0x54 + +/* CRU_PLL_CON3 */ +#define PLL_SLOW_MODE 0 +#define PLL_NORMAL_MODE 1 +#define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) +#define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) + +/* PMU CRU */ +#define PMU_CRU_GATEDIS_CON0 0x130 + +#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ */ diff --git a/plat/rockchip/rk3399/include/shared/pmu_bits.h b/plat/rockchip/rk3399/include/shared/pmu_bits.h new file mode 100644 index 00000000..59d7107c --- /dev/null +++ b/plat/rockchip/rk3399/include/shared/pmu_bits.h @@ -0,0 +1,721 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMU_BITS_H__ +#define __PMU_BITS_H__ + +enum pmu_powerdomain_id { + PD_CPUL0 = 0, + PD_CPUL1, + PD_CPUL2, + PD_CPUL3, + PD_CPUB0, + PD_CPUB1, + PD_SCUL, + PD_SCUB, + PD_TCPD0, + PD_TCPD1, + PD_CCI, + PD_PERILP, + PD_PERIHP, + PD_CENTER, + PD_VIO, + PD_GPU, + PD_VCODEC, + PD_VDU, + PD_RGA, + PD_IEP, + PD_VO, + PD_ISP0 = 22, + PD_ISP1, + PD_HDCP, + PD_GMAC, + PD_EMMC, + PD_USB3, + PD_EDP, + PD_GIC, + PD_SD, + PD_SDIOAUDIO, + PD_END +}; + +enum powerdomain_state { + PMU_POWER_ON = 0, + PMU_POWER_OFF, +}; + +enum pmu_bus_id { + BUS_ID_GPU = 0, + BUS_ID_PERILP, + BUS_ID_PERIHP, + BUS_ID_VCODEC, + BUS_ID_VDU, + BUS_ID_RGA, + BUS_ID_IEP, + BUS_ID_VOPB, + BUS_ID_VOPL, + BUS_ID_ISP0, + BUS_ID_ISP1, + BUS_ID_HDCP, + BUS_ID_USB3, + BUS_ID_PERILPM0, + BUS_ID_CENTER, + BUS_ID_CCIM0, + BUS_ID_CCIM1, + BUS_ID_VIO, + BUS_ID_MSCH0, + BUS_ID_MSCH1, + BUS_ID_ALIVE, + BUS_ID_PMU, + BUS_ID_EDP, + BUS_ID_GMAC, + BUS_ID_EMMC, + BUS_ID_CENTER1, + BUS_ID_PMUM0, + BUS_ID_GIC, + BUS_ID_SD, + BUS_ID_SDIOAUDIO, +}; + +enum pmu_bus_state { + BUS_ACTIVE, + BUS_IDLE, +}; + +/* pmu_cpuapm bit */ +enum pmu_cores_pm_by_wfi { + core_pm_en = 0, + core_pm_int_wakeup_en, + core_pm_resv, + core_pm_sft_wakeup_en +}; + +enum pmu_wkup_cfg0 { + PMU_GPIO0A_POSE_WKUP_EN = 0, + PMU_GPIO0B_POSE_WKUP_EN = 8, + PMU_GPIO0C_POSE_WKUP_EN = 16, + PMU_GPIO0D_POSE_WKUP_EN = 24, +}; + +enum pmu_wkup_cfg1 { + PMU_GPIO0A_NEGEDGE_WKUP_EN = 0, + PMU_GPIO0B_NEGEDGE_WKUP_EN = 7, + PMU_GPIO0C_NEGEDGE_WKUP_EN = 16, + PMU_GPIO0D_NEGEDGE_WKUP_EN = 24, +}; + +enum pmu_wkup_cfg2 { + PMU_GPIO1A_POSE_WKUP_EN = 0, + PMU_GPIO1B_POSE_WKUP_EN = 7, + PMU_GPIO1C_POSE_WKUP_EN = 16, + PMU_GPIO1D_POSE_WKUP_EN = 24, +}; + +enum pmu_wkup_cfg3 { + PMU_GPIO1A_NEGEDGE_WKUP_EN = 0, + PMU_GPIO1B_NEGEDGE_WKUP_EN = 7, + PMU_GPIO1C_NEGEDGE_WKUP_EN = 16, + PMU_GPIO1D_NEGEDGE_WKUP_EN = 24, +}; + +/* pmu_wkup_cfg4 */ +enum pmu_wkup_cfg4 { + PMU_CLUSTER_L_WKUP_EN = 0, + PMU_CLUSTER_B_WKUP_EN, + PMU_GPIO_WKUP_EN, + PMU_SDIO_WKUP_EN, + + PMU_SDMMC_WKUP_EN, + PMU_TIMER_WKUP_EN = 6, + PMU_USBDEV_WKUP_EN, + + PMU_SFT_WKUP_EN, + PMU_M0_WDT_WKUP_EN, + PMU_TIMEOUT_WKUP_EN, + PMU_PWM_WKUP_EN, + + PMU_PCIE_WKUP_EN = 13, +}; + +enum pmu_pwrdn_con { + PMU_A53_L0_PWRDWN_EN = 0, + PMU_A53_L1_PWRDWN_EN, + PMU_A53_L2_PWRDWN_EN, + PMU_A53_L3_PWRDWN_EN, + + PMU_A72_B0_PWRDWN_EN, + PMU_A72_B1_PWRDWN_EN, + PMU_SCU_L_PWRDWN_EN, + PMU_SCU_B_PWRDWN_EN, + + PMU_TCPD0_PWRDWN_EN, + PMU_TCPD1_PWRDWN_EN, + PMU_CCI_PWRDWN_EN, + PMU_PERILP_PWRDWN_EN, + + PMU_PERIHP_PWRDWN_EN, + PMU_CENTER_PWRDWN_EN, + PMU_VIO_PWRDWN_EN, + PMU_GPU_PWRDWN_EN, + + PMU_VCODEC_PWRDWN_EN, + PMU_VDU_PWRDWN_EN, + PMU_RGA_PWRDWN_EN, + PMU_IEP_PWRDWN_EN, + + PMU_VO_PWRDWN_EN, + PMU_ISP0_PWRDWN_EN = 22, + PMU_ISP1_PWRDWN_EN, + + PMU_HDCP_PWRDWN_EN, + PMU_GMAC_PWRDWN_EN, + PMU_EMMC_PWRDWN_EN, + PMU_USB3_PWRDWN_EN, + + PMU_EDP_PWRDWN_EN, + PMU_GIC_PWRDWN_EN, + PMU_SD_PWRDWN_EN, + PMU_SDIOAUDIO_PWRDWN_EN, +}; + +enum pmu_pwrdn_st { + PMU_A53_L0_PWRDWN_ST = 0, + PMU_A53_L1_PWRDWN_ST, + PMU_A53_L2_PWRDWN_ST, + PMU_A53_L3_PWRDWN_ST, + + PMU_A72_B0_PWRDWN_ST, + PMU_A72_B1_PWRDWN_ST, + PMU_SCU_L_PWRDWN_ST, + PMU_SCU_B_PWRDWN_ST, + + PMU_TCPD0_PWRDWN_ST, + PMU_TCPD1_PWRDWN_ST, + PMU_CCI_PWRDWN_ST, + PMU_PERILP_PWRDWN_ST, + + PMU_PERIHP_PWRDWN_ST, + PMU_CENTER_PWRDWN_ST, + PMU_VIO_PWRDWN_ST, + PMU_GPU_PWRDWN_ST, + + PMU_VCODEC_PWRDWN_ST, + PMU_VDU_PWRDWN_ST, + PMU_RGA_PWRDWN_ST, + PMU_IEP_PWRDWN_ST, + + PMU_VO_PWRDWN_ST, + PMU_ISP0_PWRDWN_ST = 22, + PMU_ISP1_PWRDWN_ST, + + PMU_HDCP_PWRDWN_ST, + PMU_GMAC_PWRDWN_ST, + PMU_EMMC_PWRDWN_ST, + PMU_USB3_PWRDWN_ST, + + PMU_EDP_PWRDWN_ST, + PMU_GIC_PWRDWN_ST, + PMU_SD_PWRDWN_ST, + PMU_SDIOAUDIO_PWRDWN_ST, + +}; + +enum pmu_pll_con { + PMU_PLL_PD_CFG = 0, + PMU_SFT_PLL_PD = 8, +}; + +enum pmu_pwermode_con { + PMU_PWR_MODE_EN = 0, + PMU_WKUP_RST_EN, + PMU_INPUT_CLAMP_EN, + PMU_OSC_DIS, + + PMU_ALIVE_USE_LF, + PMU_PMU_USE_LF, + PMU_POWER_OFF_REQ_CFG, + PMU_CHIP_PD_EN, + + PMU_PLL_PD_EN, + PMU_CPU0_PD_EN, + PMU_L2_FLUSH_EN, + PMU_L2_IDLE_EN, + + PMU_SCU_PD_EN, + PMU_CCI_PD_EN, + PMU_PERILP_PD_EN, + PMU_CENTER_PD_EN, + + PMU_SREF0_ENTER_EN, + PMU_DDRC0_GATING_EN, + PMU_DDRIO0_RET_EN, + PMU_DDRIO0_RET_DE_REQ, + + PMU_SREF1_ENTER_EN, + PMU_DDRC1_GATING_EN, + PMU_DDRIO1_RET_EN, + PMU_DDRIO1_RET_DE_REQ, + + PMU_CLK_CENTER_SRC_GATE_EN = 26, + PMU_CLK_PERILP_SRC_GATE_EN, + + PMU_CLK_CORE_SRC_GATE_EN, + PMU_DDRIO_RET_HW_DE_REQ, + PMU_SLP_OUTPUT_CFG, + PMU_MAIN_CLUSTER, +}; + +enum pmu_sft_con { + PMU_WKUP_SFT = 0, + PMU_INPUT_CLAMP_CFG, + PMU_OSC_DIS_CFG, + PMU_PMU_LF_EN_CFG, + + PMU_ALIVE_LF_EN_CFG, + PMU_24M_EN_CFG, + PMU_DBG_PWRUP_L0_CFG, + PMU_WKUP_SFT_M0, + + PMU_DDRCTL0_C_SYSREQ_CFG, + PMU_DDR0_IO_RET_CFG, + + PMU_DDRCTL1_C_SYSREQ_CFG = 12, + PMU_DDR1_IO_RET_CFG, + DBG_PWRUP_B0_CFG = 15, + + DBG_NOPWERDWN_L0_EN, + DBG_NOPWERDWN_L1_EN, + DBG_NOPWERDWN_L2_EN, + DBG_NOPWERDWN_L3_EN, + + DBG_PWRUP_REQ_L_EN = 20, + CLUSTER_L_CLK_SRC_GATING_CFG, + L2_FLUSH_REQ_CLUSTER_L, + ACINACTM_CLUSTER_L_CFG, + + DBG_NO_PWERDWN_B0_EN, + DBG_NO_PWERDWN_B1_EN, + + DBG_PWRUP_REQ_B_EN = 28, + CLUSTER_B_CLK_SRC_GATING_CFG, + L2_FLUSH_REQ_CLUSTER_B, + ACINACTM_CLUSTER_B_CFG, +}; + +enum pmu_int_con { + PMU_PMU_INT_EN = 0, + PMU_PWRMD_WKUP_INT_EN, + PMU_WKUP_GPIO0_NEG_INT_EN, + PMU_WKUP_GPIO0_POS_INT_EN, + PMU_WKUP_GPIO1_NEG_INT_EN, + PMU_WKUP_GPIO1_POS_INT_EN, +}; + +enum pmu_int_st { + PMU_PWRMD_WKUP_INT_ST = 1, + PMU_WKUP_GPIO0_NEG_INT_ST, + PMU_WKUP_GPIO0_POS_INT_ST, + PMU_WKUP_GPIO1_NEG_INT_ST, + PMU_WKUP_GPIO1_POS_INT_ST, +}; + +enum pmu_gpio0_pos_int_con { + PMU_GPIO0A_POS_INT_EN = 0, + PMU_GPIO0B_POS_INT_EN = 8, + PMU_GPIO0C_POS_INT_EN = 16, + PMU_GPIO0D_POS_INT_EN = 24, +}; + +enum pmu_gpio0_neg_int_con { + PMU_GPIO0A_NEG_INT_EN = 0, + PMU_GPIO0B_NEG_INT_EN = 8, + PMU_GPIO0C_NEG_INT_EN = 16, + PMU_GPIO0D_NEG_INT_EN = 24, +}; + +enum pmu_gpio1_pos_int_con { + PMU_GPIO1A_POS_INT_EN = 0, + PMU_GPIO1B_POS_INT_EN = 8, + PMU_GPIO1C_POS_INT_EN = 16, + PMU_GPIO1D_POS_INT_EN = 24, +}; + +enum pmu_gpio1_neg_int_con { + PMU_GPIO1A_NEG_INT_EN = 0, + PMU_GPIO1B_NEG_INT_EN = 8, + PMU_GPIO1C_NEG_INT_EN = 16, + PMU_GPIO1D_NEG_INT_EN = 24, +}; + +enum pmu_gpio0_pos_int_st { + PMU_GPIO0A_POS_INT_ST = 0, + PMU_GPIO0B_POS_INT_ST = 8, + PMU_GPIO0C_POS_INT_ST = 16, + PMU_GPIO0D_POS_INT_ST = 24, +}; + +enum pmu_gpio0_neg_int_st { + PMU_GPIO0A_NEG_INT_ST = 0, + PMU_GPIO0B_NEG_INT_ST = 8, + PMU_GPIO0C_NEG_INT_ST = 16, + PMU_GPIO0D_NEG_INT_ST = 24, +}; + +enum pmu_gpio1_pos_int_st { + PMU_GPIO1A_POS_INT_ST = 0, + PMU_GPIO1B_POS_INT_ST = 8, + PMU_GPIO1C_POS_INT_ST = 16, + PMU_GPIO1D_POS_INT_ST = 24, +}; + +enum pmu_gpio1_neg_int_st { + PMU_GPIO1A_NEG_INT_ST = 0, + PMU_GPIO1B_NEG_INT_ST = 8, + PMU_GPIO1C_NEG_INT_ST = 16, + PMU_GPIO1D_NEG_INT_ST = 24, +}; + +/* pmu power down configure register 0x0050 */ +enum pmu_pwrdn_inten { + PMU_A53_L0_PWR_SWITCH_INT_EN = 0, + PMU_A53_L1_PWR_SWITCH_INT_EN, + PMU_A53_L2_PWR_SWITCH_INT_EN, + PMU_A53_L3_PWR_SWITCH_INT_EN, + + PMU_A72_B0_PWR_SWITCH_INT_EN, + PMU_A72_B1_PWR_SWITCH_INT_EN, + PMU_SCU_L_PWR_SWITCH_INT_EN, + PMU_SCU_B_PWR_SWITCH_INT_EN, + + PMU_TCPD0_PWR_SWITCH_INT_EN, + PMU_TCPD1_PWR_SWITCH_INT_EN, + PMU_CCI_PWR_SWITCH_INT_EN, + PMU_PERILP_PWR_SWITCH_INT_EN, + + PMU_PERIHP_PWR_SWITCH_INT_EN, + PMU_CENTER_PWR_SWITCH_INT_EN, + PMU_VIO_PWR_SWITCH_INT_EN, + PMU_GPU_PWR_SWITCH_INT_EN, + + PMU_VCODEC_PWR_SWITCH_INT_EN, + PMU_VDU_PWR_SWITCH_INT_EN, + PMU_RGA_PWR_SWITCH_INT_EN, + PMU_IEP_PWR_SWITCH_INT_EN, + + PMU_VO_PWR_SWITCH_INT_EN, + PMU_ISP0_PWR_SWITCH_INT_EN = 22, + PMU_ISP1_PWR_SWITCH_INT_EN, + + PMU_HDCP_PWR_SWITCH_INT_EN, + PMU_GMAC_PWR_SWITCH_INT_EN, + PMU_EMMC_PWR_SWITCH_INT_EN, + PMU_USB3_PWR_SWITCH_INT_EN, + + PMU_EDP_PWR_SWITCH_INT_EN, + PMU_GIC_PWR_SWITCH_INT_EN, + PMU_SD_PWR_SWITCH_INT_EN, + PMU_SDIOAUDIO_PWR_SWITCH_INT_EN, +}; + +enum pmu_wkup_status { + PMU_WKUP_BY_CLSTER_L_INT = 0, + PMU_WKUP_BY_CLSTER_b_INT, + PMU_WKUP_BY_GPIO_INT, + PMU_WKUP_BY_SDIO_DET, + + PMU_WKUP_BY_SDMMC_DET, + PMU_WKUP_BY_TIMER = 6, + PMU_WKUP_BY_USBDEV_DET, + + PMU_WKUP_BY_M0_SFT, + PMU_WKUP_BY_M0_WDT_INT, + PMU_WKUP_BY_TIMEOUT, + PMU_WKUP_BY_PWM, + + PMU_WKUP_BY_PCIE = 13, +}; + +enum pmu_bus_clr { + PMU_CLR_GPU = 0, + PMU_CLR_PERILP, + PMU_CLR_PERIHP, + PMU_CLR_VCODEC, + + PMU_CLR_VDU, + PMU_CLR_RGA, + PMU_CLR_IEP, + PMU_CLR_VOPB, + + PMU_CLR_VOPL, + PMU_CLR_ISP0, + PMU_CLR_ISP1, + PMU_CLR_HDCP, + + PMU_CLR_USB3, + PMU_CLR_PERILPM0, + PMU_CLR_CENTER, + PMU_CLR_CCIM1, + + PMU_CLR_CCIM0, + PMU_CLR_VIO, + PMU_CLR_MSCH0, + PMU_CLR_MSCH1, + + PMU_CLR_ALIVE, + PMU_CLR_PMU, + PMU_CLR_EDP, + PMU_CLR_GMAC, + + PMU_CLR_EMMC, + PMU_CLR_CENTER1, + PMU_CLR_PMUM0, + PMU_CLR_GIC, + + PMU_CLR_SD, + PMU_CLR_SDIOAUDIO, +}; + +/* PMU bus idle request register */ +enum pmu_bus_idle_req { + PMU_IDLE_REQ_GPU = 0, + PMU_IDLE_REQ_PERILP, + PMU_IDLE_REQ_PERIHP, + PMU_IDLE_REQ_VCODEC, + + PMU_IDLE_REQ_VDU, + PMU_IDLE_REQ_RGA, + PMU_IDLE_REQ_IEP, + PMU_IDLE_REQ_VOPB, + + PMU_IDLE_REQ_VOPL, + PMU_IDLE_REQ_ISP0, + PMU_IDLE_REQ_ISP1, + PMU_IDLE_REQ_HDCP, + + PMU_IDLE_REQ_USB3, + PMU_IDLE_REQ_PERILPM0, + PMU_IDLE_REQ_CENTER, + PMU_IDLE_REQ_CCIM0, + + PMU_IDLE_REQ_CCIM1, + PMU_IDLE_REQ_VIO, + PMU_IDLE_REQ_MSCH0, + PMU_IDLE_REQ_MSCH1, + + PMU_IDLE_REQ_ALIVE, + PMU_IDLE_REQ_PMU, + PMU_IDLE_REQ_EDP, + PMU_IDLE_REQ_GMAC, + + PMU_IDLE_REQ_EMMC, + PMU_IDLE_REQ_CENTER1, + PMU_IDLE_REQ_PMUM0, + PMU_IDLE_REQ_GIC, + + PMU_IDLE_REQ_SD, + PMU_IDLE_REQ_SDIOAUDIO, +}; + +/* pmu bus idle status register */ +enum pmu_bus_idle_st { + PMU_IDLE_ST_GPU = 0, + PMU_IDLE_ST_PERILP, + PMU_IDLE_ST_PERIHP, + PMU_IDLE_ST_VCODEC, + + PMU_IDLE_ST_VDU, + PMU_IDLE_ST_RGA, + PMU_IDLE_ST_IEP, + PMU_IDLE_ST_VOPB, + + PMU_IDLE_ST_VOPL, + PMU_IDLE_ST_ISP0, + PMU_IDLE_ST_ISP1, + PMU_IDLE_ST_HDCP, + + PMU_IDLE_ST_USB3, + PMU_IDLE_ST_PERILPM0, + PMU_IDLE_ST_CENTER, + PMU_IDLE_ST_CCIM0, + + PMU_IDLE_ST_CCIM1, + PMU_IDLE_ST_VIO, + PMU_IDLE_ST_MSCH0, + PMU_IDLE_ST_MSCH1, + + PMU_IDLE_ST_ALIVE, + PMU_IDLE_ST_PMU, + PMU_IDLE_ST_EDP, + PMU_IDLE_ST_GMAC, + + PMU_IDLE_ST_EMMC, + PMU_IDLE_ST_CENTER1, + PMU_IDLE_ST_PMUM0, + PMU_IDLE_ST_GIC, + + PMU_IDLE_ST_SD, + PMU_IDLE_ST_SDIOAUDIO, +}; + +enum pmu_bus_idle_ack { + PMU_IDLE_ACK_GPU = 0, + PMU_IDLE_ACK_PERILP, + PMU_IDLE_ACK_PERIHP, + PMU_IDLE_ACK_VCODEC, + + PMU_IDLE_ACK_VDU, + PMU_IDLE_ACK_RGA, + PMU_IDLE_ACK_IEP, + PMU_IDLE_ACK_VOPB, + + PMU_IDLE_ACK_VOPL, + PMU_IDLE_ACK_ISP0, + PMU_IDLE_ACK_ISP1, + PMU_IDLE_ACK_HDCP, + + PMU_IDLE_ACK_USB3, + PMU_IDLE_ACK_PERILPM0, + PMU_IDLE_ACK_CENTER, + PMU_IDLE_ACK_CCIM0, + + PMU_IDLE_ACK_CCIM1, + PMU_IDLE_ACK_VIO, + PMU_IDLE_ACK_MSCH0, + PMU_IDLE_ACK_MSCH1, + + PMU_IDLE_ACK_ALIVE, + PMU_IDLE_ACK_PMU, + PMU_IDLE_ACK_EDP, + PMU_IDLE_ACK_GMAC, + + PMU_IDLE_ACK_EMMC, + PMU_IDLE_ACK_CENTER1, + PMU_IDLE_ACK_PMUM0, + PMU_IDLE_ACK_GIC, + + PMU_IDLE_ACK_SD, + PMU_IDLE_ACK_SDIOAUDIO, +}; + +enum pmu_cci500_con { + PMU_PREQ_CCI500_CFG_SW = 0, + PMU_CLR_PREQ_CCI500_HW, + PMU_PSTATE_CCI500_0, + PMU_PSTATE_CCI500_1, + + PMU_PSTATE_CCI500_2, + PMU_QREQ_CCI500_CFG_SW, + PMU_CLR_QREQ_CCI500_HW, + PMU_QGATING_CCI500_CFG, + + PMU_PREQ_CCI500_CFG_SW_WMSK = 16, + PMU_CLR_PREQ_CCI500_HW_WMSK, + PMU_PSTATE_CCI500_0_WMSK, + PMU_PSTATE_CCI500_1_WMSK, + + PMU_PSTATE_CCI500_2_WMSK, + PMU_QREQ_CCI500_CFG_SW_WMSK, + PMU_CLR_QREQ_CCI500_HW_WMSK, + PMU_QGATING_CCI500_CFG_WMSK, +}; + +enum pmu_adb400_con { + PMU_PWRDWN_REQ_CXCS_SW = 0, + PMU_PWRDWN_REQ_CORE_L_SW, + PMU_PWRDWN_REQ_CORE_L_2GIC_SW, + PMU_PWRDWN_REQ_GIC2_CORE_L_SW, + + PMU_PWRDWN_REQ_CORE_B_SW, + PMU_PWRDWN_REQ_CORE_B_2GIC_SW, + PMU_PWRDWN_REQ_GIC2_CORE_B_SW, + + PMU_CLR_CXCS_HW = 8, + PMU_CLR_CORE_L_HW, + PMU_CLR_CORE_L_2GIC_HW, + PMU_CLR_GIC2_CORE_L_HW, + + PMU_CLR_CORE_B_HW, + PMU_CLR_CORE_B_2GIC_HW, + PMU_CLR_GIC2_CORE_B_HW, + + PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16, + PMU_PWRDWN_REQ_CORE_L_SW_WMSK, + PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK, + PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK, + + PMU_PWRDWN_REQ_CORE_B_SW_WMSK, + PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK, + PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK, + + PMU_CLR_CXCS_HW_WMSK = 24, + PMU_CLR_CORE_L_HW_WMSK, + PMU_CLR_CORE_L_2GIC_HW_WMSK, + PMU_CLR_GIC2_CORE_L_HW_WMSK, + + PMU_CLR_CORE_B_HW_WMSK, + PMU_CLR_CORE_B_2GIC_HW_WMSK, + PMU_CLR_GIC2_CORE_B_HW_WMSK, +}; + +enum pmu_adb400_st { + PMU_PWRDWN_REQ_CXCS_SW_ST = 0, + PMU_PWRDWN_REQ_CORE_L_SW_ST, + PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST, + PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST, + + PMU_PWRDWN_REQ_CORE_B_SW_ST, + PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST, + PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST, + + PMU_CLR_CXCS_HW_ST = 8, + PMU_CLR_CORE_L_HW_ST, + PMU_CLR_CORE_L_2GIC_HW_ST, + PMU_CLR_GIC2_CORE_L_HW_ST, + + PMU_CLR_CORE_B_HW_ST, + PMU_CLR_CORE_B_2GIC_HW_ST, + PMU_CLR_GIC2_CORE_B_HW_ST, +}; + +enum pmu_pwrdn_con1 { + PMU_VD_SCU_L_PWRDN_EN = 0, + PMU_VD_SCU_B_PWRDN_EN, + PMU_VD_CENTER_PWRDN_EN, +}; + +enum pmu_core_pwr_st { + L2_FLUSHDONE_CLUSTER_L = 0, + STANDBY_BY_WFIL2_CLUSTER_L, + + L2_FLUSHDONE_CLUSTER_B = 10, + STANDBY_BY_WFIL2_CLUSTER_B, +}; + +#endif /* __PMU_BITS_H__ */ diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu_regs.h b/plat/rockchip/rk3399/include/shared/pmu_regs.h index 399d844c..399d844c 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu_regs.h +++ b/plat/rockchip/rk3399/include/shared/pmu_regs.h diff --git a/plat/rockchip/rk3399/plat_sip_calls.c b/plat/rockchip/rk3399/plat_sip_calls.c index 6f5a4bdf..7cf3957e 100644 --- a/plat/rockchip/rk3399/plat_sip_calls.c +++ b/plat/rockchip/rk3399/plat_sip_calls.c @@ -44,24 +44,20 @@ #define DRAM_GET_RATE 0x05 #define DRAM_CLR_IRQ 0x06 #define DRAM_SET_PARAM 0x07 +#define DRAM_SET_ODT_PD 0x08 -uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id) +uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, + uint64_t id, uint64_t arg2) { switch (id) { - case DRAM_INIT: - ddr_dfs_init(); - break; case DRAM_SET_RATE: return ddr_set_rate((uint32_t)arg0); case DRAM_ROUND_RATE: return ddr_round_rate((uint32_t)arg0); case DRAM_GET_RATE: return ddr_get_rate(); - case DRAM_CLR_IRQ: - clr_dcf_irq(); - break; - case DRAM_SET_PARAM: - dts_timing_receive((uint32_t)arg0, (uint32_t)arg1); + case DRAM_SET_ODT_PD: + dram_set_odt_pd(arg0, arg1, arg2); break; default: break; @@ -81,7 +77,7 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, { switch (smc_fid) { case RK_SIP_DDR_CFG: - SMC_RET1(handle, ddr_smc_handler(x1, x2, x3)); + SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4)); default: ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); SMC_RET1(handle, SMC_UNK); diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk index 3628dc35..c72119c4 100644 --- a/plat/rockchip/rk3399/platform.mk +++ b/plat/rockchip/rk3399/platform.mk @@ -28,63 +28,67 @@ # POSSIBILITY OF SUCH DAMAGE. # -RK_PLAT := plat/rockchip -RK_PLAT_SOC := ${RK_PLAT}/${PLAT} -RK_PLAT_COMMON := ${RK_PLAT}/common +RK_PLAT := plat/rockchip +RK_PLAT_SOC := ${RK_PLAT}/${PLAT} +RK_PLAT_COMMON := ${RK_PLAT}/common -PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \ - -I${RK_PLAT_COMMON}/include/ \ - -I${RK_PLAT_COMMON}/pmusram \ - -I${RK_PLAT_COMMON}/drivers/pmu/ \ - -I${RK_PLAT_SOC}/ \ - -I${RK_PLAT_SOC}/drivers/pmu/ \ - -I${RK_PLAT_SOC}/drivers/pwm/ \ - -I${RK_PLAT_SOC}/drivers/soc/ \ - -I${RK_PLAT_SOC}/drivers/dram/ \ - -I${RK_PLAT_SOC}/include/ \ +PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \ + -I${RK_PLAT_COMMON}/include/ \ + -I${RK_PLAT_COMMON}/pmusram \ + -I${RK_PLAT_COMMON}/drivers/pmu/ \ + -I${RK_PLAT_SOC}/ \ + -I${RK_PLAT_SOC}/drivers/pmu/ \ + -I${RK_PLAT_SOC}/drivers/pwm/ \ + -I${RK_PLAT_SOC}/drivers/secure/ \ + -I${RK_PLAT_SOC}/drivers/soc/ \ + -I${RK_PLAT_SOC}/drivers/dram/ \ + -I${RK_PLAT_SOC}/include/ \ + -I${RK_PLAT_SOC}/include/shared/ \ -RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v3/gicv3_main.c \ - drivers/arm/gic/v3/gicv3_helpers.c \ - plat/common/plat_gicv3.c \ - ${RK_PLAT}/common/rockchip_gicv3.c +RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/v3/gicv3_helpers.c \ + plat/common/plat_gicv3.c \ + ${RK_PLAT}/common/rockchip_gicv3.c -PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ - lib/xlat_tables/aarch64/xlat_tables.c \ - plat/common/aarch64/plat_common.c \ +PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c \ plat/common/plat_psci_common.c -BL31_SOURCES += ${RK_GIC_SOURCES} \ - drivers/arm/cci/cci.c \ - drivers/console/aarch64/console.S \ - drivers/ti/uart/aarch64/16550_console.S \ - drivers/delay_timer/delay_timer.c \ - drivers/delay_timer/generic_delay_timer.c \ - drivers/gpio/gpio.c \ - lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/cortex_a72.S \ - plat/common/aarch64/platform_mp_stack.S \ - ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ - ${RK_PLAT_COMMON}/bl31_plat_setup.c \ - ${RK_PLAT_COMMON}/params_setup.c \ - ${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \ - ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \ - ${RK_PLAT_COMMON}/plat_pm.c \ - ${RK_PLAT_COMMON}/plat_topology.c \ - ${RK_PLAT_COMMON}/aarch64/platform_common.c \ - ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ - ${RK_PLAT_SOC}/plat_sip_calls.c \ - ${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \ - ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ - ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \ - ${RK_PLAT_SOC}/drivers/pwm/pwm.c \ - ${RK_PLAT_SOC}/drivers/soc/soc.c \ - ${RK_PLAT_SOC}/drivers/dram/dfs.c \ - ${RK_PLAT_SOC}/drivers/dram/suspend.c \ - ${RK_PLAT_SOC}/drivers/dram/dram.c \ - ${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c +BL31_SOURCES += ${RK_GIC_SOURCES} \ + drivers/arm/cci/cci.c \ + drivers/console/aarch64/console.S \ + drivers/ti/uart/aarch64/16550_console.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/gpio/gpio.c \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a72.S \ + plat/common/aarch64/platform_mp_stack.S \ + ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ + ${RK_PLAT_COMMON}/bl31_plat_setup.c \ + ${RK_PLAT_COMMON}/params_setup.c \ + ${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \ + ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \ + ${RK_PLAT_COMMON}/plat_pm.c \ + ${RK_PLAT_COMMON}/plat_topology.c \ + ${RK_PLAT_COMMON}/aarch64/platform_common.c \ + ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ + ${RK_PLAT_SOC}/plat_sip_calls.c \ + ${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \ + ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ + ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \ + ${RK_PLAT_SOC}/drivers/pmu/m0_ctl.c \ + ${RK_PLAT_SOC}/drivers/pwm/pwm.c \ + ${RK_PLAT_SOC}/drivers/secure/secure.c \ + ${RK_PLAT_SOC}/drivers/soc/soc.c \ + ${RK_PLAT_SOC}/drivers/dram/dfs.c \ + ${RK_PLAT_SOC}/drivers/dram/dram.c \ + ${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c \ + ${RK_PLAT_SOC}/drivers/dram/suspend.c -ENABLE_PLAT_COMPAT := 0 +ENABLE_PLAT_COMPAT := 0 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) diff --git a/plat/rockchip/rk3399/rk3399_def.h b/plat/rockchip/rk3399/rk3399_def.h index fdf93fd6..a24176d9 100644 --- a/plat/rockchip/rk3399/rk3399_def.h +++ b/plat/rockchip/rk3399/rk3399_def.h @@ -31,122 +31,18 @@ #ifndef __PLAT_DEF_H__ #define __PLAT_DEF_H__ -#define RK3399_PRIMARY_CPU 0x0 +#include <addressmap.h> -/* Special value used to verify platform parameters from BL2 to BL3-1 */ -#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL - -#define SIZE_K(n) ((n) * 1024) -#define SIZE_M(n) ((n) * 1024 * 1024) - -/* Register base address and size */ -#define MMIO_BASE 0xfe000000 - -#define GIC500_BASE (MMIO_BASE + 0xe00000) -#define GIC500_SIZE SIZE_M(2) - -#define PMU_BASE (MMIO_BASE + 0x1310000) -#define PMU_SIZE SIZE_K(64) - -#define PMUGRF_BASE (MMIO_BASE + 0x1320000) -#define PMUGRF_SIZE SIZE_K(64) - -#define SGRF_BASE (MMIO_BASE + 0x1330000) -#define SGRF_SIZE SIZE_K(64) - -#define PMUSRAM_BASE (MMIO_BASE + 0x13b0000) -#define PMUSRAM_SIZE SIZE_K(64) -#define PMUSRAM_RSIZE SIZE_K(8) - -#define PWM_BASE (MMIO_BASE + 0x1420000) -#define PWM_SIZE SIZE_K(64) - -#define CIC_BASE (MMIO_BASE + 0x1620000) -#define CIC_SIZE SIZE_K(4) - -#define DCF_BASE (MMIO_BASE + 0x16a0000) -#define DCF_SIZE SIZE_K(4) - -#define GPIO0_BASE (MMIO_BASE + 0x1720000) -#define GPIO0_SIZE SIZE_K(64) - -#define GPIO1_BASE (MMIO_BASE + 0x1730000) -#define GPIO1_SIZE SIZE_K(64) - -#define CRUS_BASE (MMIO_BASE + 0x1750000) -#define CRUS_SIZE SIZE_K(128) - -#define GRF_BASE (MMIO_BASE + 0x1770000) -#define GRF_SIZE SIZE_K(64) - -#define GPIO2_BASE (MMIO_BASE + 0x1780000) -#define GPIO2_SIZE SIZE_K(32) - -#define GPIO3_BASE (MMIO_BASE + 0x1788000) -#define GPIO3_SIZE SIZE_K(32) - -#define GPIO4_BASE (MMIO_BASE + 0x1790000) -#define GPIO4_SIZE SIZE_K(32) - -#define STIME_BASE (MMIO_BASE + 0x1860000) -#define STIME_SIZE SIZE_K(64) +#define RK3399_PRIMARY_CPU 0x0 -#define SRAM_BASE (MMIO_BASE + 0x18c0000) -#define SRAM_SIZE SIZE_K(192) - -#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000) -#define NOC_0_SIZE SIZE_K(192) - -#define DDRC0_BASE (MMIO_BASE + 0x1a80000) -#define DDRC0_SIZE SIZE_K(32) - -#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000) -#define NOC_1_SIZE SIZE_K(16) - -#define DDRC1_BASE (MMIO_BASE + 0x1a88000) -#define DDRC1_SIZE SIZE_K(32) - -#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000) -#define NOC_2_SIZE SIZE_K(16) - -#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x1a90000) -#define NOC_3_SIZE SIZE_K(448) - -#define CCI500_BASE (MMIO_BASE + 0x1b00000) -#define CCI500_SIZE SIZE_M(1) - -#define DDR_PI_OFFSET 0x800 -#define DDR_PHY_OFFSET 0x2000 - -#define DDRC0_PI_BASE (DDRC0_BASE + DDR_PI_OFFSET) -#define DDRC0_PHY_BASE (DDRC0_BASE + DDR_PHY_OFFSET) -#define DDRC1_PI_BASE (DDRC1_BASE + DDR_PI_OFFSET) -#define DDRC1_PHY_BASE (DDRC1_BASE + DDR_PHY_OFFSET) - -/* Aggregate of all devices in the first GB */ -#define RK3399_DEV_RNG0_BASE MMIO_BASE -#define RK3399_DEV_RNG0_SIZE 0x1d00000 - -/* - * include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr - * 0xff650000 -0xff6c0000 - */ -#define PD_BUS0_BASE (MMIO_BASE + 0x1650000) -#define PD_BUS0_SIZE SIZE_K(448) - -#define PMUCRU_BASE (MMIO_BASE + 0x1750000) -#define CRU_BASE (MMIO_BASE + 0x1760000) - -#define COLD_BOOT_BASE (MMIO_BASE + 0x1ff0000) +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL /************************************************************************** * UART related constants **************************************************************************/ -#define RK3399_UART2_BASE (0xff1a0000) -#define RK3399_UART2_SIZE SIZE_K(64) - -#define RK3399_BAUDRATE (115200) -#define RK3399_UART_CLOCK (24000000) +#define RK3399_BAUDRATE 115200 +#define RK3399_UART_CLOCK 24000000 /****************************************************************************** * System counter frequency related constants @@ -154,8 +50,8 @@ #define SYS_COUNTER_FREQ_IN_TICKS 24000000 /* Base rockchip_platform compatible GIC memory map */ -#define BASE_GICD_BASE (GIC500_BASE) -#define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) +#define BASE_GICD_BASE (GIC500_BASE) +#define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) /***************************************************************************** * CCI-400 related constants @@ -176,6 +72,7 @@ #define ARM_IRQ_SEC_SGI_5 13 #define ARM_IRQ_SEC_SGI_6 14 #define ARM_IRQ_SEC_SGI_7 15 + /* * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 * terminology. On a GICv2 system or mode, the lists will be merged and treated diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c index e102b4f2..0fe17b5e 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_client.c +++ b/plat/xilinx/zynqmp/pm_service/pm_client.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -40,6 +40,7 @@ #include <bl_common.h> #include <mmio.h> #include <string.h> +#include <utils.h> #include "pm_api_sys.h" #include "pm_client.h" #include "pm_ipi.h" @@ -188,7 +189,7 @@ static void pm_client_set_wakeup_sources(void) uint8_t pm_wakeup_nodes_set[NODE_MAX]; uintptr_t isenabler1 = BASE_GICD_BASE + GICD_ISENABLER + 4; - memset(&pm_wakeup_nodes_set, 0, sizeof(pm_wakeup_nodes_set)); + zeromem(&pm_wakeup_nodes_set, sizeof(pm_wakeup_nodes_set)); for (reg_num = 0; reg_num < NUM_GICD_ISENABLER; reg_num++) { uint32_t base_irq = reg_num << ISENABLER_SHIFT; diff --git a/services/spd/opteed/opteed_common.c b/services/spd/opteed/opteed_common.c index 2f20b7ca..910f900b 100644 --- a/services/spd/opteed/opteed_common.c +++ b/services/spd/opteed/opteed_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ #include <bl_common.h> #include <context_mgmt.h> #include <string.h> +#include <utils.h> #include "opteed_private.h" /******************************************************************************* @@ -73,7 +74,7 @@ void opteed_init_optee_ep_state(struct entry_point_info *optee_entry_point, DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT); - memset(&optee_entry_point->args, 0, sizeof(optee_entry_point->args)); + zeromem(&optee_entry_point->args, sizeof(optee_entry_point->args)); } /******************************************************************************* diff --git a/services/spd/trusty/smcall.h b/services/spd/trusty/smcall.h index 7e876c89..a1d91e5a 100644 --- a/services/spd/trusty/smcall.h +++ b/services/spd/trusty/smcall.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -40,11 +40,12 @@ #define SMC_ENTITY(smc_nr) (((smc_nr) & 0x3F000000) >> 24) #define SMC_FUNCTION(smc_nr) ((smc_nr) & 0x0000FFFF) -#define SMC_NR(entity, fn, fastcall, smc64) ((((fastcall) & 0x1) << 31) | \ - (((smc64) & 0x1) << 30) | \ - (((entity) & 0x3F) << 24) | \ - ((fn) & 0xFFFF) \ - ) +#define SMC_NR(entity, fn, fastcall, smc64) \ + (((((unsigned int) (fastcall)) & 0x1) << 31) | \ + (((smc64) & 0x1) << 30) | \ + (((entity) & 0x3F) << 24) | \ + ((fn) & 0xFFFF) \ + ) #define SMC_FASTCALL_NR(entity, fn) SMC_NR((entity), (fn), 1, 0) #define SMC_STDCALL_NR(entity, fn) SMC_NR((entity), (fn), 0, 0) diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c index 78a68ba0..b21ce715 100644 --- a/services/spd/trusty/trusty.c +++ b/services/spd/trusty/trusty.c @@ -395,7 +395,7 @@ DECLARE_RT_SVC( DECLARE_RT_SVC( trusty_std, - OEN_TOS_START, + OEN_TAP_START, SMC_ENTITY_SECURE_MONITOR, SMC_TYPE_STD, NULL, diff --git a/services/spd/tspd/tspd_common.c b/services/spd/tspd/tspd_common.c index 3dcefea9..70959d75 100644 --- a/services/spd/tspd/tspd_common.c +++ b/services/spd/tspd/tspd_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,6 +35,7 @@ #include <debug.h> #include <string.h> #include <tsp.h> +#include <utils.h> #include "tspd_private.h" /******************************************************************************* @@ -78,7 +79,7 @@ void tspd_init_tsp_ep_state(struct entry_point_info *tsp_entry_point, tsp_entry_point->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); - memset(&tsp_entry_point->args, 0, sizeof(tsp_entry_point->args)); + zeromem(&tsp_entry_point->args, sizeof(tsp_entry_point->args)); } /******************************************************************************* diff --git a/tools/cert_create/include/key.h b/tools/cert_create/include/key.h index f60997f0..433f72ce 100644 --- a/tools/cert_create/include/key.h +++ b/tools/cert_create/include/key.h @@ -73,6 +73,7 @@ typedef struct key_s { /* Exported API */ int key_init(void); key_t *key_get_by_opt(const char *opt); +int key_new(key_t *key); int key_create(key_t *key, int type); int key_load(key_t *key, unsigned int *err_code); int key_store(key_t *key); diff --git a/tools/cert_create/src/cert.c b/tools/cert_create/src/cert.c index a559832e..375c66bf 100644 --- a/tools/cert_create/src/cert.c +++ b/tools/cert_create/src/cert.c @@ -103,10 +103,10 @@ int cert_new(cert_t *cert, int days, int ca, STACK_OF(X509_EXTENSION) * sk) cert_t *issuer_cert = &certs[cert->issuer]; EVP_PKEY *ikey = keys[issuer_cert->key].key; X509 *issuer = issuer_cert->x; - X509 *x = NULL; - X509_EXTENSION *ex = NULL; - X509_NAME *name = NULL; - ASN1_INTEGER *sno = NULL; + X509 *x; + X509_EXTENSION *ex; + X509_NAME *name; + ASN1_INTEGER *sno; int i, num; /* Create the certificate structure */ @@ -202,7 +202,7 @@ int cert_init(void) cert_t *cert_get_by_opt(const char *opt) { - cert_t *cert = NULL; + cert_t *cert; unsigned int i; for (i = 0; i < num_certs; i++) { diff --git a/tools/cert_create/src/ext.c b/tools/cert_create/src/ext.c index 3f56edb7..a50919ee 100644 --- a/tools/cert_create/src/ext.c +++ b/tools/cert_create/src/ext.c @@ -181,13 +181,13 @@ X509_EXTENSION *ext_new(int nid, int crit, unsigned char *data, int len) X509_EXTENSION *ext_new_hash(int nid, int crit, const EVP_MD *md, unsigned char *buf, size_t len) { - X509_EXTENSION *ex = NULL; - ASN1_OCTET_STRING *octet = NULL; - HASH *hash = NULL; - ASN1_OBJECT *algorithm = NULL; - X509_ALGOR *x509_algor = NULL; + X509_EXTENSION *ex; + ASN1_OCTET_STRING *octet; + HASH *hash; + ASN1_OBJECT *algorithm; + X509_ALGOR *x509_algor; unsigned char *p = NULL; - int sz = -1; + int sz; /* OBJECT_IDENTIFIER with hash algorithm */ algorithm = OBJ_nid2obj(md->type); @@ -254,16 +254,15 @@ X509_EXTENSION *ext_new_hash(int nid, int crit, const EVP_MD *md, */ X509_EXTENSION *ext_new_nvcounter(int nid, int crit, int value) { - X509_EXTENSION *ex = NULL; - ASN1_INTEGER *counter = NULL; + X509_EXTENSION *ex; + ASN1_INTEGER *counter; unsigned char *p = NULL; - int sz = -1; + int sz; /* Encode counter */ counter = ASN1_INTEGER_new(); ASN1_INTEGER_set(counter, value); - sz = i2d_ASN1_INTEGER(counter, NULL); - i2d_ASN1_INTEGER(counter, &p); + sz = i2d_ASN1_INTEGER(counter, &p); /* Create the extension */ ex = ext_new(nid, crit, p, sz); @@ -292,9 +291,9 @@ X509_EXTENSION *ext_new_nvcounter(int nid, int crit, int value) */ X509_EXTENSION *ext_new_key(int nid, int crit, EVP_PKEY *k) { - X509_EXTENSION *ex = NULL; - unsigned char *p = NULL; - int sz = -1; + X509_EXTENSION *ex; + unsigned char *p; + int sz; /* Encode key */ BIO *mem = BIO_new(BIO_s_mem()); @@ -316,7 +315,7 @@ X509_EXTENSION *ext_new_key(int nid, int crit, EVP_PKEY *k) ext_t *ext_get_by_opt(const char *opt) { - ext_t *ext = NULL; + ext_t *ext; unsigned int i; /* Sequential search. This is not a performance concern since the number diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c index a7ee7596..ce0e4da6 100644 --- a/tools/cert_create/src/key.c +++ b/tools/cert_create/src/key.c @@ -49,7 +49,7 @@ /* * Create a new key container */ -static int key_new(key_t *key) +int key_new(key_t *key) { /* Create key pair container */ key->key = EVP_PKEY_new(); @@ -62,7 +62,7 @@ static int key_new(key_t *key) static int key_create_rsa(key_t *key) { - RSA *rsa = NULL; + RSA *rsa; rsa = RSA_generate_key(RSA_KEY_BITS, RSA_F4, NULL, NULL); if (rsa == NULL) { @@ -83,7 +83,7 @@ err: #ifndef OPENSSL_NO_EC static int key_create_ecdsa(key_t *key) { - EC_KEY *ec = NULL; + EC_KEY *ec; ec = EC_KEY_new_by_curve_name(NID_X9_62_prime256v1); if (ec == NULL) { @@ -123,11 +123,6 @@ int key_create(key_t *key, int type) return 0; } - /* Create OpenSSL key container */ - if (!key_new(key)) { - return 0; - } - if (key_create_fn[type]) { return key_create_fn[type](key); } @@ -137,14 +132,8 @@ int key_create(key_t *key, int type) int key_load(key_t *key, unsigned int *err_code) { - FILE *fp = NULL; - EVP_PKEY *k = NULL; - - /* Create OpenSSL key container */ - if (!key_new(key)) { - *err_code = KEY_ERR_MALLOC; - return 0; - } + FILE *fp; + EVP_PKEY *k; if (key->fn) { /* Load key from file */ @@ -173,7 +162,7 @@ int key_load(key_t *key, unsigned int *err_code) int key_store(key_t *key) { - FILE *fp = NULL; + FILE *fp; if (key->fn) { fp = fopen(key->fn, "w"); @@ -196,7 +185,6 @@ int key_init(void) { cmd_opt_t cmd_opt; key_t *key; - int rc = 0; unsigned int i; for (i = 0; i < num_keys; i++) { @@ -211,12 +199,12 @@ int key_init(void) } } - return rc; + return 0; } key_t *key_get_by_opt(const char *opt) { - key_t *key = NULL; + key_t *key; unsigned int i; /* Sequential search. This is not a performance concern since the number diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c index c58f41de..c9c96222 100644 --- a/tools/cert_create/src/main.c +++ b/tools/cert_create/src/main.c @@ -134,7 +134,6 @@ static void print_help(const char *cmd, const struct option *long_opt) printf("\t%s [OPTIONS]\n\n", cmd); printf("Available options:\n"); - i = 0; opt = long_opt; while (opt->name) { p = line; @@ -261,12 +260,12 @@ static const cmd_opt_t common_cmd_opt[] = { int main(int argc, char *argv[]) { - STACK_OF(X509_EXTENSION) * sk = NULL; - X509_EXTENSION *cert_ext = NULL; - ext_t *ext = NULL; - key_t *key = NULL; - cert_t *cert = NULL; - FILE *file = NULL; + STACK_OF(X509_EXTENSION) * sk; + X509_EXTENSION *cert_ext; + ext_t *ext; + key_t *key; + cert_t *cert; + FILE *file; int i, j, ext_nid, nvctr; int c, opt_idx = 0; const struct option *cmd_opt; @@ -367,6 +366,11 @@ int main(int argc, char *argv[]) /* Load private keys from files (or generate new ones) */ for (i = 0 ; i < num_keys ; i++) { + if (!key_new(&keys[i])) { + ERROR("Failed to allocate key container\n"); + exit(1); + } + /* First try to load the key from disk */ if (key_load(&keys[i], &err_code)) { /* Key loaded successfully */ @@ -374,11 +378,7 @@ int main(int argc, char *argv[]) } /* Key not loaded. Check the error code */ - if (err_code == KEY_ERR_MALLOC) { - /* Cannot allocate memory. Abort. */ - ERROR("Malloc error while loading '%s'\n", keys[i].fn); - exit(1); - } else if (err_code == KEY_ERR_LOAD) { + if (err_code == KEY_ERR_LOAD) { /* File exists, but it does not contain a valid private * key. Abort. */ ERROR("Error loading '%s'\n", keys[i].fn); diff --git a/tools/fiptool/fiptool.c b/tools/fiptool/fiptool.c index 6145e26d..f3f831bd 100644 --- a/tools/fiptool/fiptool.c +++ b/tools/fiptool/fiptool.c @@ -50,9 +50,8 @@ #define OPT_TOC_ENTRY 0 #define OPT_PLAT_TOC_FLAGS 1 +#define OPT_ALIGN 2 -static image_desc_t *lookup_image_desc_from_uuid(const uuid_t *uuid); -static image_t *lookup_image_from_uuid(const uuid_t *uuid); static int info_cmd(int argc, char *argv[]); static void info_usage(void); static int create_cmd(int argc, char *argv[]); @@ -160,6 +159,12 @@ static void *xzalloc(size_t size, const char *msg) return memset(xmalloc(size, msg), 0, size); } +static void xfwrite(void *buf, size_t size, FILE *fp, const char *filename) +{ + if (fwrite(buf, 1, size, fp) != size) + log_errx("Failed to write %s", filename); +} + static image_desc_t *new_image_desc(const uuid_t *uuid, const char *name, const char *cmdline_name) { @@ -202,11 +207,10 @@ static void add_image_desc(image_desc_t *desc) { image_desc_t **p = &image_desc_head; - assert(lookup_image_desc_from_uuid(&desc->uuid) == NULL); - while (*p) p = &(*p)->next; + assert(*p == NULL); *p = desc; nr_image_descs++; } @@ -244,16 +248,32 @@ static void add_image(image_t *image) { image_t **p = &image_head; - assert(lookup_image_from_uuid(&image->uuid) == NULL); - while (*p) p = &(*p)->next; + assert(*p == NULL); *p = image; nr_images++; } +static void replace_image(image_t *image) +{ + image_t **p = &image_head; + + while (*p) { + if (!memcmp(&(*p)->toc_e.uuid, &image->toc_e.uuid, + sizeof(image->toc_e.uuid))) + break; + p = &(*p)->next; + } + + assert(*p != NULL); + + image->next = (*p)->next; + *p = image; +} + static void free_image(image_t *image) { free(image->buffer); @@ -262,20 +282,20 @@ static void free_image(image_t *image) static void remove_image(image_t *image) { - image_t *tmp = image_head, *prev; - - if (tmp == image) { - image_head = tmp->next; - free_image(tmp); - } else { - while (tmp != NULL && tmp != image) { - prev = tmp; - tmp = tmp->next; - } - assert(tmp != NULL); - prev->next = tmp->next; - free_image(tmp); + image_t *tmp, **p = &image_head; + + while (*p) { + if (*p == image) + break; + p = &(*p)->next; } + + assert(*p != NULL); + + tmp = *p; + *p = tmp->next; + free_image(tmp); + nr_images--; } @@ -317,7 +337,7 @@ static image_t *lookup_image_from_uuid(const uuid_t *uuid) image_t *image; for (image = image_head; image != NULL; image = image->next) - if (memcmp(&image->uuid, uuid, sizeof(uuid_t)) == 0) + if (!memcmp(&image->toc_e.uuid, uuid, sizeof(*uuid))) return image; return NULL; } @@ -410,7 +430,7 @@ static int parse_fip(const char *filename, fip_toc_header_t *toc_header_out) */ image = xzalloc(sizeof(*image), "failed to allocate memory for image"); - memcpy(&image->uuid, &toc_entry->uuid, sizeof(uuid_t)); + image->toc_e = *toc_entry; image->buffer = xmalloc(toc_entry->size, "failed to allocate image buffer, is FIP file corrupted?"); /* Overflow checks before memory copy. */ @@ -421,17 +441,16 @@ static int parse_fip(const char *filename, fip_toc_header_t *toc_header_out) memcpy(image->buffer, buf + toc_entry->offset_address, toc_entry->size); - image->size = toc_entry->size; /* If this is an unknown image, create a descriptor for it. */ - desc = lookup_image_desc_from_uuid(&image->uuid); + desc = lookup_image_desc_from_uuid(&toc_entry->uuid); if (desc == NULL) { char name[_UUID_STR_LEN + 1], filename[PATH_MAX]; - uuid_to_str(name, sizeof(name), &image->uuid); + uuid_to_str(name, sizeof(name), &toc_entry->uuid); snprintf(filename, sizeof(filename), "%s%s", name, ".bin"); - desc = new_image_desc(&image->uuid, name, "blob"); + desc = new_image_desc(&toc_entry->uuid, name, "blob"); desc->action = DO_UNPACK; desc->action_arg = xstrdup(filename, "failed to allocate memory for blob filename"); @@ -466,11 +485,11 @@ static image_t *read_image_from_file(const uuid_t *uuid, const char *filename) log_errx("fstat %s", filename); image = xzalloc(sizeof(*image), "failed to allocate memory for image"); - memcpy(&image->uuid, uuid, sizeof(uuid_t)); + image->toc_e.uuid = *uuid; image->buffer = xmalloc(st.st_size, "failed to allocate image buffer"); if (fread(image->buffer, 1, st.st_size, fp) != st.st_size) log_errx("Failed to read %s", filename); - image->size = st.st_size; + image->toc_e.size = st.st_size; fclose(fp); return image; @@ -483,8 +502,7 @@ static int write_image_to_file(const image_t *image, const char *filename) fp = fopen(filename, "w"); if (fp == NULL) log_err("fopen"); - if (fwrite(image->buffer, 1, image->size, fp) != image->size) - log_errx("Failed to write %s", filename); + xfwrite(image->buffer, image->toc_e.size, fp, filename); fclose(fp); return 0; } @@ -525,8 +543,6 @@ static void md_print(const unsigned char *md, size_t len) static int info_cmd(int argc, char *argv[]) { image_t *image; - uint64_t image_offset; - uint64_t image_size; fip_toc_header_t toc_header; if (argc != 2) @@ -544,31 +560,24 @@ static int info_cmd(int argc, char *argv[]) (unsigned long long)toc_header.flags); } - image_offset = sizeof(fip_toc_header_t) + - (sizeof(fip_toc_entry_t) * (nr_images + 1)); - for (image = image_head; image != NULL; image = image->next) { image_desc_t *desc; - desc = lookup_image_desc_from_uuid(&image->uuid); + desc = lookup_image_desc_from_uuid(&image->toc_e.uuid); assert(desc != NULL); - printf("%s: ", desc->name); - image_size = image->size; - printf("offset=0x%llX, size=0x%llX", - (unsigned long long)image_offset, - (unsigned long long)image_size); - if (desc != NULL) - printf(", cmdline=\"--%s\"", - desc->cmdline_name); + printf("%s: offset=0x%llX, size=0x%llX, cmdline=\"--%s\"", + desc->name, + (unsigned long long)image->toc_e.offset_address, + (unsigned long long)image->toc_e.size, + desc->cmdline_name); if (verbose) { unsigned char md[SHA256_DIGEST_LENGTH]; - SHA256(image->buffer, image_size, md); + SHA256(image->buffer, image->toc_e.size, md); printf(", sha256="); md_print(md, sizeof(md)); } putchar('\n'); - image_offset += image_size; } free_images(); @@ -581,19 +590,14 @@ static void info_usage(void) exit(1); } -static int pack_images(const char *filename, uint64_t toc_flags) +static int pack_images(const char *filename, uint64_t toc_flags, unsigned long align) { FILE *fp; image_t *image; fip_toc_header_t *toc_header; fip_toc_entry_t *toc_entry; char *buf; - uint64_t entry_offset, buf_size, payload_size; - - /* Calculate total payload size and allocate scratch buffer. */ - payload_size = 0; - for (image = image_head; image != NULL; image = image->next) - payload_size += image->size; + uint64_t entry_offset, buf_size, payload_size = 0; buf_size = sizeof(fip_toc_header_t) + sizeof(fip_toc_entry_t) * (nr_images + 1); @@ -611,19 +615,16 @@ static int pack_images(const char *filename, uint64_t toc_flags) entry_offset = buf_size; for (image = image_head; image != NULL; image = image->next) { - memcpy(&toc_entry->uuid, &image->uuid, sizeof(uuid_t)); - toc_entry->offset_address = entry_offset; - toc_entry->size = image->size; - toc_entry->flags = 0; - entry_offset += toc_entry->size; - toc_entry++; + payload_size += image->toc_e.size; + entry_offset = (entry_offset + align - 1) & ~(align - 1); + image->toc_e.offset_address = entry_offset; + *toc_entry++ = image->toc_e; + entry_offset += image->toc_e.size; } /* Append a null uuid entry to mark the end of ToC entries. */ - memcpy(&toc_entry->uuid, &uuid_null, sizeof(uuid_t)); + memset(toc_entry, 0, sizeof(*toc_entry)); toc_entry->offset_address = entry_offset; - toc_entry->size = 0; - toc_entry->flags = 0; /* Generate the FIP file. */ fp = fopen(filename, "w"); @@ -633,16 +634,18 @@ static int pack_images(const char *filename, uint64_t toc_flags) if (verbose) log_dbgx("Metadata size: %zu bytes", buf_size); - if (fwrite(buf, 1, buf_size, fp) != buf_size) - log_errx("Failed to write image to %s", filename); + xfwrite(buf, buf_size, fp, filename); free(buf); if (verbose) log_dbgx("Payload size: %zu bytes", payload_size); - for (image = image_head; image != NULL; image = image->next) - if (fwrite(image->buffer, 1, image->size, fp) != image->size) - log_errx("Failed to write image to %s", filename); + for (image = image_head; image != NULL; image = image->next) { + if (fseek(fp, image->toc_e.offset_address, SEEK_SET)) + log_errx("Failed to set file position"); + + xfwrite(image->buffer, image->toc_e.size, fp, filename); + } fclose(fp); return 0; @@ -675,8 +678,7 @@ static void update_fip(void) desc->cmdline_name, desc->action_arg); } - remove_image(old_image); - add_image(new_image); + replace_image(new_image); } else { if (verbose) log_dbgx("Adding image %s", @@ -699,6 +701,24 @@ static void parse_plat_toc_flags(const char *arg, unsigned long long *toc_flags) *toc_flags |= flags << 32; } +static int is_power_of_2(unsigned long x) +{ + return x && !(x & (x - 1)); +} + +static unsigned long get_image_align(char *arg) +{ + char *endptr; + unsigned long align; + + errno = 0; + align = strtoul(arg, &endptr, 10); + if (*endptr != '\0' || !is_power_of_2(align) || errno != 0) + log_errx("Invalid alignment: %s", arg); + + return align; +} + static void parse_blob_opt(char *arg, uuid_t *uuid, char *filename, size_t len) { char *p; @@ -719,6 +739,7 @@ static int create_cmd(int argc, char *argv[]) struct option *opts = NULL; size_t nr_opts = 0; unsigned long long toc_flags = 0; + unsigned long align = 1; if (argc < 2) create_usage(); @@ -726,6 +747,7 @@ static int create_cmd(int argc, char *argv[]) opts = fill_common_opts(opts, &nr_opts, required_argument); opts = add_opt(opts, &nr_opts, "plat-toc-flags", required_argument, OPT_PLAT_TOC_FLAGS); + opts = add_opt(opts, &nr_opts, "align", required_argument, OPT_ALIGN); opts = add_opt(opts, &nr_opts, "blob", required_argument, 'b'); opts = add_opt(opts, &nr_opts, NULL, 0, 0); @@ -747,6 +769,9 @@ static int create_cmd(int argc, char *argv[]) case OPT_PLAT_TOC_FLAGS: parse_plat_toc_flags(optarg, &toc_flags); break; + case OPT_ALIGN: + align = get_image_align(optarg); + break; case 'b': { char name[_UUID_STR_LEN + 1]; char filename[PATH_MAX] = { 0 }; @@ -782,7 +807,7 @@ static int create_cmd(int argc, char *argv[]) update_fip(); - pack_images(argv[0], toc_flags); + pack_images(argv[0], toc_flags, align); free_images(); return 0; } @@ -791,13 +816,13 @@ static void create_usage(void) { toc_entry_t *toc_entry = toc_entries; - printf("fiptool create [--blob uuid=...,file=...] " - "[--plat-toc-flags <value>] [opts] FIP_FILENAME\n"); - printf(" --blob uuid=...,file=...\tAdd an image with the given UUID " - "pointed to by file.\n"); - printf(" --plat-toc-flags <value>\t16-bit platform specific flag field " - "occupying bits 32-47 in 64-bit ToC header.\n"); - fputc('\n', stderr); + printf("fiptool create [opts] FIP_FILENAME\n"); + printf("\n"); + printf("Options:\n"); + printf(" --align <value>\t\tEach image is aligned to <value> (default: 1).\n"); + printf(" --blob uuid=...,file=...\tAdd an image with the given UUID pointed to by file.\n"); + printf(" --plat-toc-flags <value>\t16-bit platform specific flag field occupying bits 32-47 in 64-bit ToC header.\n"); + printf("\n"); printf("Specific images are packed with the following options:\n"); for (; toc_entry->cmdline_name != NULL; toc_entry++) printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name, @@ -812,12 +837,14 @@ static int update_cmd(int argc, char *argv[]) char outfile[PATH_MAX] = { 0 }; fip_toc_header_t toc_header = { 0 }; unsigned long long toc_flags = 0; + unsigned long align = 1; int pflag = 0; if (argc < 2) update_usage(); opts = fill_common_opts(opts, &nr_opts, required_argument); + opts = add_opt(opts, &nr_opts, "align", required_argument, OPT_ALIGN); opts = add_opt(opts, &nr_opts, "blob", required_argument, 'b'); opts = add_opt(opts, &nr_opts, "out", required_argument, 'o'); opts = add_opt(opts, &nr_opts, "plat-toc-flags", required_argument, @@ -865,6 +892,9 @@ static int update_cmd(int argc, char *argv[]) set_image_desc_action(desc, DO_PACK, filename); break; } + case OPT_ALIGN: + align = get_image_align(optarg); + break; case 'o': snprintf(outfile, sizeof(outfile), "%s", optarg); break; @@ -882,7 +912,7 @@ static int update_cmd(int argc, char *argv[]) if (outfile[0] == '\0') snprintf(outfile, sizeof(outfile), "%s", argv[0]); - if (access(outfile, F_OK) == 0) + if (access(argv[0], F_OK) == 0) parse_fip(argv[0], &toc_header); if (pflag) @@ -891,7 +921,7 @@ static int update_cmd(int argc, char *argv[]) update_fip(); - pack_images(outfile, toc_flags); + pack_images(outfile, toc_flags, align); free_images(); return 0; } @@ -900,14 +930,14 @@ static void update_usage(void) { toc_entry_t *toc_entry = toc_entries; - printf("fiptool update [--blob uuid=...,file=...] [--out FIP_FILENAME] " - "[--plat-toc-flags <value>] [opts] FIP_FILENAME\n"); - printf(" --blob uuid=...,file=...\tAdd or update an image " - "with the given UUID pointed to by file.\n"); + printf("fiptool update [opts] FIP_FILENAME\n"); + printf("\n"); + printf("Options:\n"); + printf(" --align <value>\t\tEach image is aligned to <value> (default: 1).\n"); + printf(" --blob uuid=...,file=...\tAdd or update an image with the given UUID pointed to by file.\n"); printf(" --out FIP_FILENAME\t\tSet an alternative output FIP file.\n"); - printf(" --plat-toc-flags <value>\t16-bit platform specific flag field " - "occupying bits 32-47 in 64-bit ToC header.\n"); - fputc('\n', stderr); + printf(" --plat-toc-flags <value>\t16-bit platform specific flag field occupying bits 32-47 in 64-bit ToC header.\n"); + printf("\n"); printf("Specific images are packed with the following options:\n"); for (; toc_entry->cmdline_name != NULL; toc_entry++) printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name, @@ -1037,19 +1067,18 @@ static void unpack_usage(void) { toc_entry_t *toc_entry = toc_entries; - printf("fiptool unpack [--blob uuid=...,file=...] [--force] " - "[--out <path>] [opts] FIP_FILENAME\n"); - printf(" --blob uuid=...,file=...\tUnpack an image with the given UUID " - "to file.\n"); - printf(" --force\t\t\tIf the output file already exists, use --force to " - "overwrite it.\n"); + printf("fiptool unpack [opts] FIP_FILENAME\n"); + printf("\n"); + printf("Options:\n"); + printf(" --blob uuid=...,file=...\tUnpack an image with the given UUID to file.\n"); + printf(" --force\t\t\tIf the output file already exists, use --force to overwrite it.\n"); printf(" --out path\t\t\tSet the output directory path.\n"); - fputc('\n', stderr); + printf("\n"); printf("Specific images are unpacked with the following options:\n"); for (; toc_entry->cmdline_name != NULL; toc_entry++) printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name, toc_entry->name); - fputc('\n', stderr); + printf("\n"); printf("If no options are provided, all images will be unpacked.\n"); exit(1); } @@ -1061,12 +1090,14 @@ static int remove_cmd(int argc, char *argv[]) char outfile[PATH_MAX] = { 0 }; fip_toc_header_t toc_header; image_desc_t *desc; + unsigned long align = 1; int fflag = 0; if (argc < 2) remove_usage(); opts = fill_common_opts(opts, &nr_opts, no_argument); + opts = add_opt(opts, &nr_opts, "align", required_argument, OPT_ALIGN); opts = add_opt(opts, &nr_opts, "blob", required_argument, 'b'); opts = add_opt(opts, &nr_opts, "force", no_argument, 'f'); opts = add_opt(opts, &nr_opts, "out", required_argument, 'o'); @@ -1087,6 +1118,9 @@ static int remove_cmd(int argc, char *argv[]) set_image_desc_action(desc, DO_REMOVE, NULL); break; } + case OPT_ALIGN: + align = get_image_align(optarg); + break; case 'b': { char name[_UUID_STR_LEN + 1], filename[PATH_MAX]; uuid_t uuid = { 0 }; @@ -1151,7 +1185,7 @@ static int remove_cmd(int argc, char *argv[]) } } - pack_images(outfile, toc_header.flags); + pack_images(outfile, toc_header.flags, align); free_images(); return 0; } @@ -1160,13 +1194,14 @@ static void remove_usage(void) { toc_entry_t *toc_entry = toc_entries; - printf("fiptool remove [--blob uuid=...] [--force] " - "[--out FIP_FILENAME] [opts] FIP_FILENAME\n"); + printf("fiptool remove [opts] FIP_FILENAME\n"); + printf("\n"); + printf("Options:\n"); + printf(" --align <value>\tEach image is aligned to <value> (default: 1).\n"); printf(" --blob uuid=...\tRemove an image with the given UUID.\n"); - printf(" --force\t\tIf the output FIP file already exists, use --force to " - "overwrite it.\n"); + printf(" --force\t\tIf the output FIP file already exists, use --force to overwrite it.\n"); printf(" --out FIP_FILENAME\tSet an alternative output FIP file.\n"); - fputc('\n', stderr); + printf("\n"); printf("Specific images are removed with the following options:\n"); for (; toc_entry->cmdline_name != NULL; toc_entry++) printf(" --%-16s\t%s\n", toc_entry->cmdline_name, @@ -1211,10 +1246,10 @@ static int help_cmd(int argc, char *argv[]) static void usage(void) { - printf("usage: [--verbose] fiptool <command> [<args>]\n"); + printf("usage: fiptool [--verbose] <command> [<args>]\n"); printf("Global options supported:\n"); printf(" --verbose\tEnable verbose output for all commands.\n"); - fputc('\n', stderr); + printf("\n"); printf("Commands supported:\n"); printf(" info\t\tList images contained in FIP.\n"); printf(" create\tCreate a new FIP with the given images.\n"); diff --git a/tools/fiptool/fiptool.h b/tools/fiptool/fiptool.h index 6ace400d..be0c6f0d 100644 --- a/tools/fiptool/fiptool.h +++ b/tools/fiptool/fiptool.h @@ -34,6 +34,7 @@ #include <stddef.h> #include <stdint.h> +#include "firmware_image_package.h" #include "uuid.h" #define NELEM(x) (sizeof (x) / sizeof *(x)) @@ -61,10 +62,9 @@ typedef struct image_desc { } image_desc_t; typedef struct image { - uuid_t uuid; - size_t size; - void *buffer; - struct image *next; + struct fip_toc_entry toc_e; + void *buffer; + struct image *next; } image_t; typedef struct cmd { |