diff options
23 files changed, 194 insertions, 53 deletions
diff --git a/docs/user-guide.rst b/docs/user-guide.rst index ce12f083..4068c9a3 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -369,6 +369,10 @@ Common build options - ``DEBUG``: Chooses between a debug and release build. It can take either 0 (release) or 1 (debug) as values. 0 is the default. +- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation + of the binary image. If set to 1, then only the ELF image is built. + 0 is the default. + - ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted Board Boot authentication at runtime. This option is meant to be enabled only for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this diff --git a/drivers/arm/smmu/smmu_v3.c b/drivers/arm/smmu/smmu_v3.c index 004e81e3..ab2eb2be 100644 --- a/drivers/arm/smmu/smmu_v3.c +++ b/drivers/arm/smmu/smmu_v3.c @@ -1,60 +1,55 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <common/debug.h> #include <cdefs.h> -#include <stdbool.h> - #include <drivers/arm/smmu_v3.h> #include <lib/mmio.h> -static inline uint32_t __init smmuv3_read_s_idr1(uintptr_t base) -{ - return mmio_read_32(base + SMMU_S_IDR1); -} +/* SMMU poll number of retries */ +#define SMMU_POLL_RETRY 1000000 -static inline uint32_t __init smmuv3_read_s_init(uintptr_t base) +static int __init smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, + uint32_t value) { - return mmio_read_32(base + SMMU_S_INIT); -} - -static inline void __init smmuv3_write_s_init(uintptr_t base, uint32_t value) -{ - mmio_write_32(base + SMMU_S_INIT, value); -} - -/* Test for pending invalidate */ -static inline bool smmuv3_inval_pending(uintptr_t base) -{ - return (smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK) != 0U; + uint32_t reg_val, retries = SMMU_POLL_RETRY; + + do { + reg_val = mmio_read_32(smmu_reg); + if ((reg_val & mask) == value) + return 0; + } while (--retries != 0U); + + ERROR("Failed to poll SMMUv3 register @%p\n", (void *)smmu_reg); + ERROR("Read value 0x%x, expected 0x%x\n", reg_val, + value == 0U ? reg_val & ~mask : reg_val | mask); + return -1; } /* * Initialize the SMMU by invalidating all secure caches and TLBs. - * - * Returns 0 on success, and -1 on failure. + * Abort all incoming transactions in order to implement a default + * deny policy on reset */ int __init smmuv3_init(uintptr_t smmu_base) { - uint32_t idr1_reg; - /* * Invalidation of secure caches and TLBs is required only if the SMMU * supports secure state. If not, it's implementation defined as to how * SMMU_S_INIT register is accessed. */ - idr1_reg = smmuv3_read_s_idr1(smmu_base); - if (((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) & - SMMU_S_IDR1_SECURE_IMPL_MASK) == 0U) { - return -1; - } + if ((mmio_read_32(smmu_base + SMMU_S_IDR1) & + SMMU_S_IDR1_SECURE_IMPL) != 0U) { - /* Initiate invalidation, and wait for it to finish */ - smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK); - while (smmuv3_inval_pending(smmu_base)) - ; + /* Initiate invalidation */ + mmio_write_32(smmu_base + SMMU_S_INIT, SMMU_S_INIT_INV_ALL); + /* Wait for global invalidation operation to finish */ + return smmuv3_poll(smmu_base + SMMU_S_INIT, + SMMU_S_INIT_INV_ALL, 0U); + } return 0; } diff --git a/include/drivers/arm/smmu_v3.h b/include/drivers/arm/smmu_v3.h index 33f3d6fc..75c9465a 100644 --- a/include/drivers/arm/smmu_v3.h +++ b/include/drivers/arm/smmu_v3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,20 +8,27 @@ #define SMMU_V3_H #include <stdint.h> - #include <lib/utils_def.h> /* SMMUv3 register offsets from device base */ +#define SMMU_GBPA U(0x0044) #define SMMU_S_IDR1 U(0x8004) #define SMMU_S_INIT U(0x803c) +#define SMMU_S_GBPA U(0x8044) + +/* SMMU_GBPA register fields */ +#define SMMU_GBPA_UPDATE (1UL << 31) +#define SMMU_GBPA_ABORT (1UL << 20) /* SMMU_S_IDR1 register fields */ -#define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31 -#define SMMU_S_IDR1_SECURE_IMPL_MASK U(0x1) +#define SMMU_S_IDR1_SECURE_IMPL (1UL << 31) /* SMMU_S_INIT register fields */ -#define SMMU_S_INIT_INV_ALL_MASK U(0x1) +#define SMMU_S_INIT_INV_ALL (1UL << 0) +/* SMMU_S_GBPA register fields */ +#define SMMU_S_GBPA_UPDATE (1UL << 31) +#define SMMU_S_GBPA_ABORT (1UL << 20) int smmuv3_init(uintptr_t smmu_base); diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 5d33954a..2d41b2db 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -438,6 +438,11 @@ else --script $(LINKERFILE) $(BUILD_DIR)/build_message.o \ $(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) endif +ifeq ($(DISABLE_BIN_GENERATION),1) + @${ECHO_BLANK_LINE} + @echo "Built $$@ successfully" + @${ECHO_BLANK_LINE} +endif $(DUMP): $(ELF) $${ECHO} " OD $$@" @@ -451,7 +456,11 @@ $(BIN): $(ELF) @${ECHO_BLANK_LINE} .PHONY: bl$(1) +ifeq ($(DISABLE_BIN_GENERATION),1) +bl$(1): $(ELF) $(DUMP) +else bl$(1): $(BIN) $(DUMP) +endif all: bl$(1) diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index be84f779..dc797ed1 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -62,6 +62,9 @@ DEBUG := 0 # Build platform DEFAULT_PLAT := fvp +# Disable the generation of the binary image (ELF only). +DISABLE_BIN_GENERATION := 0 + # Enable capability to disable authentication dynamically. Only meant for # development platforms. DYN_DISABLE_AUTH := 0 diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c index 7f28b202..3f92d377 100644 --- a/plat/arm/board/fvp/fvp_bl31_setup.c +++ b/plat/arm/board/fvp/fvp_bl31_setup.c @@ -34,7 +34,7 @@ void __init bl31_early_platform_setup2(u_register_t arg0, */ fvp_interconnect_enable(); - /* On FVP RevC, intialize SMMUv3 */ + /* On FVP RevC, initialize SMMUv3 */ if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) smmuv3_init(PLAT_FVP_SMMUV3_BASE); } diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 2c970eb8..30782d1d 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -78,7 +78,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, coreboot_serial.baud, &console); #else - console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, + console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK, PLAT_RK_UART_BAUDRATE, &console); #endif diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h index f9470e56..c0ebefc4 100644 --- a/plat/rockchip/common/include/plat_private.h +++ b/plat/rockchip/common/include/plat_private.h @@ -146,6 +146,8 @@ extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; extern const mmap_region_t plat_rk_mmap[]; +uint32_t rockchip_get_uart_base(void); + #endif /* __ASSEMBLY__ */ /****************************************************************************** diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c index baf25633..8a743bfe 100644 --- a/plat/rockchip/common/params_setup.c +++ b/plat/rockchip/common/params_setup.c @@ -28,6 +28,12 @@ static struct gpio_info *poweroff_gpio; static struct gpio_info suspend_gpio[10]; uint32_t suspend_gpio_cnt; static struct apio_info *suspend_apio; +static uint32_t rk_uart_base = PLAT_RK_UART_BASE; + +uint32_t rockchip_get_uart_base(void) +{ + return rk_uart_base; +} #if COREBOOT static int dt_process_fdt(void *blob) @@ -42,6 +48,63 @@ void *plat_get_fdt(void) return &fdt_buffer[0]; } +static void plat_rockchip_dt_process_fdt_uart(void *fdt) +{ + const char *path_name = "/chosen"; + const char *prop_name = "stdout-path"; + int node_offset; + int stdout_path_len; + const char *stdout_path; + char serial_char; + int serial_no; + uint32_t uart_base; + + node_offset = fdt_path_offset(fdt, path_name); + if (node_offset < 0) + return; + + stdout_path = fdt_getprop(fdt, node_offset, prop_name, + &stdout_path_len); + if (stdout_path == NULL) + return; + + /* + * We expect something like: + * "serial0:..."" + */ + if (strncmp("serial", stdout_path, 6) != 0) + return; + + serial_char = stdout_path[6]; + serial_no = serial_char - '0'; + + switch (serial_no) { + case 0: + uart_base = UART0_BASE; + break; + case 1: + uart_base = UART1_BASE; + break; + case 2: + uart_base = UART2_BASE; + break; +#ifdef UART3_BASE + case 3: + uart_base = UART3_BASE; + break; +#endif +#ifdef UART4_BASE + case 4: + uart_base = UART4_BASE; + break; +#endif + default: + return; + } + + rk_uart_base = uart_base; +} + static int dt_process_fdt(void *blob) { void *fdt = plat_get_fdt(); @@ -51,6 +114,8 @@ static int dt_process_fdt(void *blob) if (ret < 0) return ret; + plat_rockchip_dt_process_fdt_uart(fdt); + return 0; } #endif diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c index 7250919e..7cdbaba1 100644 --- a/plat/rockchip/common/sp_min_plat_setup.c +++ b/plat/rockchip/common/sp_min_plat_setup.c @@ -65,7 +65,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, coreboot_serial.baud, &console); #else - console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, + console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK, PLAT_RK_UART_BAUDRATE, &console); #endif VERBOSE("sp_min_setup\n"); diff --git a/plat/rockchip/rk3288/drivers/soc/soc.c b/plat/rockchip/rk3288/drivers/soc/soc.c index db90ae41..36f410b1 100644 --- a/plat/rockchip/rk3288/drivers/soc/soc.c +++ b/plat/rockchip/rk3288/drivers/soc/soc.c @@ -34,7 +34,15 @@ const mmap_region_t plat_rk_mmap[] = { MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(UART_DBG_BASE, UART_DBG_SIZE, + MAP_REGION_FLAT(UART0_BASE, UART0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART1_BASE, UART1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART2_BASE, UART2_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART3_BASE, UART3_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART4_BASE, UART4_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(CRU_BASE, CRU_SIZE, MT_DEVICE | MT_RW | MT_SECURE), diff --git a/plat/rockchip/rk3288/include/platform_def.h b/plat/rockchip/rk3288/include/platform_def.h index d9e0bc64..e24aeffa 100644 --- a/plat/rockchip/rk3288/include/platform_def.h +++ b/plat/rockchip/rk3288/include/platform_def.h @@ -87,7 +87,7 @@ #define PLAT_RK_GICD_BASE RK3288_GICD_BASE #define PLAT_RK_GICC_BASE RK3288_GICC_BASE -#define PLAT_RK_UART_BASE RK3288_UART2_BASE +#define PLAT_RK_UART_BASE UART2_BASE #define PLAT_RK_UART_CLOCK RK3288_UART_CLOCK #define PLAT_RK_UART_BAUDRATE RK3288_BAUDRATE diff --git a/plat/rockchip/rk3288/platform.mk b/plat/rockchip/rk3288/platform.mk index d2035815..1811b3af 100644 --- a/plat/rockchip/rk3288/platform.mk +++ b/plat/rockchip/rk3288/platform.mk @@ -11,6 +11,8 @@ RK_PLAT := plat/rockchip RK_PLAT_SOC := ${RK_PLAT}/${PLAT} RK_PLAT_COMMON := ${RK_PLAT}/common +DISABLE_BIN_GENERATION := 1 + PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \ -I${RK_PLAT_COMMON}/include/ \ -I${RK_PLAT_COMMON}/aarch32/ \ diff --git a/plat/rockchip/rk3288/rk3288_def.h b/plat/rockchip/rk3288/rk3288_def.h index 7b5018c7..7bff8651 100644 --- a/plat/rockchip/rk3288/rk3288_def.h +++ b/plat/rockchip/rk3288/rk3288_def.h @@ -28,8 +28,20 @@ #define DDR_PHY1_BASE 0xff640000 #define DDR_PHY1_SIZE SIZE_K(64) -#define UART_DBG_BASE 0xff690000 -#define UART_DBG_SIZE SIZE_K(64) +#define UART0_BASE 0xff180000 +#define UART0_SIZE SIZE_K(64) + +#define UART1_BASE 0xff190000 +#define UART1_SIZE SIZE_K(64) + +#define UART2_BASE 0xff690000 +#define UART2_SIZE SIZE_K(64) + +#define UART3_BASE 0xff1b0000 +#define UART3_SIZE SIZE_K(64) + +#define UART4_BASE 0xff1c0000 +#define UART4_SIZE SIZE_K(64) /* 96k instead of 64k? */ #define SRAM_BASE 0xff700000 @@ -71,7 +83,6 @@ /************************************************************************** * UART related constants **************************************************************************/ -#define RK3288_UART2_BASE UART_DBG_BASE #define RK3288_BAUDRATE 115200 #define RK3288_UART_CLOCK 24000000 diff --git a/plat/rockchip/rk3328/drivers/soc/soc.c b/plat/rockchip/rk3328/drivers/soc/soc.c index d216020c..59d85724 100644 --- a/plat/rockchip/rk3328/drivers/soc/soc.c +++ b/plat/rockchip/rk3328/drivers/soc/soc.c @@ -19,6 +19,10 @@ /* Table of regions to map using the MMU. */ const mmap_region_t plat_rk_mmap[] = { + MAP_REGION_FLAT(UART0_BASE, UART0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART1_BASE, UART1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(UART2_BASE, UART2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index b62c8686..3104d9fc 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -105,7 +105,7 @@ #define PLAT_RK_GICD_BASE RK3328_GICD_BASE #define PLAT_RK_GICC_BASE RK3328_GICC_BASE -#define PLAT_RK_UART_BASE RK3328_UART2_BASE +#define PLAT_RK_UART_BASE UART2_BASE #define PLAT_RK_UART_CLOCK RK3328_UART_CLOCK #define PLAT_RK_UART_BAUDRATE RK3328_BAUDRATE diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk index 3caa1082..3e703304 100644 --- a/plat/rockchip/rk3328/platform.mk +++ b/plat/rockchip/rk3328/platform.mk @@ -8,6 +8,8 @@ RK_PLAT := plat/rockchip RK_PLAT_SOC := ${RK_PLAT}/${PLAT} RK_PLAT_COMMON := ${RK_PLAT}/common +DISABLE_BIN_GENERATION := 1 + PLAT_INCLUDES := -Idrivers/arm/gic/common/ \ -Idrivers/arm/gic/v2/ \ -I${RK_PLAT_COMMON}/ \ @@ -40,6 +42,7 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ lib/cpus/aarch64/cortex_a53.S \ ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \ ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ + ${RK_PLAT_COMMON}/params_setup.c \ ${RK_PLAT_COMMON}/bl31_plat_setup.c \ ${RK_PLAT_COMMON}/aarch64/pmu_sram_cpus_on.S \ ${RK_PLAT_COMMON}/plat_pm.c \ diff --git a/plat/rockchip/rk3328/rk3328_def.h b/plat/rockchip/rk3328/rk3328_def.h index 0ce13ad1..60055e84 100644 --- a/plat/rockchip/rk3328/rk3328_def.h +++ b/plat/rockchip/rk3328/rk3328_def.h @@ -15,6 +15,12 @@ /* Special value used to verify platform parameters from BL2 to BL3-1 */ #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL +#define UART0_BASE 0xff110000 +#define UART0_SIZE SIZE_K(64) + +#define UART1_BASE 0xff120000 +#define UART1_SIZE SIZE_K(64) + #define UART2_BASE 0xff130000 #define UART2_SIZE SIZE_K(64) @@ -97,7 +103,6 @@ /************************************************************************** * UART related constants **************************************************************************/ -#define RK3328_UART2_BASE UART2_BASE #define RK3328_BAUDRATE 1500000 #define RK3328_UART_CLOCK 24000000 diff --git a/plat/rockchip/rk3368/drivers/soc/soc.c b/plat/rockchip/rk3368/drivers/soc/soc.c index 0c345541..7d51bb8e 100644 --- a/plat/rockchip/rk3368/drivers/soc/soc.c +++ b/plat/rockchip/rk3368/drivers/soc/soc.c @@ -30,7 +30,15 @@ const mmap_region_t plat_rk_mmap[] = { MT_MEMORY | MT_RW | MT_SECURE), MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(UART_DBG_BASE, UART_DBG_SIZE, + MAP_REGION_FLAT(UART0_BASE, UART0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART1_BASE, UART1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART2_BASE, UART2_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART3_BASE, UART3_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART4_BASE, UART4_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(CRU_BASE, CRU_SIZE, MT_DEVICE | MT_RW | MT_SECURE), diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index 815650fd..7b3cc6eb 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -106,7 +106,7 @@ #define PLAT_RK_GICD_BASE RK3368_GICD_BASE #define PLAT_RK_GICC_BASE RK3368_GICC_BASE -#define PLAT_RK_UART_BASE RK3368_UART2_BASE +#define PLAT_RK_UART_BASE UART2_BASE #define PLAT_RK_UART_CLOCK RK3368_UART_CLOCK #define PLAT_RK_UART_BAUDRATE RK3368_BAUDRATE diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk index 0495a161..51368dea 100644 --- a/plat/rockchip/rk3368/platform.mk +++ b/plat/rockchip/rk3368/platform.mk @@ -8,6 +8,8 @@ RK_PLAT := plat/rockchip RK_PLAT_SOC := ${RK_PLAT}/${PLAT} RK_PLAT_COMMON := ${RK_PLAT}/common +DISABLE_BIN_GENERATION := 1 + PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \ -I${RK_PLAT_COMMON}/include/ \ -I${RK_PLAT_COMMON}/aarch64/ \ diff --git a/plat/rockchip/rk3368/rk3368_def.h b/plat/rockchip/rk3368/rk3368_def.h index 10ac77b1..4b0fbabe 100644 --- a/plat/rockchip/rk3368/rk3368_def.h +++ b/plat/rockchip/rk3368/rk3368_def.h @@ -35,8 +35,20 @@ #define RK_INTMEM_BASE 0xff8c0000 #define RK_INTMEM_SIZE 0x10000 -#define UART_DBG_BASE 0xff690000 -#define UART_DBG_SIZE 0x10000 +#define UART0_BASE 0xff180000 +#define UART0_SIZE 0x10000 + +#define UART1_BASE 0xff190000 +#define UART1_SIZE 0x10000 + +#define UART2_BASE 0xff690000 +#define UART2_SIZE 0x10000 + +#define UART3_BASE 0xff1b0000 +#define UART3_SIZE 0x10000 + +#define UART4_BASE 0xff1c0000 +#define UART4_SIZE 0x10000 #define CRU_BASE 0xff760000 @@ -57,7 +69,6 @@ /************************************************************************** * UART related constants **************************************************************************/ -#define RK3368_UART2_BASE UART_DBG_BASE #define RK3368_BAUDRATE 115200 #define RK3368_UART_CLOCK 24000000 diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk index c73df6d7..f917f61b 100644 --- a/plat/rockchip/rk3399/platform.mk +++ b/plat/rockchip/rk3399/platform.mk @@ -8,6 +8,8 @@ RK_PLAT := plat/rockchip RK_PLAT_SOC := ${RK_PLAT}/${PLAT} RK_PLAT_COMMON := ${RK_PLAT}/common +DISABLE_BIN_GENERATION := 1 + PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \ -I${RK_PLAT_COMMON}/include/ \ -I${RK_PLAT_COMMON}/aarch64/ \ |