diff options
| -rw-r--r-- | docs/plat/rpi3.rst | 22 | ||||
| -rw-r--r-- | include/common/debug.h | 28 | ||||
| -rw-r--r-- | plat/imx/common/imx8_psci.c | 46 | ||||
| -rw-r--r-- | plat/imx/common/imx8_topology.c | 3 | ||||
| -rw-r--r-- | plat/imx/common/include/plat_imx8.h | 6 | ||||
| -rw-r--r-- | plat/imx/imx8qm/imx8qm_psci.c | 106 | ||||
| -rw-r--r-- | plat/imx/imx8qm/platform.mk | 1 | ||||
| -rw-r--r-- | plat/imx/imx8qx/imx8qx_psci.c | 60 | ||||
| -rw-r--r-- | plat/imx/imx8qx/include/platform_def.h | 2 | ||||
| -rw-r--r-- | plat/imx/imx8qx/platform.mk | 2 | ||||
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_bl31_setup.c | 8 | ||||
| -rw-r--r-- | plat/rpi3/platform.mk | 23 | ||||
| -rw-r--r-- | plat/rpi3/rpi3_bl1_setup.c | 34 | ||||
| -rw-r--r-- | plat/rpi3/rpi3_hw.h | 45 | ||||
| -rw-r--r-- | plat/rpi3/rpi3_mbox.c | 146 | ||||
| -rw-r--r-- | plat/rpi3/rpi3_pm.c | 63 | ||||
| -rw-r--r-- | plat/rpi3/rpi3_private.h | 3 | ||||
| -rw-r--r-- | services/std_svc/sdei/sdei_main.c | 44 |
18 files changed, 530 insertions, 112 deletions
diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst index 5ac90853..0ba564d8 100644 --- a/docs/plat/rpi3.rst +++ b/docs/plat/rpi3.rst @@ -196,29 +196,19 @@ Then compile TF-A. For a AArch32 kernel, use the following command line: CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ RPI3_BL33_IN_AARCH32=1 \ - BL33=../rpi3-arm-tf-bootstrap/aarch32/el2-bootstrap.bin \ - all fip + BL33=../rpi3-arm-tf-bootstrap/aarch32/el2-bootstrap.bin For a AArch64 kernel, use this other command line: .. code:: shell CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \ - BL33=../rpi3-arm-tf-bootstrap/aarch64/el2-bootstrap.bin \ - all fip + BL33=../rpi3-arm-tf-bootstrap/aarch64/el2-bootstrap.bin -Then, join BL1 and the FIP with the following instructions (replace ``release`` -by ``debug`` if you set the build option ``DEBUG=1``): - -.. code:: shell - - cp build/rpi3/release/bl1.bin bl1.pad.bin - truncate --size=131072 bl1.pad.bin - cat bl1.pad.bin build/rpi3/release/fip.bin > armstub8.bin - -The resulting file, ``armstub8.bin``, contains BL1 and the FIP in the place they -need to be for TF-A to boot correctly. Now, follow the instructions in -`Setup SD card`_. +The build system concatenates BL1 and the FIP so that the addresses match the +ones in the memory map. The resulting file is ``armstub8.bin``, located in the +build folder (e.g. ``build/rpi3/debug/armstub8.bin``). Now, follow the +instructions in `Setup SD card`_. The following build options are supported: diff --git a/include/common/debug.h b/include/common/debug.h index 3f0f84a1..99f402c0 100644 --- a/include/common/debug.h +++ b/include/common/debug.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +7,12 @@ #ifndef __DEBUG_H__ #define __DEBUG_H__ -/* The log output macros print output to the console. These macros produce +/* + * The log output macros print output to the console. These macros produce * compiled log output only if the LOG_LEVEL defined in the makefile (or the * make command line) is greater or equal than the level required for that * type of log output. + * * The format expected is the same as for printf(). For example: * INFO("Info %s.\n", "message") -> INFO: Info message. * WARN("Warning %s.\n", "message") -> WARNING: Warning message. @@ -38,34 +40,46 @@ #define LOG_MARKER_INFO "\x28" /* 40 */ #define LOG_MARKER_VERBOSE "\x32" /* 50 */ +/* + * If the log output is too low then this macro is used in place of tf_log() + * below. The intent is to get the compiler to evaluate the function call for + * type checking and format specifier correctness but let it optimize it out. + */ +#define no_tf_log(fmt, ...) \ + do { \ + if (0) { \ + tf_log(fmt, ##__VA_ARGS__); \ + } \ + } while (0) + #if LOG_LEVEL >= LOG_LEVEL_NOTICE # define NOTICE(...) tf_log(LOG_MARKER_NOTICE __VA_ARGS__) #else -# define NOTICE(...) +# define NOTICE(...) no_tf_log(LOG_MARKER_NOTICE __VA_ARGS__) #endif #if LOG_LEVEL >= LOG_LEVEL_ERROR # define ERROR(...) tf_log(LOG_MARKER_ERROR __VA_ARGS__) #else -# define ERROR(...) +# define ERROR(...) no_tf_log(LOG_MARKER_ERROR __VA_ARGS__) #endif #if LOG_LEVEL >= LOG_LEVEL_WARNING # define WARN(...) tf_log(LOG_MARKER_WARNING __VA_ARGS__) #else -# define WARN(...) +# define WARN(...) no_tf_log(LOG_MARKER_WARNING __VA_ARGS__) #endif #if LOG_LEVEL >= LOG_LEVEL_INFO # define INFO(...) tf_log(LOG_MARKER_INFO __VA_ARGS__) #else -# define INFO(...) +# define INFO(...) no_tf_log(LOG_MARKER_INFO __VA_ARGS__) #endif #if LOG_LEVEL >= LOG_LEVEL_VERBOSE # define VERBOSE(...) tf_log(LOG_MARKER_VERBOSE __VA_ARGS__) #else -# define VERBOSE(...) +# define VERBOSE(...) no_tf_log(LOG_MARKER_VERBOSE __VA_ARGS__) #endif void __dead2 do_panic(void); diff --git a/plat/imx/common/imx8_psci.c b/plat/imx/common/imx8_psci.c new file mode 100644 index 00000000..22a531bf --- /dev/null +++ b/plat/imx/common/imx8_psci.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <debug.h> +#include <plat_imx8.h> +#include <sci/sci.h> +#include <stdbool.h> + +void __dead2 imx_system_off(void) +{ + sc_pm_set_sys_power_mode(ipc_handle, SC_PM_PW_MODE_OFF); + wfi(); + ERROR("power off failed.\n"); + panic(); +} + +void __dead2 imx_system_reset(void) +{ + sc_pm_reset(ipc_handle, SC_PM_RESET_TYPE_BOARD); + wfi(); + ERROR("system reset failed.\n"); + panic(); +} + +int imx_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + /* TODO */ + return PSCI_E_INVALID_PARAMS; +} + +void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + unsigned int i; + + /* CPU & cluster off, system in retention */ + for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; + req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; +} + diff --git a/plat/imx/common/imx8_topology.c b/plat/imx/common/imx8_topology.c index bcb7d59f..64145c4c 100644 --- a/plat/imx/common/imx8_topology.c +++ b/plat/imx/common/imx8_topology.c @@ -11,7 +11,8 @@ const unsigned char imx_power_domain_tree_desc[] = { PWR_DOMAIN_AT_MAX_LVL, PLATFORM_CLUSTER_COUNT, - PLATFORM_CORE_COUNT, + PLATFORM_CLUSTER0_CORE_COUNT, + PLATFORM_CLUSTER1_CORE_COUNT, }; const unsigned char *plat_get_power_domain_tree_desc(void) diff --git a/plat/imx/common/include/plat_imx8.h b/plat/imx/common/include/plat_imx8.h index 27d4c376..a333bfbe 100644 --- a/plat/imx/common/include/plat_imx8.h +++ b/plat/imx/common/include/plat_imx8.h @@ -8,6 +8,7 @@ #define __PLAT_IMX8_H__ #include <gicv3.h> +#include <psci.h> unsigned int plat_calc_core_pos(uint64_t mpidr); void imx_mailbox_init(uintptr_t base_addr); @@ -17,4 +18,9 @@ void plat_gic_cpuif_enable(void); void plat_gic_cpuif_disable(void); void plat_gic_pcpu_init(void); +void __dead2 imx_system_off(void); +void __dead2 imx_system_reset(void); +int imx_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state); +void imx_get_sys_suspend_power_state(psci_power_state_t *req_state); #endif /*__PLAT_IMX8_H__ */ diff --git a/plat/imx/imx8qm/imx8qm_psci.c b/plat/imx/imx8qm/imx8qm_psci.c index b9b794be..c37c39c4 100644 --- a/plat/imx/imx8qm/imx8qm_psci.c +++ b/plat/imx/imx8qm/imx8qm_psci.c @@ -15,17 +15,18 @@ #include <sci/sci.h> #include <stdbool.h> +#define CORE_PWR_STATE(state) \ + ((state)->pwr_domain_state[MPIDR_AFFLVL0]) +#define CLUSTER_PWR_STATE(state) \ + ((state)->pwr_domain_state[MPIDR_AFFLVL1]) +#define SYSTEM_PWR_STATE(state) \ + ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) + const static int ap_core_index[PLATFORM_CORE_COUNT] = { SC_R_A53_0, SC_R_A53_1, SC_R_A53_2, SC_R_A53_3, SC_R_A72_0, SC_R_A72_1, }; -/* need to enable USE_COHERENT_MEM to avoid coherence issue */ -#if USE_COHERENT_MEM -static unsigned int a53_cpu_on_number __section("tzfw_coherent_mem"); -static unsigned int a72_cpu_on_number __section("tzfw_coherent_mem"); -#endif - int imx_pwr_domain_on(u_register_t mpidr) { int ret = PSCI_E_SUCCESS; @@ -37,9 +38,8 @@ int imx_pwr_domain_on(u_register_t mpidr) tf_printf("imx_pwr_domain_on cluster_id %d, cpu_id %d\n", cluster_id, cpu_id); if (cluster_id == 0) { - if (a53_cpu_on_number == 0) - sc_pm_set_resource_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_ON); - + sc_pm_set_resource_power_mode(ipc_handle, SC_R_A53, + SC_PM_PW_MODE_ON); if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], SC_PM_PW_MODE_ON) != SC_ERR_NONE) { ERROR("cluster0 core %d power on failed!\n", cpu_id); @@ -52,9 +52,8 @@ int imx_pwr_domain_on(u_register_t mpidr) ret = PSCI_E_INTERN_FAIL; } } else { - if (a72_cpu_on_number == 0) - sc_pm_set_resource_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON); - + sc_pm_set_resource_power_mode(ipc_handle, SC_R_A72, + SC_PM_PW_MODE_ON); if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id + 4], SC_PM_PW_MODE_ON) != SC_ERR_NONE) { ERROR(" cluster1 core %d power on failed!\n", cpu_id); @@ -74,17 +73,56 @@ int imx_pwr_domain_on(u_register_t mpidr) void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) { uint64_t mpidr = read_mpidr_el1(); - unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); - if (cluster_id == 0 && a53_cpu_on_number++ == 0) - cci_enable_snoop_dvm_reqs(0); - if (cluster_id == 1 && a72_cpu_on_number++ == 0) - cci_enable_snoop_dvm_reqs(1); + if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); plat_gic_pcpu_init(); plat_gic_cpuif_enable(); } +void imx_pwr_domain_off(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + plat_gic_cpuif_disable(); + sc_pm_req_cpu_low_power_mode(ipc_handle, + ap_core_index[cpu_id + cluster_id * 4], + SC_PM_PW_MODE_OFF, + SC_PM_WAKE_SRC_NONE); + if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + tf_printf("turn off cluster:%d core:%d\n", cluster_id, cpu_id); +} + +void imx_domain_suspend(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + plat_gic_cpuif_disable(); + + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + + sc_pm_set_cpu_resume_addr(ipc_handle, + ap_core_index[cpu_id + cluster_id * 4], BL31_BASE); + sc_pm_req_cpu_low_power_mode(ipc_handle, + ap_core_index[cpu_id + cluster_id * 4], + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC); +} + +void imx_domain_suspend_finish(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + + plat_gic_cpuif_enable(); +} + int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) { return PSCI_E_SUCCESS; @@ -93,22 +131,42 @@ int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) static const plat_psci_ops_t imx_plat_psci_ops = { .pwr_domain_on = imx_pwr_domain_on, .pwr_domain_on_finish = imx_pwr_domain_on_finish, + .pwr_domain_off = imx_pwr_domain_off, + .pwr_domain_suspend = imx_domain_suspend, + .pwr_domain_suspend_finish = imx_domain_suspend_finish, + .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, + .validate_power_state = imx_validate_power_state, .validate_ns_entrypoint = imx_validate_ns_entrypoint, + .system_off = imx_system_off, + .system_reset = imx_system_reset, }; int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { - uint64_t mpidr = read_mpidr_el1(); - unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); - imx_mailbox_init(sec_entrypoint); *psci_ops = &imx_plat_psci_ops; - if (cluster_id == 0) - a53_cpu_on_number++; - else - a72_cpu_on_number++; + /* Request low power mode for cluster/cci, only need to do once */ + sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_OFF); + sc_pm_req_low_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_OFF); + sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_OFF); + + /* Request RUN and LP modes for DDR, system interconnect etc. */ + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, + SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, + SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, + SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, + SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, + SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, + SC_PM_PW_MODE_STBY); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, + SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, + SC_PM_PW_MODE_STBY); return 0; } diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk index c295e14b..022ad990 100644 --- a/plat/imx/imx8qm/platform.mk +++ b/plat/imx/imx8qm/platform.mk @@ -21,6 +21,7 @@ BL31_SOURCES += plat/imx/common/lpuart_console.S \ plat/imx/imx8qm/imx8qm_bl31_setup.c \ plat/imx/imx8qm/imx8qm_psci.c \ plat/imx/common/imx8_topology.c \ + plat/imx/common/imx8_psci.c \ lib/xlat_tables/aarch64/xlat_tables.c \ lib/xlat_tables/xlat_tables_common.c \ lib/cpus/aarch64/cortex_a53.S \ diff --git a/plat/imx/imx8qx/imx8qx_psci.c b/plat/imx/imx8qx/imx8qx_psci.c index 47233dc8..f1df267a 100644 --- a/plat/imx/imx8qx/imx8qx_psci.c +++ b/plat/imx/imx8qx/imx8qx_psci.c @@ -18,13 +18,6 @@ const static int ap_core_index[PLATFORM_CORE_COUNT] = { SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3 }; -plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, - const plat_local_state_t *target_state, - unsigned int ncpu) -{ - return 0; -} - int imx_pwr_domain_on(u_register_t mpidr) { int ret = PSCI_E_SUCCESS; @@ -60,10 +53,51 @@ int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) return PSCI_E_SUCCESS; } +void imx_pwr_domain_off(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + plat_gic_cpuif_disable(); + sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_NONE); + tf_printf("turn off core:%d\n", cpu_id); +} + +void imx_domain_suspend(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + plat_gic_cpuif_disable(); + + sc_pm_set_cpu_resume_addr(ipc_handle, ap_core_index[cpu_id], BL31_BASE); + sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC); +} + +void imx_domain_suspend_finish(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id], + SC_PM_PW_MODE_ON); + + plat_gic_cpuif_enable(); +} + static const plat_psci_ops_t imx_plat_psci_ops = { .pwr_domain_on = imx_pwr_domain_on, .pwr_domain_on_finish = imx_pwr_domain_on_finish, .validate_ns_entrypoint = imx_validate_ns_entrypoint, + .system_off = imx_system_off, + .system_reset = imx_system_reset, + .pwr_domain_off = imx_pwr_domain_off, + .pwr_domain_suspend = imx_domain_suspend, + .pwr_domain_suspend_finish = imx_domain_suspend_finish, + .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, + .validate_power_state = imx_validate_power_state, }; int plat_setup_psci_ops(uintptr_t sec_entrypoint, @@ -72,5 +106,17 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, imx_mailbox_init(sec_entrypoint); *psci_ops = &imx_plat_psci_ops; + /* Request low power mode for A35 cluster, only need to do once */ + sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF); + + /* Request RUN and LP modes for DDR, system interconnect etc. */ + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, + SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, + SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, + SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, + SC_PM_PW_MODE_STBY); + return 0; } diff --git a/plat/imx/imx8qx/include/platform_def.h b/plat/imx/imx8qx/include/platform_def.h index 2cd14009..8c861746 100644 --- a/plat/imx/imx8qx/include/platform_def.h +++ b/plat/imx/imx8qx/include/platform_def.h @@ -17,6 +17,8 @@ #define PLATFORM_MAX_CPU_PER_CLUSTER 4 #define PLATFORM_CLUSTER_COUNT 1 #define PLATFORM_CORE_COUNT 4 +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 0 #define PWR_DOMAIN_AT_MAX_LVL 1 #define PLAT_MAX_PWR_LVL 2 diff --git a/plat/imx/imx8qx/platform.mk b/plat/imx/imx8qx/platform.mk index c16ce6e6..06766189 100644 --- a/plat/imx/imx8qx/platform.mk +++ b/plat/imx/imx8qx/platform.mk @@ -20,6 +20,8 @@ BL31_SOURCES += plat/imx/common/lpuart_console.S \ plat/imx/imx8qx/imx8qx_bl31_setup.c \ plat/imx/imx8qx/imx8qx_psci.c \ plat/imx/common/imx8_topology.c \ + plat/imx/common/imx8_psci.c \ + plat/common/plat_psci_common.c \ lib/xlat_tables/xlat_tables_common.c \ lib/xlat_tables/aarch64/xlat_tables.c \ lib/cpus/aarch64/cortex_a35.S \ diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 2fe4e7db..f0a7036e 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -116,9 +116,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, { plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)plat_params_from_bl2; -#if LOG_LEVEL >= LOG_LEVEL_INFO - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; -#endif image_info_t bl32_img_info = { {0} }; uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; @@ -227,8 +224,9 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, /* Early platform setup for Tegra SoCs */ plat_early_platform_setup(); - INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? - "Denver" : "ARM", read_mpidr()); + INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", + (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) + == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); } #ifdef SPD_trusty diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk index df19705e..5990f275 100644 --- a/plat/rpi3/platform.mk +++ b/plat/rpi3/platform.mk @@ -20,7 +20,8 @@ BL1_SOURCES += drivers/io/io_fip.c \ plat/common/aarch64/platform_mp_stack.S \ plat/rpi3/aarch64/plat_helpers.S \ plat/rpi3/rpi3_bl1_setup.c \ - plat/rpi3/rpi3_io_storage.c + plat/rpi3/rpi3_io_storage.c \ + plat/rpi3/rpi3_mbox.c BL2_SOURCES += common/desc_image_load.c \ drivers/io/io_fip.c \ @@ -54,6 +55,26 @@ else TF_CFLAGS_aarch64 += -mtune=cortex-a53 endif +# Platform Makefile target +# ------------------------ + +RPI3_BL1_PAD_BIN := ${BUILD_PLAT}/bl1_pad.bin +RPI3_ARMSTUB8_BIN := ${BUILD_PLAT}/armstub8.bin + +# Add new default target when compiling this platform +all: armstub + +# This target concatenates BL1 and the FIP so that the base addresses match the +# ones defined in the memory map +armstub: bl1 fip + @echo " CAT $@" + ${Q}cp ${BUILD_PLAT}/bl1.bin ${RPI3_BL1_PAD_BIN} + ${Q}truncate --size=131072 ${RPI3_BL1_PAD_BIN} + ${Q}cat ${RPI3_BL1_PAD_BIN} ${BUILD_PLAT}/fip.bin > ${RPI3_ARMSTUB8_BIN} + @${ECHO_BLANK_LINE} + @echo "Built $@ successfully" + @${ECHO_BLANK_LINE} + # Build config flags # ------------------ diff --git a/plat/rpi3/rpi3_bl1_setup.c b/plat/rpi3/rpi3_bl1_setup.c index c98715b9..39bb3325 100644 --- a/plat/rpi3/rpi3_bl1_setup.c +++ b/plat/rpi3/rpi3_bl1_setup.c @@ -7,6 +7,7 @@ #include <arch.h> #include <arch_helpers.h> #include <bl_common.h> +#include <debug.h> #include <platform_def.h> #include <xlat_mmu_helpers.h> #include <xlat_tables_defs.h> @@ -56,6 +57,39 @@ void bl1_plat_arch_setup(void) void bl1_platform_setup(void) { + uint32_t __unused rev; + int __unused rc; + + rc = rpi3_vc_hardware_get_board_revision(&rev); + + if (rc == 0) { + const char __unused *model, __unused *info; + + switch (rev) { + case 0xA02082: + model = "Raspberry Pi 3 Model B"; + info = "(1GB, Sony, UK)"; + break; + case 0xA22082: + model = "Raspberry Pi 3 Model B"; + info = "(1GB, Embest, China)"; + break; + case 0xA020D3: + model = "Raspberry Pi 3 Model B+"; + info = "(1GB, Sony, UK)"; + break; + default: + model = "Unknown"; + info = "(Unknown)"; + ERROR("rpi3: Unknown board revision 0x%08x\n", rev); + break; + } + + NOTICE("rpi3: Detected: %s %s [0x%08x]\n", model, info, rev); + } else { + ERROR("rpi3: Unable to detect board revision\n"); + } + /* Initialise the IO layer and register platform IO devices */ plat_rpi3_io_setup(); } diff --git a/plat/rpi3/rpi3_hw.h b/plat/rpi3/rpi3_hw.h index 70272e00..a83a0ad1 100644 --- a/plat/rpi3/rpi3_hw.h +++ b/plat/rpi3/rpi3_hw.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,11 +17,25 @@ #define RPI3_IO_SIZE ULL(0x01000000) /* - * Serial port (called 'Mini UART' in the BCM docucmentation). + * ARM <-> VideoCore mailboxes */ -#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) -#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) -#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) +#define RPI3_MBOX_OFFSET ULL(0x0000B880) +#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) +/* VideoCore -> ARM */ +#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) +#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) +#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) +#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) +#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) +/* ARM -> VideoCore */ +#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) +#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) +#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) +#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) +#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) +/* Mailbox status constants */ +#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ +#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ /* * Power management, reset controller, watchdog. @@ -30,11 +44,26 @@ #define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) /* Registers on top of RPI3_PM_BASE. */ #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) +#define RPI3_PM_RSTS_OFFSET ULL(0x00000020) #define RPI3_PM_WDOG_OFFSET ULL(0x00000024) /* Watchdog constants */ -#define RPI3_PM_PASSWORD ULL(0x5A000000) -#define RPI3_PM_RSTC_WRCFG_MASK ULL(0x00000030) -#define RPI3_PM_RSTC_WRCFG_FULL_RESET ULL(0x00000020) +#define RPI3_PM_PASSWORD U(0x5A000000) +#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) +#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) +/* + * The RSTS register is used by the VideoCore firmware when booting the + * Raspberry Pi to know which partition to boot from. The partition value is + * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware + * to indicate halt. + */ +#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) + +/* + * Serial port (called 'Mini UART' in the BCM docucmentation). + */ +#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) +#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) +#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) /* * Local interrupt controller diff --git a/plat/rpi3/rpi3_mbox.c b/plat/rpi3/rpi3_mbox.c new file mode 100644 index 00000000..77e17af6 --- /dev/null +++ b/plat/rpi3/rpi3_mbox.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <arch_helpers.h> +#include <debug.h> +#include <mmio.h> +#include <platform_def.h> + +#include "rpi3_hw.h" + +/* This struct must be aligned to 16 bytes */ +typedef struct __packed __aligned(16) rpi3_mbox_request { + uint32_t size; /* Buffer size in bytes */ + uint32_t code; /* Request/response code */ + uint32_t tags[0]; +} rpi3_mbox_request_t; + +#define RPI3_MBOX_BUFFER_SIZE U(256) +static uint8_t __aligned(16) rpi3_mbox_buffer[RPI3_MBOX_BUFFER_SIZE]; + +/* Constants to perform a request/check the status of a request. */ +#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000) +#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000) +#define RPI3_MBOX_REQUEST_ERROR U(0x80000001) + +/* Command constants */ +#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002) +#define RPI3_TAG_END U(0x00000000) + +#define RPI3_TAG_REQUEST U(0x00000000) +#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */ +#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF) + +#define RPI3_CHANNEL_ARM_TO_VC U(0x8) +#define RPI3_CHANNEL_MASK U(0xF) + +#define RPI3_MAILBOX_MAX_RETRIES U(1000000) + +/******************************************************************************* + * Helpers to send requests to the VideoCore using the mailboxes. + ******************************************************************************/ +static void rpi3_vc_mailbox_request_send(void) +{ + uint32_t st, data; + uintptr_t resp_addr, addr; + unsigned int retries; + + /* This is the location of the request buffer */ + addr = (uintptr_t) &rpi3_mbox_buffer; + + /* Make sure that the changes are seen by the VideoCore */ + flush_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); + + /* Wait until the outbound mailbox is empty */ + retries = 0U; + + do { + st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); + + retries++; + if (retries == RPI3_MAILBOX_MAX_RETRIES) { + ERROR("rpi3: mbox: Send request timeout\n"); + return; + } + + } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); + + /* Send base address of this message to start request */ + mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET, + RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr); + + /* Wait until the inbound mailbox isn't empty */ + retries = 0U; + + do { + st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); + + retries++; + if (retries == RPI3_MAILBOX_MAX_RETRIES) { + ERROR("rpi3: mbox: Receive response timeout\n"); + return; + } + + } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); + + /* Get location and channel */ + data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET); + + if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) { + ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data); + panic(); + } + + resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK); + if (addr != resp_addr) { + ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data); + panic(); + } + + /* Make sure that the data seen by the CPU is up to date */ + inv_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); +} + +/******************************************************************************* + * Request board revision. Returns the revision and 0 on success, -1 on error. + ******************************************************************************/ +int rpi3_vc_hardware_get_board_revision(uint32_t *revision) +{ + uint32_t tag_request_size = sizeof(uint32_t); + rpi3_mbox_request_t *req = (rpi3_mbox_request_t *) rpi3_mbox_buffer; + + assert(revision != NULL); + + VERBOSE("rpi3: mbox: Sending request at %p\n", (void *)req); + + req->size = sizeof(rpi3_mbox_buffer); + req->code = RPI3_MBOX_PROCESS_REQUEST; + + req->tags[0] = RPI3_TAG_HARDWARE_GET_BOARD_REVISION; + req->tags[1] = tag_request_size; /* Space available for the response */ + req->tags[2] = RPI3_TAG_REQUEST; + req->tags[3] = 0; /* Placeholder for the response */ + + req->tags[4] = RPI3_TAG_END; + + rpi3_vc_mailbox_request_send(); + + if (req->code != RPI3_MBOX_REQUEST_SUCCESSFUL) { + ERROR("rpi3: mbox: Code = 0x%08x\n", req->code); + return -1; + } + + if (req->tags[2] != (RPI3_TAG_IS_RESPONSE | tag_request_size)) { + ERROR("rpi3: mbox: get board revision failed (0x%08x)\n", + req->tags[2]); + return -1; + } + + *revision = req->tags[3]; + + return 0; +} diff --git a/plat/rpi3/rpi3_pm.c b/plat/rpi3/rpi3_pm.c index 1d067fb1..96948580 100644 --- a/plat/rpi3/rpi3_pm.c +++ b/plat/rpi3/rpi3_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -150,41 +150,61 @@ void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state) } /******************************************************************************* - * Platform handler to reboot the system + * Platform handlers for system reset and system off. ******************************************************************************/ -#define RESET_TIMEOUT 10 -static void __dead2 rpi3_system_reset(void) -{ - /* Setup watchdog for reset */ +/* 10 ticks (Watchdog timer = Timer clock / 16) */ +#define RESET_TIMEOUT U(10) - static const uintptr_t base = RPI3_PM_BASE; +static void __dead2 rpi3_watchdog_reset(void) +{ uint32_t rstc; - INFO("rpi3: PSCI System Reset: invoking watchdog reset\n"); - console_flush(); - rstc = mmio_read_32(base + RPI3_PM_RSTC_OFFSET); - rstc &= ~RPI3_PM_RSTC_WRCFG_MASK; - rstc |= RPI3_PM_RSTC_WRCFG_FULL_RESET; - - dmbst(); + dsbsy(); + isb(); - /* - * Watchdog timer = Timer clock / 16 - * Password (31:16) | Value (11:0) - */ - mmio_write_32(base + RPI3_PM_WDOG_OFFSET, + mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET, RPI3_PM_PASSWORD | RESET_TIMEOUT); - mmio_write_32(base + RPI3_PM_RSTC_OFFSET, - RPI3_PM_PASSWORD | rstc); + + rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET); + rstc &= ~RPI3_PM_RSTC_WRCFG_MASK; + rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET; + mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc); for (;;) { wfi(); } } +static void __dead2 rpi3_system_reset(void) +{ + INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n"); + + rpi3_watchdog_reset(); +} + +static void __dead2 rpi3_system_off(void) +{ + uint32_t rsts; + + INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n"); + + /* + * This function doesn't actually make the Raspberry Pi turn itself off, + * the hardware doesn't allow it. It simply reboots it and the RSTS + * value tells the bootcode.bin firmware not to continue the regular + * bootflow and to stay in a low power mode. + */ + + rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET); + rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT; + mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts); + + rpi3_watchdog_reset(); +} + /******************************************************************************* * Platform handlers and setup function. ******************************************************************************/ @@ -192,6 +212,7 @@ static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { .cpu_standby = rpi3_cpu_standby, .pwr_domain_on = rpi3_pwr_domain_on, .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, + .system_off = rpi3_system_off, .system_reset = rpi3_system_reset, .validate_power_state = rpi3_validate_power_state, }; diff --git a/plat/rpi3/rpi3_private.h b/plat/rpi3/rpi3_private.h index a9fbfe47..9d1744e3 100644 --- a/plat/rpi3/rpi3_private.h +++ b/plat/rpi3/rpi3_private.h @@ -33,4 +33,7 @@ uint32_t rpi3_get_spsr_for_bl33_entry(void); /* IO storage utility functions */ void plat_rpi3_io_setup(void); +/* VideoCore firmware commands */ +int rpi3_vc_hardware_get_board_revision(uint32_t *revision); + #endif /*__RPI3_PRIVATE_H__ */ diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c index d6d092de..28afc1d4 100644 --- a/services/std_svc/sdei/sdei_main.c +++ b/services/std_svc/sdei/sdei_main.c @@ -932,43 +932,43 @@ uint64_t sdei_smc_handler(uint32_t smc_fid, case SDEI_VERSION: SDEI_LOG("> VER\n"); ret = sdei_version(); - SDEI_LOG("< VER:%lx\n", ret); + SDEI_LOG("< VER:%llx\n", ret); SMC_RET1(handle, ret); case SDEI_EVENT_REGISTER: x5 = SMC_GET_GP(handle, CTX_GPREG_X5); - SDEI_LOG("> REG(n:%d e:%lx a:%lx f:%x m:%lx)\n", (int) x1, + SDEI_LOG("> REG(n:%d e:%llx a:%llx f:%x m:%llx)\n", (int) x1, x2, x3, (int) x4, x5); ret = sdei_event_register(x1, x2, x3, x4, x5); - SDEI_LOG("< REG:%ld\n", ret); + SDEI_LOG("< REG:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_EVENT_ENABLE: SDEI_LOG("> ENABLE(n:%d)\n", (int) x1); ret = sdei_event_enable(x1); - SDEI_LOG("< ENABLE:%ld\n", ret); + SDEI_LOG("< ENABLE:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_EVENT_DISABLE: SDEI_LOG("> DISABLE(n:%d)\n", (int) x1); ret = sdei_event_disable(x1); - SDEI_LOG("< DISABLE:%ld\n", ret); + SDEI_LOG("< DISABLE:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_EVENT_CONTEXT: SDEI_LOG("> CTX(p:%d):%lx\n", (int) x1, read_mpidr_el1()); ret = sdei_event_context(handle, x1); - SDEI_LOG("< CTX:%ld\n", ret); + SDEI_LOG("< CTX:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_EVENT_COMPLETE_AND_RESUME: resume = 1; case SDEI_EVENT_COMPLETE: - SDEI_LOG("> COMPLETE(r:%d sta/ep:%lx):%lx\n", resume, x1, + SDEI_LOG("> COMPLETE(r:%d sta/ep:%llx):%lx\n", resume, x1, read_mpidr_el1()); ret = sdei_event_complete(resume, x1); - SDEI_LOG("< COMPLETE:%lx\n", ret); + SDEI_LOG("< COMPLETE:%llx\n", ret); /* * Set error code only if the call failed. If the call @@ -985,19 +985,19 @@ uint64_t sdei_smc_handler(uint32_t smc_fid, case SDEI_EVENT_STATUS: SDEI_LOG("> STAT(n:%d)\n", (int) x1); ret = sdei_event_status(x1); - SDEI_LOG("< STAT:%ld\n", ret); + SDEI_LOG("< STAT:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_EVENT_GET_INFO: SDEI_LOG("> INFO(n:%d, %d)\n", (int) x1, (int) x2); ret = sdei_event_get_info(x1, x2); - SDEI_LOG("< INFO:%ld\n", ret); + SDEI_LOG("< INFO:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_EVENT_UNREGISTER: SDEI_LOG("> UNREG(n:%d)\n", (int) x1); ret = sdei_event_unregister(x1); - SDEI_LOG("< UNREG:%ld\n", ret); + SDEI_LOG("< UNREG:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_PE_UNMASK: @@ -1009,49 +1009,49 @@ uint64_t sdei_smc_handler(uint32_t smc_fid, case SDEI_PE_MASK: SDEI_LOG("> MASK:%lx\n", read_mpidr_el1()); ret = sdei_pe_mask(); - SDEI_LOG("< MASK:%ld\n", ret); + SDEI_LOG("< MASK:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_INTERRUPT_BIND: SDEI_LOG("> BIND(%d)\n", (int) x1); ret = sdei_interrupt_bind(x1); - SDEI_LOG("< BIND:%ld\n", ret); + SDEI_LOG("< BIND:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_INTERRUPT_RELEASE: SDEI_LOG("> REL(%d)\n", (int) x1); ret = sdei_interrupt_release(x1); - SDEI_LOG("< REL:%ld\n", ret); + SDEI_LOG("< REL:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_SHARED_RESET: SDEI_LOG("> S_RESET():%lx\n", read_mpidr_el1()); ret = sdei_shared_reset(); - SDEI_LOG("< S_RESET:%ld\n", ret); + SDEI_LOG("< S_RESET:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_PRIVATE_RESET: SDEI_LOG("> P_RESET():%lx\n", read_mpidr_el1()); ret = sdei_private_reset(); - SDEI_LOG("< P_RESET:%ld\n", ret); + SDEI_LOG("< P_RESET:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_EVENT_ROUTING_SET: - SDEI_LOG("> ROUTE_SET(n:%d f:%lx aff:%lx)\n", (int) x1, x2, x3); + SDEI_LOG("> ROUTE_SET(n:%d f:%llx aff:%llx)\n", (int) x1, x2, x3); ret = sdei_event_routing_set(x1, x2, x3); - SDEI_LOG("< ROUTE_SET:%ld\n", ret); + SDEI_LOG("< ROUTE_SET:%lld\n", ret); SMC_RET1(handle, ret); case SDEI_FEATURES: - SDEI_LOG("> FTRS(f:%lx)\n", x1); + SDEI_LOG("> FTRS(f:%llx)\n", x1); ret = sdei_features(x1); - SDEI_LOG("< FTRS:%lx\n", ret); + SDEI_LOG("< FTRS:%llx\n", ret); SMC_RET1(handle, ret); case SDEI_EVENT_SIGNAL: - SDEI_LOG("> SIGNAL(e:%lx t:%lx)\n", x1, x2); + SDEI_LOG("> SIGNAL(e:%llx t:%llx)\n", x1, x2); ret = sdei_signal(x1, x2); - SDEI_LOG("< SIGNAL:%ld\n", ret); + SDEI_LOG("< SIGNAL:%lld\n", ret); SMC_RET1(handle, ret); default: |