diff options
| -rw-r--r-- | drivers/arm/pl011/pl011_console.c | 7 | ||||
| -rw-r--r-- | plat/fvp/fvp_def.h | 2 | ||||
| -rw-r--r-- | plat/fvp/fvp_pm.c | 13 |
3 files changed, 8 insertions, 14 deletions
diff --git a/drivers/arm/pl011/pl011_console.c b/drivers/arm/pl011/pl011_console.c index a26c00ed..81897cab 100644 --- a/drivers/arm/pl011/pl011_console.c +++ b/drivers/arm/pl011/pl011_console.c @@ -71,7 +71,12 @@ void console_init(unsigned long base_addr) int console_putc(int c) { - assert(uart_base); + /* If the console has not been initialized then return an error + * code. Asserting here would result in recursion and stack + * exhaustion + */ + if (!uart_base) + return -1; if (c == '\n') { WAIT_UNTIL_UART_FREE(uart_base); diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h index 04ba6116..59dcc90b 100644 --- a/plat/fvp/fvp_def.h +++ b/plat/fvp/fvp_def.h @@ -137,7 +137,7 @@ #define SYS_LED_EC_MASK 0x1f /* V2M sysid register bits */ -#define SYS_ID_REV_SHIFT 27 +#define SYS_ID_REV_SHIFT 28 #define SYS_ID_HBI_SHIFT 16 #define SYS_ID_BLD_SHIFT 12 #define SYS_ID_ARCH_SHIFT 8 diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c index d7026430..03f06e7c 100644 --- a/plat/fvp/fvp_pm.c +++ b/plat/fvp/fvp_pm.c @@ -290,7 +290,7 @@ int fvp_affinst_on_finish(unsigned long mpidr, int rc = PSCI_E_SUCCESS; unsigned long linear_id, cpu_setup; mailbox_t *fvp_mboxes; - unsigned int gicd_base, gicc_base, reg_val, ectlr; + unsigned int gicd_base, gicc_base, ectlr; switch (afflvl) { @@ -354,17 +354,6 @@ int fvp_affinst_on_finish(unsigned long mpidr, /* TODO: This setup is needed only after a cold boot */ gic_pcpu_distif_setup(gicd_base); - /* Allow access to the System counter timer module */ - reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); - reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); - reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); - mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val); - mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); - - reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | - (1 << CNTNSAR_NS_SHIFT(1)); - mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); - break; default: |