diff options
| -rw-r--r-- | docs/maintainers.rst | 23 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_e1.S | 29 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_n1.S | 6 | ||||
| -rw-r--r-- | plat/allwinner/common/allwinner-common.mk | 9 | ||||
| -rw-r--r-- | plat/arm/common/sp_min/arm_sp_min.mk | 6 |
5 files changed, 62 insertions, 11 deletions
diff --git a/docs/maintainers.rst b/docs/maintainers.rst index 5449faa2..098fc5f5 100644 --- a/docs/maintainers.rst +++ b/docs/maintainers.rst @@ -11,10 +11,16 @@ Main maintainers ---------------- :M: Dan Handley <dan.handley@arm.com> :G: `danh-arm`_ -:M: Dimitris Papastamos <dimitrs.papastamos@arm.com> -:G: `dp-arm`_ :M: Soby Mathew <soby.mathew@arm.com> :G: `soby-mathew`_ +:M: Sandrine Bailleux <sandrine.bailleux@arm.com> +:G: `sandrine-bailleux-arm`_ +:M: Alexei Fedorov <alexei.fedorov@arm.com> +:G: `AlexeiFedorov`_ +:M: Paul Beesley <paul.beesley@arm.com> +:G: `pbeesley-arm`_ +:M: John Tsichritzis <john.tsichritzis@arm.com> +:G: `jts-arm`_ Allwinner ARMv8 platform port ----------------------------- @@ -260,28 +266,33 @@ Xilinx platform port :F: docs/plat/xilinx-zynqmp.rst :F: plat/xilinx/ +.. _AlexeiFedorov: https://github.com/AlexeiFedorov .. _Andre-ARM: https://github.com/Andre-ARM .. _Anson-Huang: https://github.com/Anson-Huang .. _bryanodonoghue: https://github.com/bryanodonoghue .. _b49020: https://github.com/b49020 .. _danh-arm: https://github.com/danh-arm -.. _dp-arm: https://github.com/dp-arm .. _etienne-lms: https://github.com/etienne-lms .. _glneo: https://github.com/glneo +.. _grandpaul: https://github.com/grandpaul .. _hzhuang1: https://github.com/hzhuang1 .. _JackyBai: https://github.com/JackyBai .. _jenswi-linaro: https://github.com/jenswi-linaro +.. _jts-arm: https://github.com/jts-arm +.. _jwerner-chromium: https://github.com/jwerner-chromium +.. _kostapr: https://github.com/kostapr .. _ldts: https://github.com/ldts .. _marex: https://github.com/marex -.. _niej: https://github.com/niej -.. _kostapr: https://github.com/kostapr .. _masahir0y: https://github.com/masahir0y .. _mmind: https://github.com/mmind .. _mtk09422: https://github.com/mtk09422 +.. _niej: https://github.com/niej .. _npoushin: https://github.com/npoushin +.. _pbeesley-arm: https://github.com/pbeesley-arm .. _qoriq-open-source: https://github.com/qoriq-open-source .. _remi-triplefault: https://github.com/repk .. _rockchip-linux: https://github.com/rockchip-linux +.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm .. _shawnguo2: https://github.com/shawnguo2 .. _sivadur: https://github.com/sivadur .. _smaeul: https://github.com/smaeul @@ -290,5 +301,3 @@ Xilinx platform port .. _TonyXie06: https://github.com/TonyXie06 .. _vwadekar: https://github.com/vwadekar .. _Yann-lms: https://github.com/Yann-lms -.. _grandpaul: https://github.com/grandpaul -.. _jwerner-chromium: https://github.com/jwerner-chromium diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S index d840da84..96b63cf0 100644 --- a/lib/cpus/aarch64/neoverse_e1.S +++ b/lib/cpus/aarch64/neoverse_e1.S @@ -21,6 +21,21 @@ #error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif + /* ------------------------------------------------- + * The CPU Ops reset function for Neoverse-E1. + * Shall clobber: x0-x19 + * ------------------------------------------------- + */ +func neoverse_e1_reset_func + mov x19, x30 + +#if ERRATA_DSU_936184 + bl errata_dsu_936184_wa +#endif + + ret x19 +endfunc neoverse_e1_reset_func + func neoverse_e1_cpu_pwr_dwn mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT @@ -34,6 +49,18 @@ endfunc neoverse_e1_cpu_pwr_dwn * Errata printing function for Neoverse N1. Must follow AAPCS. */ func neoverse_e1_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184 + + ldp x8, x30, [sp], #16 ret endfunc neoverse_e1_errata_report #endif @@ -50,5 +77,5 @@ func neoverse_e1_cpu_reg_dump endfunc neoverse_e1_cpu_reg_dump declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ - CPU_NO_RESET_FUNC, \ + neoverse_e1_reset_func, \ neoverse_e1_cpu_pwr_dwn diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index d685b7e9..8afc4a28 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -146,6 +146,11 @@ func neoverse_n1_reset_func msr CPUAMCNTENSET_EL0, x0 isb #endif + +#if ERRATA_DSU_936184 + bl errata_dsu_936184_wa +#endif + ret x19 endfunc neoverse_n1_reset_func @@ -181,6 +186,7 @@ func neoverse_n1_errata_report */ report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 + report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 ldp x8, x30, [sp], #16 ret diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk index f20f5157..585079b7 100644 --- a/plat/allwinner/common/allwinner-common.mk +++ b/plat/allwinner/common/allwinner-common.mk @@ -38,6 +38,12 @@ BL31_SOURCES += drivers/arm/gic/common/gic_common.c \ # The bootloader is guaranteed to only run on CPU 0 by the boot ROM. COLD_BOOT_SINGLE_CPU := 1 +# Do not enable SPE (not supported on ARM v8.0). +ENABLE_SPE_FOR_LOWER_ELS := 0 + +# Do not enable SVE (not supported on ARM v8.0). +ENABLE_SVE_FOR_NS := 0 + # Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4. ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 @@ -56,3 +62,6 @@ RESET_TO_BL31 := 1 # We are short on memory, so save 3.5KB by not having an extra coherent page. USE_COHERENT_MEM := 0 + +# This platform is single-cluster and does not require coherency setup. +WARMBOOT_ENABLE_DCACHE_EARLY := 1 diff --git a/plat/arm/common/sp_min/arm_sp_min.mk b/plat/arm/common/sp_min/arm_sp_min.mk index edab8843..dbd451ce 100644 --- a/plat/arm/common/sp_min/arm_sp_min.mk +++ b/plat/arm/common/sp_min/arm_sp_min.mk @@ -1,15 +1,16 @@ # -# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # # SP MIN source files common to ARM standard platforms -# Skip building BL1 and BL2 if RESET_TO_SP_MIN flag is set. +# Skip building BL1, BL2 and BL2U if RESET_TO_SP_MIN flag is set. ifeq (${RESET_TO_SP_MIN},1) BL1_SOURCES = BL2_SOURCES = + BL2U_SOURCES = endif BL32_SOURCES += plat/arm/common/arm_pm.c \ @@ -17,4 +18,3 @@ BL32_SOURCES += plat/arm/common/arm_pm.c \ plat/arm/common/sp_min/arm_sp_min_setup.c \ plat/common/aarch32/platform_mp_stack.S \ plat/common/plat_psci_common.c - |