diff options
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a53.h | 11 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a53.h | 12 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 10 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a75.h | 4 |
4 files changed, 21 insertions, 16 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h index a2d7ec09..3f991f34 100644 --- a/include/lib/cpus/aarch32/cortex_a53.h +++ b/include/lib/cpus/aarch32/cortex_a53.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef CORTEX_A53_H #define CORTEX_A53_H +#include <lib/utils_def.h> + /* Cortex-A53 midr for revision 0 */ #define CORTEX_A53_MIDR 0x410FD030 @@ -42,9 +44,10 @@ ******************************************************************************/ #define CORTEX_A53_CPUACTLR p15, 0, c15 -#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT 44 -#define CORTEX_A53_CPUACTLR_ENDCCASCI (1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT) -#define CORTEX_A53_CPUACTLR_DTAH (1 << 24) +#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT U(44) +#define CORTEX_A53_CPUACTLR_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT) +#define CORTEX_A53_CPUACTLR_DTAH_SHIFT U(24) +#define CORTEX_A53_CPUACTLR_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_DTAH_SHIFT) /******************************************************************************* * L2 Auxiliary Control register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 4b7d238c..cdd6f881 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef CORTEX_A53_H #define CORTEX_A53_H +#include <lib/utils_def.h> + /* Cortex-A53 midr for revision 0 */ #define CORTEX_A53_MIDR U(0x410FD030) @@ -43,13 +45,13 @@ #define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44) -#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) #define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27) -#define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) #define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25) -#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24) -#define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) /******************************************************************************* * L2 Auxiliary Control register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 5b6c9dd2..90ba3687 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,10 +26,10 @@ ******************************************************************************/ #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 -#define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) -#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) -#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) -#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) +#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h index fabc1afd..286681a9 100644 --- a/include/lib/cpus/aarch64/cortex_a75.h +++ b/include/lib/cpus/aarch64/cortex_a75.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,7 +23,7 @@ ******************************************************************************/ #define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0 -#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (1 << 35) +#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35) /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ #define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1) |