diff options
| -rw-r--r-- | Makefile | 4 | ||||
| -rw-r--r-- | bl31/aarch64/runtime_exceptions.S | 23 | ||||
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 5 | ||||
| -rw-r--r-- | bl32/tsp/aarch64/tsp_exceptions.S | 28 | ||||
| -rw-r--r-- | common/aarch32/debug.S | 2 | ||||
| -rw-r--r-- | common/aarch64/debug.S | 4 | ||||
| -rw-r--r-- | docs/firmware-design.rst | 2 | ||||
| -rw-r--r-- | include/common/asm_macros_common.S | 12 | ||||
| -rw-r--r-- | plat/hisilicon/hikey/hisi_pwrc_sram.S | 3 | ||||
| -rw-r--r-- | plat/nvidia/tegra/common/aarch64/tegra_helpers.S | 3 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t186/plat_trampoline.S | 3 | ||||
| -rw-r--r-- | plat/rockchip/common/aarch64/plat_helpers.S | 3 |
12 files changed, 46 insertions, 46 deletions
@@ -571,10 +571,10 @@ endif locate-checkpatch: ifndef CHECKPATCH - $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl") + $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/scripts/checkpatch.pl") else ifeq (,$(wildcard ${CHECKPATCH})) - $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl") + $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/scripts/checkpatch.pl") endif endif diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 45b0213d..d8fbb9b2 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -49,7 +49,8 @@ b.eq smc_handler64 /* Other kinds of synchronous exceptions are not handled */ - no_ret report_unhandled_exception + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + b report_unhandled_exception .endm @@ -152,7 +153,7 @@ vector_base runtime_exceptions */ vector_entry sync_exception_sp_el0 /* We don't expect any synchronous exceptions from EL3 */ - no_ret report_unhandled_exception + b report_unhandled_exception check_vector_size sync_exception_sp_el0 vector_entry irq_sp_el0 @@ -160,17 +161,17 @@ vector_entry irq_sp_el0 * EL3 code is non-reentrant. Any asynchronous exception is a serious * error. Loop infinitely. */ - no_ret report_unhandled_interrupt + b report_unhandled_interrupt check_vector_size irq_sp_el0 vector_entry fiq_sp_el0 - no_ret report_unhandled_interrupt + b report_unhandled_interrupt check_vector_size fiq_sp_el0 vector_entry serror_sp_el0 - no_ret report_unhandled_exception + b report_unhandled_exception check_vector_size serror_sp_el0 /* --------------------------------------------------------------------- @@ -184,19 +185,19 @@ vector_entry sync_exception_sp_elx * synchronous exception. There is a high probability that SP_EL3 is * corrupted. */ - no_ret report_unhandled_exception + b report_unhandled_exception check_vector_size sync_exception_sp_elx vector_entry irq_sp_elx - no_ret report_unhandled_interrupt + b report_unhandled_interrupt check_vector_size irq_sp_elx vector_entry fiq_sp_elx - no_ret report_unhandled_interrupt + b report_unhandled_interrupt check_vector_size fiq_sp_elx vector_entry serror_sp_elx - no_ret report_unhandled_exception + b report_unhandled_exception check_vector_size serror_sp_elx /* --------------------------------------------------------------------- @@ -226,7 +227,7 @@ vector_entry serror_aarch64 * SError exceptions from lower ELs are not currently supported. * Report their occurrence. */ - no_ret report_unhandled_exception + b report_unhandled_exception check_vector_size serror_aarch64 /* --------------------------------------------------------------------- @@ -256,7 +257,7 @@ vector_entry serror_aarch32 * SError exceptions from lower ELs are not currently supported. * Report their occurrence. */ - no_ret report_unhandled_exception + b report_unhandled_exception check_vector_size serror_aarch32 diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 2c325785..489183c5 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -43,10 +43,7 @@ msr spsr_el1, \reg2 .endm - .section .text, "ax" - .align 3 - -func tsp_entrypoint +func tsp_entrypoint _align=3 /* --------------------------------------------- * Set the exception vector to something sane. diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S index 96d958eb..4b2ad75e 100644 --- a/bl32/tsp/aarch64/tsp_exceptions.S +++ b/bl32/tsp/aarch64/tsp_exceptions.S @@ -81,19 +81,19 @@ vector_base tsp_exceptions * ----------------------------------------------------- */ vector_entry sync_exception_sp_el0 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size sync_exception_sp_el0 vector_entry irq_sp_el0 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size irq_sp_el0 vector_entry fiq_sp_el0 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size fiq_sp_el0 vector_entry serror_sp_el0 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size serror_sp_el0 @@ -103,7 +103,7 @@ vector_entry serror_sp_el0 * ----------------------------------------------------- */ vector_entry sync_exception_sp_elx - no_ret plat_panic_handler + b plat_panic_handler check_vector_size sync_exception_sp_elx vector_entry irq_sp_elx @@ -115,7 +115,7 @@ vector_entry fiq_sp_elx check_vector_size fiq_sp_elx vector_entry serror_sp_elx - no_ret plat_panic_handler + b plat_panic_handler check_vector_size serror_sp_elx @@ -125,19 +125,19 @@ vector_entry serror_sp_elx * ----------------------------------------------------- */ vector_entry sync_exception_aarch64 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size sync_exception_aarch64 vector_entry irq_aarch64 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size irq_aarch64 vector_entry fiq_aarch64 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size fiq_aarch64 vector_entry serror_aarch64 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size serror_aarch64 @@ -147,17 +147,17 @@ vector_entry serror_aarch64 * ----------------------------------------------------- */ vector_entry sync_exception_aarch32 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size sync_exception_aarch32 vector_entry irq_aarch32 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size irq_aarch32 vector_entry fiq_aarch32 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size fiq_aarch32 vector_entry serror_aarch32 - no_ret plat_panic_handler + b plat_panic_handler check_vector_size serror_aarch32 diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S index 2e60bd52..583ee4a5 100644 --- a/common/aarch32/debug.S +++ b/common/aarch32/debug.S @@ -51,7 +51,7 @@ func do_panic 1: mov lr, r6 - no_ret plat_panic_handler + b plat_panic_handler endfunc do_panic /*********************************************************** diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S index fe6a9a2d..d794d12e 100644 --- a/common/aarch64/debug.S +++ b/common/aarch64/debug.S @@ -175,6 +175,6 @@ el3_panic: _panic_handler: /* Pass to plat_panic_handler the address from where el3_panic was * called, not the address of the call from el3_panic. */ - mov x30,x6 - no_ret plat_panic_handler + mov x30, x6 + b plat_panic_handler endfunc do_panic diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst index 4c3c4204..3bca7643 100644 --- a/docs/firmware-design.rst +++ b/docs/firmware-design.rst @@ -1864,7 +1864,7 @@ A ToC entry has the following fields: `offset_address`: The offset address at which the corresponding payload data can be found. The offset is calculated from the ToC base address. `size`: The size of the corresponding payload data in bytes. - `flags`: Flags associated with this entry. Non are yet defined. + `flags`: Flags associated with this entry. None are yet defined. Firmware Image Package creation tool ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/include/common/asm_macros_common.S b/include/common/asm_macros_common.S index b529246d..dbc9e2d3 100644 --- a/include/common/asm_macros_common.S +++ b/include/common/asm_macros_common.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,9 +11,12 @@ * code into a separate text section based on the function name * to enable elimination of unused code during linking. It also adds * basic debug information to enable call stack printing most of the - * time. + * time. The optional _align parameter can be used to force a + * non-standard alignment (indicated in powers of 2). Do *not* try to + * use a raw .align directive. Since func switches to a new section, + * this would not have the desired effect. */ - .macro func _name + .macro func _name, _align=-1 /* * Add Call Frame Information entry in the .debug_frame section for * debugger consumption. This enables callstack printing in debuggers. @@ -33,6 +36,9 @@ * .debug_frame */ .cfi_startproc + .if (\_align) != -1 + .align \_align + .endif \_name: .endm diff --git a/plat/hisilicon/hikey/hisi_pwrc_sram.S b/plat/hisilicon/hikey/hisi_pwrc_sram.S index 1fb63eaf..f9e1de41 100644 --- a/plat/hisilicon/hikey/hisi_pwrc_sram.S +++ b/plat/hisilicon/hikey/hisi_pwrc_sram.S @@ -15,8 +15,7 @@ .global v7_asm .global v7_asm_end - .align 3 -func pm_asm_code +func pm_asm_code _align=3 mov x0, 0 msr oslar_el1, x0 diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index e5e51268..691b90af 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -307,8 +307,7 @@ endfunc plat_reset_handler * Secure entrypoint function for CPU boot * ---------------------------------------- */ - .align 6 -func tegra_secure_entrypoint +func tegra_secure_entrypoint _align=6 #if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S index 4841aa20..6a17c332 100644 --- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S @@ -12,11 +12,10 @@ #define TEGRA186_SMMU_CTX_SIZE 0x420 - .align 4 .globl tegra186_cpu_reset_handler /* CPU reset handler routine */ -func tegra186_cpu_reset_handler +func tegra186_cpu_reset_handler _align=4 /* * The TZRAM loses state during System Suspend. We use this * information to decide if the reset handler is running after a diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S index 1c8aefcb..abfb5a79 100644 --- a/plat/rockchip/common/aarch64/plat_helpers.S +++ b/plat/rockchip/common/aarch64/plat_helpers.S @@ -112,8 +112,7 @@ endfunc plat_crash_console_putc * cpus online or resume enterpoint * -------------------------------------------------------------------- */ - .align 16 -func platform_cpu_warmboot +func platform_cpu_warmboot _align=16 mrs x0, MPIDR_EL1 and x19, x0, #MPIDR_CPU_MASK and x20, x0, #MPIDR_CLUSTER_MASK |