diff options
28 files changed, 709 insertions, 294 deletions
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S new file mode 100644 index 00000000..9d7c5e8a --- /dev/null +++ b/bl31/aarch64/ea_delegate.S @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#include <assert_macros.S> +#include <asm_macros.S> +#include <assert_macros.S> +#include <context.h> +#include <ea_handle.h> +#include <ras_arch.h> + + + .globl handle_lower_el_ea_esb + .globl enter_lower_el_sync_ea + .globl enter_lower_el_async_ea + + +/* + * Function to delegate External Aborts synchronized by ESB instruction at EL3 + * vector entry. This function assumes GP registers x0-x29 have been saved, and + * are available for use. It delegates the handling of the EA to platform + * handler, and returns only upon successfully handling the EA; otherwise + * panics. On return from this function, the original exception handler is + * expected to resume. + */ +func handle_lower_el_ea_esb + mov x0, #ERROR_EA_ESB + mrs x1, DISR_EL1 + b ea_proceed +endfunc handle_lower_el_ea_esb + + +/* + * This function forms the tail end of Synchronous Exception entry from lower + * EL, and expects to handle only Synchronous External Aborts from lower EL. If + * any other kind of exception is detected, then this function reports unhandled + * exception. + * + * Since it's part of exception vector, this function doesn't expect any GP + * registers to have been saved. It delegates the handling of the EA to platform + * handler, and upon successfully handling the EA, exits EL3; otherwise panics. + */ +func enter_lower_el_sync_ea + /* + * Explicitly save x30 so as to free up a register and to enable + * branching. + */ + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + + mrs x30, esr_el3 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + + /* Check for I/D aborts from lower EL */ + cmp x30, #EC_IABORT_LOWER_EL + b.eq 1f + + cmp x30, #EC_DABORT_LOWER_EL + b.ne 2f + +1: + /* Test for EA bit in the instruction syndrome */ + mrs x30, esr_el3 + tbz x30, #ESR_ISS_EABORT_EA_BIT, 2f + + /* Save GP registers */ + bl save_gp_registers + + /* Setup exception class and syndrome arguments for platform handler */ + mov x0, #ERROR_EA_SYNC + mrs x1, esr_el3 + adr x30, el3_exit + b delegate_sync_ea + +2: + /* Synchronous exceptions other than the above are assumed to be EA */ + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + no_ret report_unhandled_exception +endfunc enter_lower_el_sync_ea + + +/* + * This function handles SErrors from lower ELs. + * + * Since it's part of exception vector, this function doesn't expect any GP + * registers to have been saved. It delegates the handling of the EA to platform + * handler, and upon successfully handling the EA, exits EL3; otherwise panics. + */ +func enter_lower_el_async_ea + /* + * Explicitly save x30 so as to free up a register and to enable + * branching + */ + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + + /* Save GP registers */ + bl save_gp_registers + + /* Setup exception class and syndrome arguments for platform handler */ + mov x0, #ERROR_EA_ASYNC + mrs x1, esr_el3 + adr x30, el3_exit + b delegate_async_ea +endfunc enter_lower_el_async_ea + + +/* + * Prelude for Synchronous External Abort handling. This function assumes that + * all GP registers have been saved by the caller. + * + * x0: EA reason + * x1: EA syndrome + */ +func delegate_sync_ea +#if RAS_EXTENSION + /* + * Check for Uncontainable error type. If so, route to the platform + * fatal error handler rather than the generic EA one. + */ + ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH + cmp x2, #ERROR_STATUS_SET_UC + b.ne 1f + + /* Check fault status code */ + ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH + cmp x3, #SYNC_EA_FSC + b.ne 1f + + no_ret plat_handle_uncontainable_ea +1: +#endif + + b ea_proceed +endfunc delegate_sync_ea + + +/* + * Prelude for Asynchronous External Abort handling. This function assumes that + * all GP registers have been saved by the caller. + * + * x0: EA reason + * x1: EA syndrome + */ +func delegate_async_ea +#if RAS_EXTENSION + /* + * Check for Implementation Defined Syndrome. If so, skip checking + * Uncontainable error type from the syndrome as the format is unknown. + */ + tbnz x1, #SERROR_IDS_BIT, 1f + + /* + * Check for Uncontainable error type. If so, route to the platform + * fatal error handler rather than the generic EA one. + */ + ubfx x2, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH + cmp x2, #ERROR_STATUS_UET_UC + b.ne 1f + + /* Check DFSC for SError type */ + ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH + cmp x3, #DFSC_SERROR + b.ne 1f + + no_ret plat_handle_uncontainable_ea +1: +#endif + + b ea_proceed +endfunc delegate_async_ea + + +/* + * Delegate External Abort handling to platform's EA handler. This function + * assumes that all GP registers have been saved by the caller. + * + * x0: EA reason + * x1: EA syndrome + */ +func ea_proceed + /* + * If the ESR loaded earlier is not zero, we were processing an EA + * already, and this is a double fault. + */ + ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3] + cbz x5, 1f + no_ret plat_handle_double_fault + +1: + /* Save EL3 state */ + mrs x2, spsr_el3 + mrs x3, elr_el3 + stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + + /* + * Save ESR as handling might involve lower ELs, and returning back to + * EL3 from there would trample the original ESR. + */ + mrs x4, scr_el3 + mrs x5, esr_el3 + stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + + /* + * Setup rest of arguments, and call platform External Abort handler. + * + * x0: EA reason (already in place) + * x1: Exception syndrome (already in place). + * x2: Cookie (unused for now). + * x3: Context pointer. + * x4: Flags (security state from SCR for now). + */ + mov x2, xzr + mov x3, sp + ubfx x4, x4, #0, #1 + + /* Switch to runtime stack */ + ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + msr spsel, #0 + mov sp, x5 + + mov x29, x30 +#if ENABLE_ASSERTIONS + /* Stash the stack pointer */ + mov x28, sp +#endif + bl plat_ea_handler + +#if ENABLE_ASSERTIONS + /* + * Error handling flows might involve long jumps; so upon returning from + * the platform error handler, validate that the we've completely + * unwound the stack. + */ + mov x27, sp + cmp x28, x27 + ASM_ASSERT(eq) +#endif + + /* Make SP point to context */ + msr spsel, #1 + + /* Restore EL3 state and ESR */ + ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + msr spsr_el3, x1 + msr elr_el3, x2 + + /* Restore ESR_EL3 and SCR_EL3 */ + ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + msr scr_el3, x3 + msr esr_el3, x4 + +#if ENABLE_ASSERTIONS + cmp x4, xzr + ASM_ASSERT(ne) +#endif + + /* Clear ESR storage */ + str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3] + + ret x29 +endfunc ea_proceed diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 12f9f109..54db6814 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -66,9 +66,7 @@ /* Save GP registers and restore them afterwards */ bl save_gp_registers - mov x0, #ERROR_EA_ESB - mrs x1, DISR_EL1 - bl delegate_ea + bl handle_lower_el_ea_esb bl restore_gp_registers 1: @@ -80,27 +78,6 @@ #endif .endm - /* - * Handle External Abort by delegating to the platform's EA handler. - * Once the platform handler returns, the macro exits EL3 and returns to - * where the abort was taken from. - * - * This macro assumes that x30 is available for use. - * - * 'abort_type' is a constant passed to the platform handler, indicating - * the cause of the External Abort. - */ - .macro handle_ea abort_type - /* Save GP registers */ - bl save_gp_registers - - /* Setup exception class and syndrome arguments for platform handler */ - mov x0, \abort_type - mrs x1, esr_el3 - adr x30, el3_exit - b delegate_ea - .endm - /* --------------------------------------------------------------------- * This macro handles Synchronous exceptions. * Only SMC exceptions are supported. @@ -130,23 +107,9 @@ cmp x30, #EC_AARCH64_SMC b.eq smc_handler64 - /* Check for I/D aborts from lower EL */ - cmp x30, #EC_IABORT_LOWER_EL - b.eq 1f - - cmp x30, #EC_DABORT_LOWER_EL - b.ne 2f - -1: - /* Test for EA bit in the instruction syndrome */ - mrs x30, esr_el3 - tbz x30, #ESR_ISS_EABORT_EA_BIT, 2f - handle_ea #ERROR_EA_SYNC - -2: - /* Other kinds of synchronous exceptions are not handled */ + /* Synchronous exceptions other than the above are assumed to be EA */ ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - b report_unhandled_exception + b enter_lower_el_sync_ea .endm @@ -250,7 +213,7 @@ end_vector_entry fiq_sp_el0 vector_entry serror_sp_el0 - b report_unhandled_exception + no_ret plat_handle_el3_ea end_vector_entry serror_sp_el0 /* --------------------------------------------------------------------- @@ -276,7 +239,7 @@ vector_entry fiq_sp_elx end_vector_entry fiq_sp_elx vector_entry serror_sp_elx - b report_unhandled_exception + no_ret plat_handle_el3_ea end_vector_entry serror_sp_elx /* --------------------------------------------------------------------- @@ -306,13 +269,7 @@ end_vector_entry fiq_aarch64 vector_entry serror_aarch64 msr daifclr, #DAIF_ABT_BIT - - /* - * Explicitly save x30 so as to free up a register and to enable - * branching - */ - str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - handle_ea #ERROR_EA_ASYNC + b enter_lower_el_async_ea end_vector_entry serror_aarch64 /* --------------------------------------------------------------------- @@ -342,13 +299,7 @@ end_vector_entry fiq_aarch32 vector_entry serror_aarch32 msr daifclr, #DAIF_ABT_BIT - - /* - * Explicitly save x30 so as to free up a register and to enable - * branching - */ - str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - handle_ea #ERROR_EA_ASYNC + b enter_lower_el_async_ea end_vector_entry serror_aarch32 @@ -525,62 +476,3 @@ rt_svc_fw_critical_error: msr spsel, #1 no_ret report_unhandled_exception endfunc smc_handler - -/* - * Delegate External Abort handling to platform's EA handler. This function - * assumes that all GP registers have been saved by the caller. - * - * x0: EA reason - * x1: EA syndrome - */ -func delegate_ea - /* Save EL3 state */ - mrs x2, spsr_el3 - mrs x3, elr_el3 - stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] - - /* - * Save ESR as handling might involve lower ELs, and returning back to - * EL3 from there would trample the original ESR. - */ - mrs x4, scr_el3 - mrs x5, esr_el3 - stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] - - /* - * Setup rest of arguments, and call platform External Abort handler. - * - * x0: EA reason (already in place) - * x1: Exception syndrome (already in place). - * x2: Cookie (unused for now). - * x3: Context pointer. - * x4: Flags (security state from SCR for now). - */ - mov x2, xzr - mov x3, sp - ubfx x4, x4, #0, #1 - - /* Switch to runtime stack */ - ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] - msr spsel, #0 - mov sp, x5 - - mov x29, x30 - bl plat_ea_handler - mov x30, x29 - - /* Make SP point to context */ - msr spsel, #1 - - /* Restore EL3 state */ - ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] - msr spsr_el3, x1 - msr elr_el3, x2 - - /* Restore ESR_EL3 and SCR_EL3 */ - ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] - msr scr_el3, x3 - msr esr_el3, x4 - - ret -endfunc delegate_ea diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 307ddab6..bff96538 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -19,6 +19,7 @@ BL31_SOURCES += bl31/bl31_main.c \ bl31/interrupt_mgmt.c \ bl31/aarch64/bl31_entrypoint.S \ bl31/aarch64/crash_reporting.S \ + bl31/aarch64/ea_delegate.S \ bl31/aarch64/runtime_exceptions.S \ bl31/bl31_context_mgmt.c \ common/runtime_svc.c \ diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index 603d44aa..65f39b0a 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -2850,6 +2850,106 @@ you can keep the default implementation here (which calls ``console_flush()``). If you're trying to debug crashes in BL1, you can call the console_xx_core_flush function exported by some console drivers from here. +Extternal Abort handling and RAS Support +---------------------------------------- + +Function : plat_ea_handler +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : int + Argument : uint64_t + Argument : void * + Argument : void * + Argument : uint64_t + Return : void + +This function is invoked by the RAS framework for the platform to handle an +External Abort received at EL3. The intention of the function is to attempt to +resolve the cause of External Abort and return; if that's not possible, to +initiate orderly shutdown of the system. + +The first parameter (``int ea_reason``) indicates the reason for External Abort. +Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. + +The second parameter (``uint64_t syndrome``) is the respective syndrome +presented to EL3 after having received the External Abort. Depending on the +nature of the abort (as can be inferred from the ``ea_reason`` parameter), this +can be the content of either ``ESR_EL3`` or ``DISR_EL1``. + +The third parameter (``void *cookie``) is unused for now. The fourth parameter +(``void *handle``) is a pointer to the preempted context. The fifth parameter +(``uint64_t flags``) indicates the preempted security state. These parameters +are received from the top-level exception handler. + +If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this +function iterates through RAS handlers registered by the platform. If any of the +RAS handlers resolve the External Abort, no further action is taken. + +If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers +could resolve the External Abort, the default implementation prints an error +message, and panics. + +Function : plat_handle_uncontainable_ea +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : int + Argument : uint64_t + Return : void + +This function is invoked by the RAS framework when an External Abort of +Uncontainable type is received at EL3. Due to the critical nature of +Uncontainable errors, the intention of this function is to initiate orderly +shutdown of the system, and is not expected to return. + +This function must be implemented in assembly. + +The first and second parameters are the same as that of ``plat_ea_handler``. + +The default implementation of this function calls +``report_unhandled_exception``. + +Function : plat_handle_double_fault +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : int + Argument : uint64_t + Return : void + +This function is invoked by the RAS framework when another External Abort is +received at EL3 while one is already being handled. I.e., a call to +``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of +this function is to initiate orderly shutdown of the system, and is not expected +recover or return. + +This function must be implemented in assembly. + +The first and second parameters are the same as that of ``plat_ea_handler``. + +The default implementation of this function calls +``report_unhandled_exception``. + +Function : plat_handle_el3_ea +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Return : void + +This function is invoked when an External Abort is received while executing in +EL3. Due to its critical nature, the intention of this function is to initiate +orderly shutdown of the system, and is not expected recover or return. + +This function must be implemented in assembly. + +The default implementation of this function calls +``report_unhandled_exception``. + Build flags ----------- diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h index 7d210531..6ec4da80 100644 --- a/include/lib/extensions/ras_arch.h +++ b/include/lib/extensions/ras_arch.h @@ -4,15 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __RAS_H__ -#define __RAS_H__ - -#include <arch.h> -#include <arch_helpers.h> -#include <assert.h> -#include <context.h> -#include <mmio.h> -#include <stdint.h> +#ifndef RAS_ARCH_H +#define RAS_ARCH_H /* * Size of nodes implementing Standard Error Records - currently only 4k is @@ -146,12 +139,53 @@ #define ERR_CTLR_ENABLE_FIELD(_ctlr, _field) \ ERR_CTLR_SET_FIELD(_ctlr, _field, ERR_CTLR_ ##_field ##_MASK) -/* Uncorrected error types */ +/* Uncorrected error types for Asynchronous exceptions */ #define ERROR_STATUS_UET_UC 0x0 /* Uncontainable */ #define ERROR_STATUS_UET_UEU 0x1 /* Unrecoverable */ #define ERROR_STATUS_UET_UEO 0x2 /* Restable */ #define ERROR_STATUS_UET_UER 0x3 /* Recoverable */ +/* Error types for Synchronous exceptions */ +#define ERROR_STATUS_SET_UER 0x0 /* Recoverable */ +#define ERROR_STATUS_SET_UEO 0x1 /* Restable */ +#define ERROR_STATUS_SET_UC 0x2 /* Uncontainable */ +#define ERROR_STATUS_SET_CE 0x3 /* Corrected */ + +/* Implementation Defined Syndrome bit in ESR */ +#define SERROR_IDS_BIT U(24) + +/* + * Asynchronous Error Type in exception syndrome. The field has same values in + * both DISR_EL1 and ESR_EL3 for SError. + */ +#define EABORT_AET_SHIFT U(10) +#define EABORT_AET_WIDTH U(3) +#define EABORT_AET_MASK U(0x7) + +/* DFSC field in Asynchronous exception syndrome */ +#define EABORT_DFSC_SHIFT U(0) +#define EABORT_DFSC_WIDTH U(6) +#define EABORT_DFSC_MASK U(0x3f) + +/* Synchronous Error Type in exception syndrome. */ +#define EABORT_SET_SHIFT U(11) +#define EABORT_SET_WIDTH U(2) +#define EABORT_SET_MASK U(0x3) + +/* DFSC code for SErrors */ +#define DFSC_SERROR 0x11 + +/* I/DFSC code for synchronous external abort */ +#define SYNC_EA_FSC 0x10 + +#ifndef __ASSEMBLY__ + +#include <arch.h> +#include <arch_helpers.h> +#include <assert.h> +#include <context.h> +#include <mmio.h> +#include <stdint.h> /* * Standard Error Record accessors for memory-mapped registers. @@ -221,5 +255,6 @@ static inline void ser_sys_select_record(unsigned int idx) /* Library functions to probe Standard Error Record */ int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data); int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data); +#endif /* __ASSEMBLY__ */ -#endif /* __RAS_H__ */ +#endif /* RAS_ARCH_H */ diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h index 5e1d680c..c3ae5643 100644 --- a/include/plat/arm/board/common/board_arm_def.h +++ b/include/plat/arm/board/common/board_arm_def.h @@ -28,7 +28,7 @@ # define PLATFORM_STACK_SIZE 0x400 # endif #elif defined(IMAGE_BL2U) -# define PLATFORM_STACK_SIZE 0x200 +# define PLATFORM_STACK_SIZE 0x400 #elif defined(IMAGE_BL31) #if ENABLE_SPM # define PLATFORM_STACK_SIZE 0x500 diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index e3d0edbc..12137ae4 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -241,6 +241,25 @@ ARM_EL3_TZC_DRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) +#if SEPARATE_CODE_AND_RODATA +#define ARM_MAP_BL_CODE MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) +#define ARM_MAP_BL_RO_DATA MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) +#endif +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + /* * The number of regions like RO(code), coherent and data required by * different BL stages which need to be mapped in the MMU. diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 42bbf385..506bed34 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -69,17 +69,8 @@ typedef struct arm_tzc_regions_info { /* * Utility functions common to ARM standard platforms */ -void arm_setup_page_tables(uintptr_t total_base, - size_t total_size, - uintptr_t code_start, - uintptr_t code_limit, - uintptr_t rodata_start, - uintptr_t rodata_limit -#if USE_COHERENT_MEM - , uintptr_t coh_start, - uintptr_t coh_limit -#endif -); +void arm_setup_page_tables(const mmap_region_t bl_regions[], + const mmap_region_t plat_regions[]); #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) /* @@ -292,5 +283,6 @@ void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, /* global variables */ extern plat_psci_ops_t plat_arm_psci_pm_ops; extern const mmap_region_t plat_arm_mmap[]; +extern const unsigned int arm_pm_idle_states[]; #endif /* __PLAT_ARM_H__ */ diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 725c27cb..048c58a3 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -101,6 +101,14 @@ NSRAM_SIZE, \ MT_DEVICE | MT_RW | MT_NS) +#if defined(IMAGE_BL2U) +#define CSS_MAP_SCP_BL2U MAP_REGION_FLAT( \ + SCP_BL2U_BASE, \ + SCP_BL2U_LIMIT \ + - SCP_BL2U_BASE,\ + MT_RW_DATA | MT_SECURE) +#endif + /* Platform ID address */ #define SSC_VERSION_OFFSET 0x040 diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/common/board_css_common.c index c4e83a42..40b1a275 100644 --- a/plat/arm/board/common/board_css_common.c +++ b/plat/arm/board/common/board_css_common.c @@ -53,6 +53,8 @@ const mmap_region_t plat_arm_mmap[] = { const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, CSS_MAP_DEVICE, + CSS_MAP_SCP_BL2U, + V2M_MAP_IOFPGA, SOC_CSS_MAP_DEVICE, {0} }; diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 80d4ba81..a781c4f0 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -98,7 +98,7 @@ #endif #ifdef IMAGE_BL2U -# define PLAT_ARM_MMAP_ENTRIES 4 +# define PLAT_ARM_MMAP_ENTRIES 5 # define MAX_XLAT_TABLES 3 #endif diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index c9b1a68a..94839767 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -7,6 +7,7 @@ #include <arch.h> #include <arm_def.h> #include <arm_xlat_tables.h> +#include <assert.h> #include <bl1.h> #include <bl_common.h> #include <plat_arm.h> @@ -23,6 +24,19 @@ #pragma weak bl1_plat_sec_mem_layout #pragma weak bl1_plat_prepare_exit +#define MAP_BL1_TOTAL MAP_REGION_FLAT( \ + bl1_tzram_layout.total_base, \ + bl1_tzram_layout.total_size, \ + MT_MEMORY | MT_RW | MT_SECURE) +#define MAP_BL1_CODE MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL1_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) +#define MAP_BL1_RO_DATA MAP_REGION_FLAT( \ + BL1_RO_DATA_BASE, \ + BL1_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) /* Data structure which holds the extents of the trusted SRAM for BL1*/ static meminfo_t bl1_tzram_layout; @@ -84,17 +98,19 @@ void bl1_early_platform_setup(void) *****************************************************************************/ void arm_bl1_plat_arch_setup(void) { - arm_setup_page_tables(bl1_tzram_layout.total_base, - bl1_tzram_layout.total_size, - BL_CODE_BASE, - BL1_CODE_END, - BL1_RO_DATA_BASE, - BL1_RO_DATA_END #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* ARM platforms dont use coherent memory in BL1 */ + assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL1_TOTAL, + MAP_BL1_CODE, + MAP_BL1_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); #ifdef AARCH32 enable_mmu_secure(0); #else diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c index e7247c63..1d602bb1 100644 --- a/plat/arm/common/arm_bl2_el3_setup.c +++ b/plat/arm/common/arm_bl2_el3_setup.c @@ -3,6 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ +#include <arm_def.h> +#include <assert.h> #include <generic_delay_timer.h> #include <plat_arm.h> #include <platform.h> @@ -11,6 +13,11 @@ #pragma weak bl2_el3_plat_arch_setup #pragma weak bl2_el3_plat_prepare_exit +#define MAP_BL2_EL3_TOTAL MAP_REGION_FLAT( \ + bl2_el3_tzram_layout.total_base, \ + bl2_el3_tzram_layout.total_size, \ + MT_MEMORY | MT_RW | MT_SECURE) + static meminfo_t bl2_el3_tzram_layout; /* @@ -60,17 +67,20 @@ void bl2_el3_early_platform_setup(u_register_t arg0 __unused, ******************************************************************************/ void arm_bl2_el3_plat_arch_setup(void) { - arm_setup_page_tables(bl2_el3_tzram_layout.total_base, - bl2_el3_tzram_layout.total_size, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* Ensure ARM platforms dont use coherent memory in BL2_AT_EL3 */ + assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL2_EL3_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); #ifdef AARCH32 enable_mmu_secure(0); diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 33c2fe85..88c0bc92 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -35,6 +35,11 @@ CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); #pragma weak bl2_plat_arch_setup #pragma weak bl2_plat_sec_mem_layout +#define MAP_BL2_TOTAL MAP_REGION_FLAT( \ + bl2_tzram_layout.total_base, \ + bl2_tzram_layout.total_size, \ + MT_MEMORY | MT_RW | MT_SECURE) + #if LOAD_IMAGE_V2 #pragma weak bl2_plat_handle_post_image_load @@ -232,17 +237,20 @@ void bl2_platform_setup(void) ******************************************************************************/ void arm_bl2_plat_arch_setup(void) { - arm_setup_page_tables(bl2_tzram_layout.total_base, - bl2_tzram_layout.total_size, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* Ensure ARM platforms dont use coherent memory in BL2 */ + assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL2_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); #ifdef AARCH32 enable_mmu_secure(0); diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c index dce00e5b..2bf8a936 100644 --- a/plat/arm/common/arm_bl2u_setup.c +++ b/plat/arm/common/arm_bl2u_setup.c @@ -6,6 +6,7 @@ #include <arch_helpers.h> #include <arm_def.h> +#include <assert.h> #include <bl_common.h> #include <generic_delay_timer.h> #include <plat_arm.h> @@ -18,6 +19,11 @@ #pragma weak bl2u_early_platform_setup #pragma weak bl2u_plat_arch_setup +#define MAP_BL2U_TOTAL MAP_REGION_FLAT( \ + BL2U_BASE, \ + BL2U_LIMIT - BL2U_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + /* * Perform ARM standard platform setup for BL2U */ @@ -58,18 +64,21 @@ void bl2u_early_platform_setup(struct meminfo *mem_layout, void *plat_info) ******************************************************************************/ void arm_bl2u_plat_arch_setup(void) { - arm_setup_page_tables(BL2U_BASE, - BL31_LIMIT, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + #if USE_COHERENT_MEM - , - BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* Ensure ARM platforms dont use coherent memory in BL2U */ + assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL2U_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); + #ifdef AARCH32 enable_mmu_secure(0); #else diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index b1f95c95..557854c5 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -37,6 +37,10 @@ CASSERT(BL31_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl31_base_overflows); #pragma weak bl31_plat_arch_setup #pragma weak bl31_plat_get_next_image_ep_info +#define MAP_BL31_TOTAL MAP_REGION_FLAT( \ + BL31_BASE, \ + BL31_END - BL31_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for the @@ -280,17 +284,19 @@ void bl31_plat_runtime_setup(void) ******************************************************************************/ void arm_bl31_plat_arch_setup(void) { - arm_setup_page_tables(BL31_BASE, - BL31_END - BL31_BASE, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + + const mmap_region_t bl_regions[] = { + MAP_BL31_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + ARM_MAP_BL_COHERENT_RAM, #endif - ); + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); + enable_mmu_el3(0); } diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 270abb2b..f83005f6 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -26,61 +26,34 @@ /* * Set up the page tables for the generic and platform-specific memory regions. - * The extents of the generic memory regions are specified by the function - * arguments and consist of: - * - Trusted SRAM seen by the BL image; + * The size of the Trusted SRAM seen by the BL image must be specified as well + * as an array specifying the generic memory regions which can be; * - Code section; * - Read-only data section; * - Coherent memory region, if applicable. */ -void arm_setup_page_tables(uintptr_t total_base, - size_t total_size, - uintptr_t code_start, - uintptr_t code_limit, - uintptr_t rodata_start, - uintptr_t rodata_limit -#if USE_COHERENT_MEM - , - uintptr_t coh_start, - uintptr_t coh_limit -#endif - ) + +void arm_setup_page_tables(const mmap_region_t bl_regions[], + const mmap_region_t plat_regions[]) { +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + const mmap_region_t *regions = bl_regions; + + while (regions->size != 0U) { + VERBOSE("Region: 0x%lx - 0x%lx has attributes 0x%x\n", + regions->base_va, + (regions->base_va + regions->size), + regions->attr); + regions++; + } +#endif /* * Map the Trusted SRAM with appropriate memory attributes. * Subsequent mappings will adjust the attributes for specific regions. */ - VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", - (void *) total_base, (void *) (total_base + total_size)); - mmap_add_region(total_base, total_base, - total_size, - MT_MEMORY | MT_RW | MT_SECURE); - - /* Re-map the code section */ - VERBOSE("Code region: %p - %p\n", - (void *) code_start, (void *) code_limit); - mmap_add_region(code_start, code_start, - code_limit - code_start, - MT_CODE | MT_SECURE); - - /* Re-map the read-only data section */ - VERBOSE("Read-only data region: %p - %p\n", - (void *) rodata_start, (void *) rodata_limit); - mmap_add_region(rodata_start, rodata_start, - rodata_limit - rodata_start, - MT_RO_DATA | MT_SECURE); - -#if USE_COHERENT_MEM - /* Re-map the coherent memory region */ - VERBOSE("Coherent region: %p - %p\n", - (void *) coh_start, (void *) coh_limit); - mmap_add_region(coh_start, coh_start, - coh_limit - coh_start, - MT_DEVICE | MT_RW | MT_SECURE); -#endif - + mmap_add(bl_regions); /* Now (re-)map the platform-specific memory regions */ - mmap_add(plat_arm_get_mmap()); + mmap_add(plat_regions); /* Create the page tables to reflect the above mappings */ init_xlat_tables(); diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index d0350d6c..fb183207 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -18,10 +18,6 @@ #pragma weak plat_arm_psci_override_pm_ops #pragma weak plat_arm_program_trusted_mailbox -#if ARM_RECOM_STATE_ID_ENC -extern unsigned int arm_pm_idle_states[]; -#endif /* __ARM_RECOM_STATE_ID_ENC__ */ - #if !ARM_RECOM_STATE_ID_ENC /******************************************************************************* * ARM standard platform handler called to check the validity of the power state diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c index b42e35f3..c7f317c5 100644 --- a/plat/arm/common/sp_min/arm_sp_min_setup.c +++ b/plat/arm/common/sp_min/arm_sp_min_setup.c @@ -22,6 +22,11 @@ static entry_point_info_t bl33_image_ep_info; #pragma weak sp_min_plat_arch_setup #pragma weak plat_arm_sp_min_early_platform_setup +#define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_END - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + /* * Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. @@ -196,18 +201,17 @@ void sp_min_plat_runtime_setup(void) ******************************************************************************/ void sp_min_plat_arch_setup(void) { - - arm_setup_page_tables(BL32_BASE, - (BL32_END - BL32_BASE), - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + const mmap_region_t bl_regions[] = { + MAP_BL_SP_MIN_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + ARM_MAP_BL_COHERENT_RAM, #endif - ); + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_secure(0); } diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c index 16125ad4..491705df 100644 --- a/plat/arm/common/tsp/arm_tsp_setup.c +++ b/plat/arm/common/tsp/arm_tsp_setup.c @@ -5,6 +5,7 @@ */ #include <arm_def.h> +#include <assert.h> #include <bl_common.h> #include <console.h> #include <debug.h> @@ -20,6 +21,10 @@ #pragma weak tsp_platform_setup #pragma weak tsp_plat_arch_setup +#define MAP_BL_TSP_TOTAL MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_END - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) /******************************************************************************* * Initialize the UART @@ -69,16 +74,18 @@ void tsp_platform_setup(void) ******************************************************************************/ void tsp_plat_arch_setup(void) { - arm_setup_page_tables(BL32_BASE, - (BL32_END - BL32_BASE), - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* Ensure ARM platforms dont use coherent memory in TSP */ + assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL_TSP_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el1(0); } diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S index a413f5fd..a5d26c01 100644 --- a/plat/common/aarch64/platform_helpers.S +++ b/plat/common/aarch64/platform_helpers.S @@ -20,6 +20,10 @@ .weak bl31_plat_enable_mmu .weak bl32_plat_enable_mmu + .weak plat_handle_uncontainable_ea + .weak plat_handle_double_fault + .weak plat_handle_el3_ea + #if !ENABLE_PLAT_COMPAT .globl platform_get_core_pos @@ -186,3 +190,34 @@ endfunc bl31_plat_enable_mmu func bl32_plat_enable_mmu b enable_mmu_direct_el1 endfunc bl32_plat_enable_mmu + + + /* ----------------------------------------------------- + * Platform handler for Uncontainable External Abort. + * + * x0: EA reason + * x1: EA syndrome + * ----------------------------------------------------- + */ +func plat_handle_uncontainable_ea + b report_unhandled_exception +endfunc plat_handle_uncontainable_ea + + /* ----------------------------------------------------- + * Platform handler for Double Fault. + * + * x0: EA reason + * x1: EA syndrome + * ----------------------------------------------------- + */ +func plat_handle_double_fault + b report_unhandled_exception +endfunc plat_handle_double_fault + + /* ----------------------------------------------------- + * Platform handler for EL3 External Abort. + * ----------------------------------------------------- + */ +func plat_handle_el3_ea + b report_unhandled_exception +endfunc plat_handle_el3_ea diff --git a/plat/hisilicon/hikey/include/hikey_layout.h b/plat/hisilicon/hikey/include/hikey_layout.h index 5c593fc8..acc7ad6f 100644 --- a/plat/hisilicon/hikey/include/hikey_layout.h +++ b/plat/hisilicon/hikey/include/hikey_layout.h @@ -31,20 +31,20 @@ * + loader + * ++++++++++ 0xF980_1000 * + BL1_RO + - * ++++++++++ 0xF981_0000 + * ++++++++++ 0xF981_8000 * + BL1_RW + * ++++++++++ 0xF989_8000 */ #define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) -#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) -#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ -#define BL1_RW_SIZE (0x00088000) +#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x18000) +#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_8000 */ +#define BL1_RW_SIZE (0x00080000) #define BL1_RW_LIMIT (0xF9898000) /* * Non-Secure BL1U specific defines. */ -#define NS_BL1U_BASE (0xf9818000) +#define NS_BL1U_BASE (0xf9828000) #define NS_BL1U_SIZE (0x00010000) #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk index acd1e62b..6a2474e8 100644 --- a/plat/hisilicon/hikey/platform.mk +++ b/plat/hisilicon/hikey/platform.mk @@ -134,6 +134,11 @@ AUTH_SOURCES := drivers/auth/auth_mod.c \ drivers/auth/img_parser_mod.c \ drivers/auth/tbbr/tbbr_cot.c +BL1_SOURCES += ${AUTH_SOURCES} \ + plat/common/tbbr/plat_tbbr.c \ + plat/hisilicon/hikey/hikey_tbbr.c \ + plat/hisilicon/hikey/hikey_rotpk.S + BL2_SOURCES += ${AUTH_SOURCES} \ plat/common/tbbr/plat_tbbr.c \ plat/hisilicon/hikey/hikey_tbbr.c \ @@ -143,6 +148,7 @@ ROT_KEY = $(BUILD_PLAT)/rot_key.pem ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin $(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) +$(BUILD_PLAT)/bl1/hikey_rotpk.o: $(ROTPK_HASH) $(BUILD_PLAT)/bl2/hikey_rotpk.o: $(ROTPK_HASH) certificates: $(ROT_KEY) @@ -154,8 +160,6 @@ $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ openssl dgst -sha256 -binary > $@ 2>/dev/null - -override BL1_SOURCES = endif # Enable workarounds for selected Cortex-A53 errata. diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk index 546f84aa..96427a16 100644 --- a/plat/socionext/synquacer/platform.mk +++ b/plat/socionext/synquacer/platform.mk @@ -18,6 +18,10 @@ ERRATA_A53_855873 := 1 # Libraries include lib/xlat_tables_v2/xlat_tables.mk +ifeq (${SPD},opteed) +TF_CFLAGS_aarch64 += -DBL32_BASE=0xfc000000 +endif + PLAT_PATH := plat/socionext/synquacer PLAT_INCLUDES := -I$(PLAT_PATH)/include \ -I$(PLAT_PATH)/drivers/scpi \ diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c index 461c8dec..30d06e9e 100644 --- a/plat/socionext/synquacer/sq_bl31_setup.c +++ b/plat/socionext/synquacer/sq_bl31_setup.c @@ -70,15 +70,31 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, assert(from_bl2 == NULL); assert(plat_params_from_bl2 == NULL); + /* Initialize power controller before setting up topology */ + plat_sq_pwrc_setup(); + #ifdef BL32_BASE - /* Populate entry point information for BL32 */ - SET_PARAM_HEAD(&bl32_image_ep_info, - PARAM_EP, - VERSION_1, - 0); - SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); - bl32_image_ep_info.pc = BL32_BASE; - bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); + struct draminfo di = {0}; + + scpi_get_draminfo(&di); + + /* + * Check if OP-TEE has been loaded in Secure RAM allocated + * from DRAM1 region + */ + if ((di.base1 + di.size1) <= BL32_BASE) { + NOTICE("OP-TEE has been loaded by SCP firmware\n"); + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); + } else { + NOTICE("OP-TEE has not been loaded by SCP firmware\n"); + } #endif /* BL32_BASE */ /* Populate entry point information for BL33 */ @@ -125,9 +141,6 @@ void bl31_platform_setup(void) /* Allow access to the System counter timer module */ sq_configure_sys_timer(); - - /* Initialize power controller before setting up topology */ - plat_sq_pwrc_setup(); } void bl31_plat_runtime_setup(void) diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c index ca7d214a..3de57a7c 100644 --- a/plat/ti/k3/common/k3_bl31_setup.c +++ b/plat/ti/k3/common/k3_bl31_setup.c @@ -99,12 +99,18 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { - arm_setup_page_tables(BL31_BASE, - BL31_END - BL31_BASE, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END); + + const mmap_region_t bl_regions[] = { + MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE), + MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_END, + MT_RO_DATA | MT_SECURE), + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el3(0); } diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 0b3106f7..abfb8c6f 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -179,13 +179,20 @@ void bl31_plat_arch_setup(void) plat_arm_interconnect_init(); plat_arm_interconnect_enter_coherency(); - arm_setup_page_tables(BL31_BASE, - BL31_END - BL31_BASE, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END, - BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END); + + const mmap_region_t bl_regions[] = { + MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE), + MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, + MT_RO_DATA | MT_SECURE), + MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, + MT_DEVICE | MT_RW | MT_SECURE), + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el3(0); } diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c index ecc4d0a9..52d4bf8c 100644 --- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c +++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c @@ -44,14 +44,19 @@ void tsp_platform_setup(void) ******************************************************************************/ void tsp_plat_arch_setup(void) { - arm_setup_page_tables(BL32_BASE, - BL32_END - BL32_BASE, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END, - BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END - ); + const mmap_region_t bl_regions[] = { + MAP_REGION_FLAT(BL32_BASE, BL32_END - BL32_BASE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE), + MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, + MT_RO_DATA | MT_SECURE), + MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, + MT_DEVICE | MT_RW | MT_SECURE), + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el1(0); } |