diff options
| -rw-r--r-- | plat/xilinx/zynqmp/aarch64/zynqmp_common.c | 40 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/zynqmp_def.h | 6 |
2 files changed, 10 insertions, 36 deletions
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index 562cac83..11a9e760 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -77,22 +77,6 @@ unsigned int zynqmp_get_uart_clk(void) return 100000000; } -static unsigned int zynqmp_get_system_timer_freq(void) -{ - unsigned int ver = zynqmp_get_silicon_ver(); - - switch (ver) { - case ZYNQMP_CSU_VERSION_VELOCE: - return 10000; - case ZYNQMP_CSU_VERSION_EP108: - return 4000000; - case ZYNQMP_CSU_VERSION_QEMU: - return 50000000; - } - - return 100000000; -} - unsigned int zynqmp_get_silicon_id(void) { uint32_t id; @@ -284,25 +268,21 @@ void zynqmp_config_setup(void) { zynqmp_discover_pmufw(); zynqmp_print_platform_name(); - - /* Global timer init - Program time stamp reference clk */ - uint32_t val = mmio_read_32(CRL_APB_TIMESTAMP_REF_CTRL); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - mmio_write_32(CRL_APB_TIMESTAMP_REF_CTRL, val); - - /* Program freq register in System counter and enable system counter. */ - mmio_write_32(IOU_SCNTRS_BASEFREQ, zynqmp_get_system_timer_freq()); - mmio_write_32(IOU_SCNTRS_CONTROL, IOU_SCNTRS_CONTROL_EN); - generic_delay_timer_init(); } unsigned int plat_get_syscnt_freq2(void) { - unsigned int counter_base_frequency; + unsigned int ver = zynqmp_get_silicon_ver(); - /* FIXME: Read the frequency from Frequency modes table */ - counter_base_frequency = zynqmp_get_system_timer_freq(); + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + return 10000; + case ZYNQMP_CSU_VERSION_EP108: + return 4000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 50000000; + } - return counter_base_frequency; + return mmio_read_32(IOU_SCNTRS_BASEFREQ); } diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/zynqmp_def.h index 65bc25f8..1f1bf0f4 100644 --- a/plat/xilinx/zynqmp/zynqmp_def.h +++ b/plat/xilinx/zynqmp/zynqmp_def.h @@ -69,12 +69,9 @@ /* CRL registers and bitfields */ #define CRL_APB_BASE 0xFF5E0000 #define CRL_APB_RPLL_CTRL (CRL_APB_BASE + 0x30) -#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_BASE + 0x128) #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 24) - #define CRL_APB_RPLL_CTRL_BYPASS (1 << 3) #define CRL_APB_RESET_CTRL_SOFT_RESET (1 << 4) @@ -84,11 +81,8 @@ /* system counter registers and bitfields */ #define IOU_SCNTRS_BASE 0xFF260000 -#define IOU_SCNTRS_CONTROL (IOU_SCNTRS_BASE + 0) #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) -#define IOU_SCNTRS_CONTROL_EN (1 << 0) - /* APU registers and bitfields */ #define APU_BASE 0xFD5C0000 #define APU_CONFIG_0 (APU_BASE + 0x20) |