diff options
Diffstat (limited to 'bl32/tsp')
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 19 | ||||
| -rw-r--r-- | bl32/tsp/aarch64/tsp_exceptions.S | 34 |
2 files changed, 26 insertions, 27 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 531ab9bf..453d2c14 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -391,7 +391,7 @@ tsp_sel1_intr_return: /* Should never reach here */ tsp_sel1_int_entry_panic: - b tsp_sel1_int_entry_panic + bl plat_panic_handler endfunc tsp_sel1_intr_entry /*--------------------------------------------- @@ -407,8 +407,9 @@ endfunc tsp_sel1_intr_entry func tsp_cpu_resume_entry bl tsp_cpu_resume_main restore_args_call_smc -tsp_cpu_resume_panic: - b tsp_cpu_resume_panic + + /* Should never reach here */ + bl plat_panic_handler endfunc tsp_cpu_resume_entry /*--------------------------------------------- @@ -419,8 +420,9 @@ endfunc tsp_cpu_resume_entry func tsp_fast_smc_entry bl tsp_smc_handler restore_args_call_smc -tsp_fast_smc_entry_panic: - b tsp_fast_smc_entry_panic + + /* Should never reach here */ + bl plat_panic_handler endfunc tsp_fast_smc_entry /*--------------------------------------------- @@ -435,6 +437,7 @@ func tsp_std_smc_entry bl tsp_smc_handler msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT restore_args_call_smc -tsp_std_smc_entry_panic: - b tsp_std_smc_entry_panic + + /* Should never reach here */ + bl plat_panic_handler endfunc tsp_std_smc_entry diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S index d5e089f6..edcfb718 100644 --- a/bl32/tsp/aarch64/tsp_exceptions.S +++ b/bl32/tsp/aarch64/tsp_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -108,24 +108,23 @@ tsp_exceptions: * ----------------------------------------------------- */ sync_exception_sp_el0: - wfi - b sync_exception_sp_el0 + bl plat_panic_handler check_vector_size sync_exception_sp_el0 .align 7 irq_sp_el0: - b irq_sp_el0 + bl plat_panic_handler check_vector_size irq_sp_el0 .align 7 fiq_sp_el0: - b fiq_sp_el0 + bl plat_panic_handler check_vector_size fiq_sp_el0 .align 7 serror_sp_el0: - b serror_sp_el0 + bl plat_panic_handler check_vector_size serror_sp_el0 @@ -136,8 +135,7 @@ serror_sp_el0: */ .align 7 sync_exception_sp_elx: - wfi - b sync_exception_sp_elx + bl plat_panic_handler check_vector_size sync_exception_sp_elx .align 7 @@ -152,7 +150,7 @@ fiq_sp_elx: .align 7 serror_sp_elx: - b serror_sp_elx + bl plat_panic_handler check_vector_size serror_sp_elx @@ -163,23 +161,22 @@ serror_sp_elx: */ .align 7 sync_exception_aarch64: - wfi - b sync_exception_aarch64 + bl plat_panic_handler check_vector_size sync_exception_aarch64 .align 7 irq_aarch64: - b irq_aarch64 + bl plat_panic_handler check_vector_size irq_aarch64 .align 7 fiq_aarch64: - b fiq_aarch64 + bl plat_panic_handler check_vector_size fiq_aarch64 .align 7 serror_aarch64: - b serror_aarch64 + bl plat_panic_handler check_vector_size serror_aarch64 @@ -190,22 +187,21 @@ serror_aarch64: */ .align 7 sync_exception_aarch32: - wfi - b sync_exception_aarch32 + bl plat_panic_handler check_vector_size sync_exception_aarch32 .align 7 irq_aarch32: - b irq_aarch32 + bl plat_panic_handler check_vector_size irq_aarch32 .align 7 fiq_aarch32: - b fiq_aarch32 + bl plat_panic_handler check_vector_size fiq_aarch32 .align 7 serror_aarch32: - b serror_aarch32 + bl plat_panic_handler check_vector_size serror_aarch32 .align 7 |