diff options
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/change-log.rst | 4 | ||||
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 10 | ||||
| -rw-r--r-- | docs/platform-migration-guide.rst | 13 | ||||
| -rw-r--r-- | docs/porting-guide.rst | 32 | ||||
| -rw-r--r-- | docs/user-guide.rst | 10 |
5 files changed, 51 insertions, 18 deletions
diff --git a/docs/change-log.rst b/docs/change-log.rst index 708ec057..f5ad5623 100644 --- a/docs/change-log.rst +++ b/docs/change-log.rst @@ -266,7 +266,7 @@ New features pre-empted SMC during PSCI power management requests. Issues resolved since last release -================================== +---------------------------------- - ARM TF can be built with the latest mbed TLS version (v2.4.2). The earlier version 2.3.0 cannot be used due to build warnings that the ARM TF build @@ -280,7 +280,7 @@ Issues resolved since last release shutdown request using the PSCI SYSTEM_OFF API. Known Issues -============ +------------ - Building TF with compiler optimisations disabled (-O0) fails. diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index ce564a2d..5738927c 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -51,10 +51,20 @@ For Cortex-A53, following errata build flags are defined : - ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. +- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and + link time to Cortex-A53 CPU. This needs to be enabled for some variants of + revision <= r0p4. This workaround can lead the linker to create ``*.stub`` + sections. + - ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From r0p4 and onwards, this errata is enabled by default in hardware. +- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time + to Cortex-A53 CPU. This needs to be enabled for some variants of revision + <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections + which are 4kB aligned. + - ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 CPUs. Though the erratum is present in every revision of the CPU, this workaround is only applied to CPUs from r0p3 onwards, which feature diff --git a/docs/platform-migration-guide.rst b/docs/platform-migration-guide.rst index 5e8eeba1..638033e4 100644 --- a/docs/platform-migration-guide.rst +++ b/docs/platform-migration-guide.rst @@ -146,6 +146,7 @@ for the ``plat_psci_ops`` structure which is declared as : void (*cpu_standby)(plat_local_state_t cpu_state); int (*pwr_domain_on)(u_register_t mpidr); void (*pwr_domain_off)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend_early)(const psci_power_state_t *target_state); void (*pwr_domain_suspend)(const psci_power_state_t *target_state); void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); void (*pwr_domain_suspend_finish)( @@ -170,12 +171,12 @@ convert the power-state parameter (possibly encoding a composite power state) passed in a PSCI ``CPU_SUSPEND`` to the ``psci_power_state`` format. This handler is now mandatory for PSCI ``CPU_SUSPEND`` support. -The ``plat_psci_ops`` handlers, ``pwr_domain_off`` and ``pwr_domain_suspend``, are -passed the target local state for each affected power domain. The platform -must execute operations specific to these target states. Similarly, -``pwr_domain_on_finish`` and ``pwr_domain_suspend_finish`` are passed the local -states of the affected power domains before wakeup. The platform -must execute actions to restore these power domains from these specific +The ``plat_psci_ops`` handlers, ``pwr_domain_off``, ``pwr_domain_suspend_early`` +and ``pwr_domain_suspend``, are passed the target local state for each affected +power domain. The platform must execute operations specific to these target +states. Similarly, ``pwr_domain_on_finish`` and ``pwr_domain_suspend_finish`` +are passed the local states of the affected power domains before wakeup. The +platform must execute actions to restore these power domains from these specific local states. - Difference in invocation diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index 66fe0f1d..bf8dea7b 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -60,11 +60,16 @@ A platform port must enable the Memory Management Unit (MMU) as well as the instruction and data caches for each BL stage. Setting up the translation tables is the responsibility of the platform port because memory maps differ across platforms. A memory translation library (see ``lib/xlat_tables/``) is -provided to help in this setup. Note that although this library supports -non-identity mappings, this is intended only for re-mapping peripheral physical -addresses and allows platforms with high I/O addresses to reduce their virtual -address space. All other addresses corresponding to code and data must currently -use an identity mapping. +provided to help in this setup. + +Note that although this library supports non-identity mappings, this is intended +only for re-mapping peripheral physical addresses and allows platforms with high +I/O addresses to reduce their virtual address space. All other addresses +corresponding to code and data must currently use an identity mapping. + +Also, the only translation granule size supported in Trusted Firmware is 4KB, as +various parts of the code assume that is the case. It is not possible to switch +to 16 KB or 64 KB granule sizes at the moment. In ARM standard platforms, each BL stage configures the MMU in the platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses @@ -2055,6 +2060,23 @@ power down state where as it could be either power down, retention or run state for the higher power domain levels depending on the result of state coordination. The generic code expects the handler to succeed. +plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This optional function may be used as a performance optimization to replace +or complement pwr_domain_suspend() on some platforms. Its calling semantics +are identical to pwr_domain_suspend(), except the PSCI implementation only +calls this function when suspending to a power down state, and it guarantees +that data caches are enabled. + +When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches +before calling pwr_domain_suspend(). If the target_state corresponds to a +power down state and it is safe to perform some or all of the platform +specific actions in that function with data caches enabled, it may be more +efficient to move those actions to this function. When HW_ASSISTED_COHERENCY += 1, data caches remain enabled throughout, and so there is no advantage to +moving platform specific actions to this function. + plat\_psci\_ops.pwr\_domain\_suspend() ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 6b82e3d1..ec8c2333 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -337,6 +337,11 @@ Common build options Currently, only PSCI is instrumented. Enabling this option enables the ``ENABLE_PMF`` build option as well. Default is 0. +- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling + extensions. This is an optional architectural feature available only for + AArch64 8.2 onwards. This option defaults to 1 but is automatically + disabled when the target architecture is AArch32 or AArch64 8.0/8.1. + - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection checks in GCC. Allowed values are "all", "strong" and "0" (default). "strong" is the recommended stack protection level if this feature is @@ -563,11 +568,6 @@ Common build options cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. This option defaults to 0. -- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling - extensions. This is an optional architectural feature available only for - AArch64 8.2 onwards. This option defaults to 1 but is automatically - disabled when the target architecture is AArch32 or AArch64 8.0/8.1. - ARM development platform specific build options ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |