15 files changed, 665 insertions, 0 deletions
diff --git a/include/drivers/marvell/a8k_i2c.h b/include/drivers/marvell/a8k_i2c.h
new file mode 100644
index 00000000..8a9abe8d
--- /dev/null
+++ b/include/drivers/marvell/a8k_i2c.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* This driver provides I2C support for Marvell A8K and compatible SoCs */
+
+#ifndef _A8K_I2C_H_
+#define _A8K_I2C_H_
+
+#include <stdint.h>
+
+/*
+ * Initialization, must be called once on start up, may be called
+ * repeatedly to change the speed and slave addresses.
+ */
+void i2c_init(void *i2c_base);
+
+/*
+ * Read/Write interface:
+ *   chip:    I2C chip address, range 0..127
+ *   addr:    Memory (register) address within the chip
+ *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
+ *              memories, 0 for register type devices with only one
+ *              register)
+ *   buffer:  Where to read/write the data
+ *   len:     How many bytes to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uint8_t chip,
+	     unsigned int addr, int alen, uint8_t *buffer, int len);
+
+int i2c_write(uint8_t chip,
+	      unsigned int addr, int alen, uint8_t *buffer, int len);
+#endif
diff --git a/include/drivers/marvell/addr_map.h b/include/drivers/marvell/addr_map.h
new file mode 100644
index 00000000..6b957a16
--- /dev/null
+++ b/include/drivers/marvell/addr_map.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* Address map types for Marvell address translation unit drivers */
+
+#ifndef _ADDR_MAP_H_
+#define _ADDR_MAP_H_
+
+#include <stdint.h>
+
+struct addr_map_win {
+	uint64_t base_addr;
+	uint64_t win_size;
+	uint32_t target_id;
+};
+
+#endif /* _ADDR_MAP_H_ */
diff --git a/include/drivers/marvell/amb_adec.h b/include/drivers/marvell/amb_adec.h
new file mode 100644
index 00000000..087864a4
--- /dev/null
+++ b/include/drivers/marvell/amb_adec.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */
+
+#ifndef _AMB_ADEC_H_
+#define _AMB_ADEC_H_
+
+#include <stdint.h>
+
+enum amb_attribute_ids {
+	AMB_SPI0_CS0_ID = 0x1E,
+	AMB_SPI0_CS1_ID = 0x5E,
+	AMB_SPI0_CS2_ID = 0x9E,
+	AMB_SPI0_CS3_ID = 0xDE,
+	AMB_SPI1_CS0_ID = 0x1A,
+	AMB_SPI1_CS1_ID = 0x5A,
+	AMB_SPI1_CS2_ID = 0x9A,
+	AMB_SPI1_CS3_ID = 0xDA,
+	AMB_DEV_CS0_ID = 0x3E,
+	AMB_DEV_CS1_ID = 0x3D,
+	AMB_DEV_CS2_ID = 0x3B,
+	AMB_DEV_CS3_ID = 0x37,
+	AMB_BOOT_CS_ID = 0x2f,
+	AMB_BOOT_ROM_ID = 0x1D,
+};
+
+#define AMB_MAX_WIN_ID		7
+
+int init_amb_adec(uintptr_t base);
+
+#endif /* _AMB_ADEC_H_ */
diff --git a/include/drivers/marvell/aro.h b/include/drivers/marvell/aro.h
new file mode 100644
index 00000000..3627a201
--- /dev/null
+++ b/include/drivers/marvell/aro.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2017 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+#ifndef _ARO_H_
+#define _ARO_H_
+
+enum hws_freq {
+	CPU_FREQ_2000,
+	CPU_FREQ_1800,
+	CPU_FREQ_1600,
+	CPU_FREQ_1400,
+	CPU_FREQ_1300,
+	CPU_FREQ_1200,
+	CPU_FREQ_1000,
+	CPU_FREQ_600,
+	CPU_FREQ_800,
+	DDR_FREQ_LAST,
+	DDR_FREQ_SAR
+};
+
+enum cpu_clock_freq_mode {
+	CPU_2000_DDR_1200_RCLK_1200 = 0x0,
+	CPU_2000_DDR_1050_RCLK_1050 = 0x1,
+	CPU_1600_DDR_800_RCLK_800   = 0x4,
+	CPU_1800_DDR_1200_RCLK_1200 = 0x6,
+	CPU_1800_DDR_1050_RCLK_1050 = 0x7,
+	CPU_1600_DDR_900_RCLK_900   = 0x0B,
+	CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
+	CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
+	CPU_1000_DDR_650_RCLK_650   = 0x13,
+	CPU_1300_DDR_800_RCLK_800   = 0x14,
+	CPU_1300_DDR_650_RCLK_650   = 0x17,
+	CPU_1200_DDR_800_RCLK_800   = 0x19,
+	CPU_1400_DDR_800_RCLK_800   = 0x1a,
+	CPU_600_DDR_800_RCLK_800    = 0x1B,
+	CPU_800_DDR_800_RCLK_800    = 0x1C,
+	CPU_1000_DDR_800_RCLK_800   = 0x1D,
+	CPU_DDR_RCLK_INVALID
+};
+
+int init_aro(void);
+
+#endif /* _ARO_H_ */
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
new file mode 100644
index 00000000..9e417939
--- /dev/null
+++ b/include/drivers/marvell/cache_llc.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* LLC driver is the Last Level Cache (L3C) driver
+ * for Marvell SoCs in AP806, AP807, and AP810
+ */
+
+#ifndef _CACHE_LLC_H_
+#define _CACHE_LLC_H_
+
+#define LLC_CTRL(ap)			(MVEBU_LLC_BASE(ap) + 0x100)
+#define LLC_SYNC(ap)			(MVEBU_LLC_BASE(ap) + 0x700)
+#define L2X0_INV_WAY(ap)		(MVEBU_LLC_BASE(ap) + 0x77C)
+#define L2X0_CLEAN_WAY(ap)		(MVEBU_LLC_BASE(ap) + 0x7BC)
+#define L2X0_CLEAN_INV_WAY(ap)		(MVEBU_LLC_BASE(ap) + 0x7FC)
+#define LLC_TC0_LOCK(ap)		(MVEBU_LLC_BASE(ap) + 0x920)
+
+#define MASTER_LLC_CTRL			LLC_CTRL(MVEBU_AP0)
+#define MASTER_L2X0_INV_WAY		L2X0_INV_WAY(MVEBU_AP0)
+#define MASTER_LLC_TC0_LOCK		LLC_TC0_LOCK(MVEBU_AP0)
+
+#define LLC_CTRL_EN			1
+#define LLC_EXCLUSIVE_EN		0x100
+#define LLC_WAY_MASK			0xFFFFFFFF
+
+#ifndef __ASSEMBLY__
+void llc_cache_sync(int ap_index);
+void llc_flush_all(int ap_index);
+void llc_clean_all(int ap_index);
+void llc_inv_all(int ap_index);
+void llc_disable(int ap_index);
+void llc_enable(int ap_index, int excl_mode);
+int llc_is_exclusive(int ap_index);
+void llc_runtime_enable(int ap_index);
+#endif
+
+#endif /* _CACHE_LLC_H_ */
+
diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h
new file mode 100644
index 00000000..ff30a76a
--- /dev/null
+++ b/include/drivers/marvell/ccu.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */
+
+#ifndef _CCU_H_
+#define _CCU_H_
+
+#ifndef __ASSEMBLY__
+#include <addr_map.h>
+#endif
+
+/* CCU registers definitions */
+#define CCU_WIN_CR_OFFSET(ap, win)		(MVEBU_CCU_BASE(ap) + 0x0 + \
+						(0x10 * win))
+#define CCU_TARGET_ID_OFFSET			(8)
+#define CCU_TARGET_ID_MASK			(0x7F)
+
+#define CCU_WIN_SCR_OFFSET(ap, win)		(MVEBU_CCU_BASE(ap) + 0x4 + \
+						(0x10 * win))
+#define CCU_WIN_ENA_WRITE_SECURE		(0x1)
+#define CCU_WIN_ENA_READ_SECURE			(0x2)
+
+#define CCU_WIN_ALR_OFFSET(ap, win)		(MVEBU_CCU_BASE(ap) + 0x8 + \
+						(0x10 * win))
+#define CCU_WIN_AHR_OFFSET(ap, win)		(MVEBU_CCU_BASE(ap) + 0xC + \
+						(0x10 * win))
+
+#define CCU_WIN_GCR_OFFSET(ap)			(MVEBU_CCU_BASE(ap) + 0xD0)
+#define CCU_GCR_TARGET_OFFSET			(8)
+#define CCU_GCR_TARGET_MASK			(0xFF)
+
+#define CCU_SRAM_WIN_CR				CCU_WIN_CR_OFFSET(MVEBU_AP0, 1)
+
+#ifndef __ASSEMBLY__
+int init_ccu(int);
+void ccu_win_check(struct addr_map_win *win);
+void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
+void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
+void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
+void ccu_dram_win_config(int ap_index, struct addr_map_win *win);
+void ccu_dram_target_set(int ap_index, uint32_t target);
+void ccu_save_win_all(int ap_id);
+void ccu_restore_win_all(int ap_id);
+#endif
+
+#endif /* _CCU_H_ */
diff --git a/include/drivers/marvell/gwin.h b/include/drivers/marvell/gwin.h
new file mode 100644
index 00000000..5dc9f244
--- /dev/null
+++ b/include/drivers/marvell/gwin.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* GWIN unit device driver for Marvell AP810 SoC */
+
+#ifndef _GWIN_H_
+#define _GWIN_H_
+
+#include <addr_map.h>
+
+int init_gwin(int ap_index);
+void gwin_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
+void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
+
+#endif /* _GWIN_H_ */
diff --git a/include/drivers/marvell/i2c.h b/include/drivers/marvell/i2c.h
new file mode 100644
index 00000000..bd143852
--- /dev/null
+++ b/include/drivers/marvell/i2c.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+
+void i2c_init(void);
+
+int i2c_read(uint8_t chip,
+	     unsigned int addr, int alen, uint8_t *buffer, int len);
+
+int i2c_write(uint8_t chip,
+	      unsigned int addr, int alen, uint8_t *buffer, int len);
+#endif
diff --git a/include/drivers/marvell/io_win.h b/include/drivers/marvell/io_win.h
new file mode 100644
index 00000000..4102a11a
--- /dev/null
+++ b/include/drivers/marvell/io_win.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */
+
+#ifndef _IO_WIN_H_
+#define _IO_WIN_H_
+
+#include <addr_map.h>
+
+int init_io_win(int ap_index);
+void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
+void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
+void iow_save_win_all(int ap_id);
+void iow_restore_win_all(int ap_id);
+
+#endif /* _IO_WIN_H_ */
diff --git a/include/drivers/marvell/iob.h b/include/drivers/marvell/iob.h
new file mode 100644
index 00000000..9848c0ab
--- /dev/null
+++ b/include/drivers/marvell/iob.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* IOW unit device driver for Marvell CP110 and CP115 SoCs */
+
+#ifndef _IOB_H_
+#define _IOB_H_
+
+#include <addr_map.h>
+
+enum target_ids_iob {
+	INTERNAL_TID	= 0x0,
+	MCI0_TID	= 0x1,
+	PEX1_TID	= 0x2,
+	PEX2_TID	= 0x3,
+	PEX0_TID	= 0x4,
+	NAND_TID	= 0x5,
+	RUNIT_TID	= 0x6,
+	MCI1_TID	= 0x7,
+	IOB_MAX_TID
+};
+
+int init_iob(uintptr_t base);
+void iob_cfg_space_update(int ap_idx, int cp_idx,
+			  uintptr_t base, uintptr_t new_base);
+
+#endif /* _IOB_H_ */
diff --git a/include/drivers/marvell/mci.h b/include/drivers/marvell/mci.h
new file mode 100644
index 00000000..789b3b96
--- /dev/null
+++ b/include/drivers/marvell/mci.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* MCI bus driver for Marvell ARMADA 8K and 8K+ SoCs */
+
+#ifndef _MCI_H_
+#define _MCI_H_
+
+int mci_initialize(int mci_index);
+void mci_turn_link_down(void);
+void mci_turn_link_on(void);
+int mci_get_link_status(void);
+
+#endif /* _MCI_H_ */
diff --git a/include/drivers/marvell/mochi/ap_setup.h b/include/drivers/marvell/mochi/ap_setup.h
new file mode 100644
index 00000000..41f2bac3
--- /dev/null
+++ b/include/drivers/marvell/mochi/ap_setup.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* AP8xx Marvell SoC driver */
+
+#ifndef __AP_SETUP_H__
+#define __AP_SETUP_H__
+
+void ap_init(void);
+void ap_ble_init(void);
+int ap_get_count(void);
+
+#endif /* __AP_SETUP_H__ */
diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h
new file mode 100644
index 00000000..1c88980a
--- /dev/null
+++ b/include/drivers/marvell/mochi/cp110_setup.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* CP110 Marvell SoC driver */
+
+#ifndef __CP110_SETUP_H__
+#define __CP110_SETUP_H__
+
+#include <mmio.h>
+#include <mvebu_def.h>
+
+#define MVEBU_DEVICE_ID_REG		(MVEBU_CP_DFX_OFFSET + 0x40)
+#define MVEBU_DEVICE_ID_OFFSET		(0)
+#define MVEBU_DEVICE_ID_MASK		(0xffff << MVEBU_DEVICE_ID_OFFSET)
+#define MVEBU_DEVICE_REV_OFFSET		(16)
+#define MVEBU_DEVICE_REV_MASK		(0xf << MVEBU_DEVICE_REV_OFFSET)
+#define MVEBU_70X0_DEV_ID		(0x7040)
+#define MVEBU_70X0_CP115_DEV_ID		(0x7045)
+#define MVEBU_80X0_DEV_ID		(0x8040)
+#define MVEBU_80X0_CP115_DEV_ID		(0x8045)
+#define MVEBU_CP110_SA_DEV_ID		(0x110)
+#define MVEBU_CP110_REF_ID_A1		1
+#define MVEBU_CP110_REF_ID_A2		2
+#define MAX_STREAM_ID_PER_CP		(0x10)
+#define STREAM_ID_BASE			(0x40)
+
+static inline uint32_t cp110_device_id_get(uintptr_t base)
+{
+	/* Returns:
+	 * - MVEBU_70X0_DEV_ID for A70X0 family
+	 * - MVEBU_80X0_DEV_ID for A80X0 family
+	 * - MVEBU_CP110_SA_DEV_ID for CP that connected stand alone
+	 */
+	return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) >>
+		MVEBU_DEVICE_ID_OFFSET) &
+		MVEBU_DEVICE_ID_MASK;
+}
+
+static inline uint32_t cp110_rev_id_get(uintptr_t base)
+{
+	return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) &
+		MVEBU_DEVICE_REV_MASK) >>
+		MVEBU_DEVICE_REV_OFFSET;
+}
+
+void cp110_init(uintptr_t cp110_base, uint32_t stream_id);
+void cp110_ble_init(uintptr_t cp110_base);
+
+#endif /* __CP110_SETUP_H__ */
diff --git a/include/drivers/marvell/thermal.h b/include/drivers/marvell/thermal.h
new file mode 100644
index 00000000..191f97ba
--- /dev/null
+++ b/include/drivers/marvell/thermal.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* Driver for thermal unit located in Marvell ARMADA 8K and compatible SoCs */
+
+#ifndef _THERMAL_H
+#define _THERMAL_H
+
+struct tsen_config {
+	/* thermal temperature parameters */
+	int tsen_offset;
+	int tsen_gain;
+	int tsen_divisor;
+	/* thermal data */
+	int tsen_ready;
+	void *regs_base;
+	/* thermal functionality */
+	int (*ptr_tsen_probe)(struct tsen_config *cfg);
+	int (*ptr_tsen_read)(struct tsen_config *cfg, int *temp);
+};
+
+/* Thermal driver APIs */
+int marvell_thermal_init(struct tsen_config *tsen_cfg);
+int marvell_thermal_read(struct tsen_config *tsen_cfg, int *temp);
+struct tsen_config *marvell_thermal_config_get(void);
+
+#endif /* _THERMAL_H */
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
new file mode 100644
index 00000000..65f4bbdc
--- /dev/null
+++ b/include/drivers/mmc.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MMC_H__
+#define __MMC_H__
+
+#include <stdint.h>
+#include <utils_def.h>
+
+#define MMC_BLOCK_SIZE			U(512)
+#define MMC_BLOCK_MASK			(MMC_BLOCK_SIZE - U(1))
+#define MMC_BOOT_CLK_RATE		(400 * 1000)
+
+#define MMC_CMD(_x)			U(_x)
+
+#define MMC_ACMD(_x)			U(_x)
+
+#define OCR_POWERUP			BIT(31)
+#define OCR_HCS				BIT(30)
+#define OCR_BYTE_MODE			(U(0) << 29)
+#define OCR_SECTOR_MODE			(U(2) << 29)
+#define OCR_ACCESS_MODE_MASK		(U(3) << 29)
+#define OCR_3_5_3_6			BIT(23)
+#define OCR_3_4_3_5			BIT(22)
+#define OCR_3_3_3_4			BIT(21)
+#define OCR_3_2_3_3			BIT(20)
+#define OCR_3_1_3_2			BIT(19)
+#define OCR_3_0_3_1			BIT(18)
+#define OCR_2_9_3_0			BIT(17)
+#define OCR_2_8_2_9			BIT(16)
+#define OCR_2_7_2_8			BIT(15)
+#define OCR_VDD_MIN_2V7			GENMASK(23, 15)
+#define OCR_VDD_MIN_2V0			GENMASK(14, 8)
+#define OCR_VDD_MIN_1V7			BIT(7)
+
+#define MMC_RESPONSE_R(_x)		U(_x)
+
+/* Value randomly chosen for eMMC RCA, it should be > 1 */
+#define MMC_FIX_RCA			6
+#define RCA_SHIFT_OFFSET		16
+
+#define CMD_EXTCSD_PARTITION_CONFIG	179
+#define CMD_EXTCSD_BUS_WIDTH		183
+#define CMD_EXTCSD_HS_TIMING		185
+#define CMD_EXTCSD_SEC_CNT		212
+
+#define PART_CFG_BOOT_PARTITION1_ENABLE	(U(1) << 3)
+#define PART_CFG_PARTITION1_ACCESS	(U(1) << 0)
+
+/* Values in EXT CSD register */
+#define MMC_BUS_WIDTH_1			U(0)
+#define MMC_BUS_WIDTH_4			U(1)
+#define MMC_BUS_WIDTH_8			U(2)
+#define MMC_BUS_WIDTH_DDR_4		U(5)
+#define MMC_BUS_WIDTH_DDR_8		U(6)
+#define MMC_BOOT_MODE_BACKWARD		(U(0) << 3)
+#define MMC_BOOT_MODE_HS_TIMING		(U(1) << 3)
+#define MMC_BOOT_MODE_DDR		(U(2) << 3)
+
+#define EXTCSD_SET_CMD			(U(0) << 24)
+#define EXTCSD_SET_BITS			(U(1) << 24)
+#define EXTCSD_CLR_BITS			(U(2) << 24)
+#define EXTCSD_WRITE_BYTES		(U(3) << 24)
+#define EXTCSD_CMD(x)			(((x) & 0xff) << 16)
+#define EXTCSD_VALUE(x)			(((x) & 0xff) << 8)
+#define EXTCSD_CMD_SET_NORMAL		U(1)
+
+#define CSD_TRAN_SPEED_UNIT_MASK	GENMASK(2, 0)
+#define CSD_TRAN_SPEED_MULT_MASK	GENMASK(6, 3)
+#define CSD_TRAN_SPEED_MULT_SHIFT	3
+
+#define STATUS_CURRENT_STATE(x)		(((x) & 0xf) << 9)
+#define STATUS_READY_FOR_DATA		BIT(8)
+#define STATUS_SWITCH_ERROR		BIT(7)
+#define MMC_GET_STATE(x)		(((x) >> 9) & 0xf)
+#define MMC_STATE_IDLE			0
+#define MMC_STATE_READY			1
+#define MMC_STATE_IDENT			2
+#define MMC_STATE_STBY			3
+#define MMC_STATE_TRAN			4
+#define MMC_STATE_DATA			5
+#define MMC_STATE_RCV			6
+#define MMC_STATE_PRG			7
+#define MMC_STATE_DIS			8
+#define MMC_STATE_BTST			9
+#define MMC_STATE_SLP			10
+
+#define MMC_FLAG_CMD23			(U(1) << 0)
+
+#define CMD8_CHECK_PATTERN		U(0xAA)
+#define VHS_2_7_3_6_V			BIT(8)
+
+#define SD_SCR_BUS_WIDTH_1		BIT(8)
+#define SD_SCR_BUS_WIDTH_4		BIT(10)
+
+struct mmc_cmd {
+	unsigned int	cmd_idx;
+	unsigned int	cmd_arg;
+	unsigned int	resp_type;
+	unsigned int	resp_data[4];
+};
+
+struct mmc_ops {
+	void (*init)(void);
+	int (*send_cmd)(struct mmc_cmd *cmd);
+	int (*set_ios)(unsigned int clk, unsigned int width);
+	int (*prepare)(int lba, uintptr_t buf, size_t size);
+	int (*read)(int lba, uintptr_t buf, size_t size);
+	int (*write)(int lba, const uintptr_t buf, size_t size);
+};
+
+struct mmc_csd_emmc {
+	unsigned int		not_used:		1;
+	unsigned int		crc:			7;
+	unsigned int		ecc:			2;
+	unsigned int		file_format:		2;
+	unsigned int		tmp_write_protect:	1;
+	unsigned int		perm_write_protect:	1;
+	unsigned int		copy:			1;
+	unsigned int		file_format_grp:	1;
+
+	unsigned int		reserved_1:		5;
+	unsigned int		write_bl_partial:	1;
+	unsigned int		write_bl_len:		4;
+	unsigned int		r2w_factor:		3;
+	unsigned int		default_ecc:		2;
+	unsigned int		wp_grp_enable:		1;
+
+	unsigned int		wp_grp_size:		5;
+	unsigned int		erase_grp_mult:		5;
+	unsigned int		erase_grp_size:		5;
+	unsigned int		c_size_mult:		3;
+	unsigned int		vdd_w_curr_max:		3;
+	unsigned int		vdd_w_curr_min:		3;
+	unsigned int		vdd_r_curr_max:		3;
+	unsigned int		vdd_r_curr_min:		3;
+	unsigned int		c_size_low:		2;
+
+	unsigned int		c_size_high:		10;
+	unsigned int		reserved_2:		2;
+	unsigned int		dsr_imp:		1;
+	unsigned int		read_blk_misalign:	1;
+	unsigned int		write_blk_misalign:	1;
+	unsigned int		read_bl_partial:	1;
+	unsigned int		read_bl_len:		4;
+	unsigned int		ccc:			12;
+
+	unsigned int		tran_speed:		8;
+	unsigned int		nsac:			8;
+	unsigned int		taac:			8;
+	unsigned int		reserved_3:		2;
+	unsigned int		spec_vers:		4;
+	unsigned int		csd_structure:		2;
+};
+
+struct mmc_csd_sd_v2 {
+	unsigned int		not_used:		1;
+	unsigned int		crc:			7;
+	unsigned int		reserved_1:		2;
+	unsigned int		file_format:		2;
+	unsigned int		tmp_write_protect:	1;
+	unsigned int		perm_write_protect:	1;
+	unsigned int		copy:			1;
+	unsigned int		file_format_grp:	1;
+
+	unsigned int		reserved_2:		5;
+	unsigned int		write_bl_partial:	1;
+	unsigned int		write_bl_len:		4;
+	unsigned int		r2w_factor:		3;
+	unsigned int		reserved_3:		2;
+	unsigned int		wp_grp_enable:		1;
+
+	unsigned int		wp_grp_size:		7;
+	unsigned int		sector_size:		7;
+	unsigned int		erase_block_en:		1;
+	unsigned int		reserved_4:		1;
+	unsigned int		c_size_low:		16;
+
+	unsigned int		c_size_high:		6;
+	unsigned int		reserved_5:		6;
+	unsigned int		dsr_imp:		1;
+	unsigned int		read_blk_misalign:	1;
+	unsigned int		write_blk_misalign:	1;
+	unsigned int		read_bl_partial:	1;
+	unsigned int		read_bl_len:		4;
+	unsigned int		ccc:			12;
+
+	unsigned int		tran_speed:		8;
+	unsigned int		nsac:			8;
+	unsigned int		taac:			8;
+	unsigned int		reserved_6:		6;
+	unsigned int		csd_structure:		2;
+};
+
+enum mmc_device_type {
+	MMC_IS_EMMC,
+	MMC_IS_SD,
+	MMC_IS_SD_HC,
+};
+
+struct mmc_device_info {
+	unsigned long long	device_size;	/* Size of device in bytes */
+	unsigned int		block_size;	/* Block size in bytes */
+	unsigned int		max_bus_freq;	/* Max bus freq in Hz */
+	enum mmc_device_type	mmc_dev_type;	/* Type of MMC */
+};
+
+size_t mmc_read_blocks(unsigned int lba, uintptr_t buf, size_t size);
+size_t mmc_write_blocks(unsigned int lba, const uintptr_t buf, size_t size);
+size_t mmc_erase_blocks(unsigned int lba, size_t size);
+size_t mmc_rpmb_read_blocks(unsigned int lba, uintptr_t buf, size_t size);
+size_t mmc_rpmb_write_blocks(unsigned int lba, const uintptr_t buf,
+			     size_t size);
+size_t mmc_rpmb_erase_blocks(unsigned int lba, size_t size);
+int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
+	     unsigned int width, unsigned int flags,
+	     struct mmc_device_info *device_info);
+
+#endif	/* __MMC_H__ */