diff options
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch32/arch.h | 39 | ||||
| -rw-r--r-- | include/lib/aarch32/arch_helpers.h | 1 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 52 |
3 files changed, 88 insertions, 4 deletions
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index d70e4c7a..661dbf81 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -101,14 +101,19 @@ #define SCTLR_TRE_BIT (1 << 28) #define SCTLR_AFE_BIT (1 << 29) #define SCTLR_TE_BIT (1 << 30) +#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ + SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) /* SDCR definitions */ #define SDCR_SPD(x) ((x) << 14) #define SDCR_SPD_LEGACY 0x0 #define SDCR_SPD_DISABLE 0x2 #define SDCR_SPD_ENABLE 0x3 +#define SDCR_RESET_VAL 0x0 +#if !ERROR_DEPRECATED #define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE) +#endif /* HSCTLR definitions */ #define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \ @@ -145,6 +150,7 @@ #define SCR_IRQ_BIT (1 << 1) #define SCR_NS_BIT (1 << 0) #define SCR_VALID_BIT_MASK 0x33ff +#define SCR_RESET_VAL 0x0 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) @@ -152,9 +158,10 @@ #define HCR_AMO_BIT (1 << 5) #define HCR_IMO_BIT (1 << 4) #define HCR_FMO_BIT (1 << 3) +#define HCR_RESET_VAL 0x0 /* CNTHCTL definitions */ -#define EVNTEN_BIT (1 << 2) +#define CNTHCTL_RESET_VAL 0x0 #define PL1PCEN_BIT (1 << 1) #define PL1PCTEN_BIT (1 << 0) @@ -169,16 +176,42 @@ #define EVNTI_MASK 0xf /* HCPTR definitions */ +#define HCPTR_RES1 ((1 << 13) | (1<<12) | 0x3ff) #define TCPAC_BIT (1 << 31) #define TTA_BIT (1 << 20) #define TCP11_BIT (1 << 10) #define TCP10_BIT (1 << 10) +#define HCPTR_RESET_VAL HCPTR_RES1 + +/* VTTBR defintions */ +#define VTTBR_RESET_VAL ULL(0x0) +#define VTTBR_VMID_MASK ULL(0xff) +#define VTTBR_VMID_SHIFT 48 +#define VTTBR_BADDR_MASK 0xffffffffffff +#define VTTBR_BADDR_SHIFT 0 + +/* HDCR definitions */ +#define HDCR_RESET_VAL 0x0 + +/* HSTR definitions */ +#define HSTR_RESET_VAL 0x0 + +/* CNTHP_CTL definitions */ +#define CNTHP_CTL_RESET_VAL 0x0 /* NASCR definitions */ #define NSASEDIS_BIT (1 << 15) #define NSTRCDIS_BIT (1 << 20) +/* NOTE: correct typo in the definitions */ +#if !ERROR_DEPRECATED #define NASCR_CP11_BIT (1 << 11) #define NASCR_CP10_BIT (1 << 10) +#endif +#define NSACR_CP11_BIT (1 << 11) +#define NSACR_CP10_BIT (1 << 10) +#define NSACR_IMP_DEF_MASK (0x7 << 16) +#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) +#define NSACR_RESET_VAL 0x0 /* CPACR definitions */ #define ASEDIS_BIT (1 << 31) @@ -187,9 +220,12 @@ #define CPACR_CP10_SHIFT 20 #define CPACR_ENABLE_FP_ACCESS (0x3 << CPACR_CP11_SHIFT |\ 0x3 << CPACR_CP10_SHIFT) +#define CPACR_RESET_VAL 0x0 /* FPEXC definitions */ +#define FPEXC_RES1 ((1 << 10) | (1 << 9) | (1 << 8)) #define FPEXC_EN_BIT (1 << 30) +#define FPEXC_RESET_VAL FPEXC_RES1 /* SPSR/CPSR definitions */ #define SPSR_FIQ_BIT (1 << 0) @@ -369,6 +405,7 @@ #define HSCTLR p15, 4, c1, c0, 0 #define HCR p15, 4, c1, c1, 0 #define HCPTR p15, 4, c1, c1, 2 +#define HSTR p15, 4, c1, c1, 3 #define CNTHCTL p15, 4, c14, c1, 0 #define CNTKCTL p15, 0, c14, c1, 0 #define VPIDR p15, 4, c0, c0, 0 diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index e652a59e..ff53627f 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -228,6 +228,7 @@ DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64) DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64) DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64) DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR) +DEFINE_COPROCR_RW_FUNCS(hstr, HSTR) DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE) DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE) diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index e84c888c..990c1692 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -135,16 +135,20 @@ & ID_PFR1_VIRTEXT_MASK) /* SCTLR definitions */ -#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ +#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) -#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ +#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) #define SCTLR_AARCH32_EL1_RES1 \ ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ (U(1) << 4) | (U(1) << 3)) +#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ + (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ + (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) + #define SCTLR_M_BIT (U(1) << 0) #define SCTLR_A_BIT (U(1) << 1) #define SCTLR_C_BIT (U(1) << 2) @@ -155,6 +159,7 @@ #define SCTLR_NTWE_BIT (U(1) << 18) #define SCTLR_WXN_BIT (U(1) << 19) #define SCTLR_EE_BIT (U(1) << 25) +#define SCTLR_RESET_VAL SCTLR_EL3_RES1 /* CPACR_El1 definitions */ #define CPACR_EL1_FPEN(x) ((x) << 20) @@ -176,15 +181,47 @@ #define SCR_IRQ_BIT (U(1) << 1) #define SCR_NS_BIT (U(1) << 0) #define SCR_VALID_BIT_MASK U(0x2f8f) +#define SCR_RESET_VAL SCR_RES1_BITS -/* MDCR definitions */ +/* MDCR_EL3 definitions */ #define MDCR_SPD32(x) ((x) << 14) #define MDCR_SPD32_LEGACY U(0x0) #define MDCR_SPD32_DISABLE U(0x2) #define MDCR_SPD32_ENABLE U(0x3) #define MDCR_SDD_BIT (U(1) << 16) +#define MDCR_TDOSA_BIT (U(1) << 10) +#define MDCR_TDA_BIT (U(1) << 9) +#define MDCR_TPM_BIT (U(1) << 6) +#define MDCR_EL3_RESET_VAL U(0x0) +#if !ERROR_DEPRECATED #define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) +#endif + +/* MDCR_EL2 definitions */ +#define MDCR_EL2_TDRA_BIT (U(1) << 11) +#define MDCR_EL2_TDOSA_BIT (U(1) << 10) +#define MDCR_EL2_TDA_BIT (U(1) << 9) +#define MDCR_EL2_TDE_BIT (U(1) << 8) +#define MDCR_EL2_HPME_BIT (U(1) << 7) +#define MDCR_EL2_TPM_BIT (U(1) << 6) +#define MDCR_EL2_TPMCR_BIT (U(1) << 5) +#define MDCR_EL2_RESET_VAL U(0x0) + +/* HSTR_EL2 definitions */ +#define HSTR_EL2_RESET_VAL U(0x0) +#define HSTR_EL2_T_MASK U(0xff) + +/* CNTHP_CTL_EL2 definitions */ +#define CNTHP_CTL_ENABLE_BIT (U(1) << 0) +#define CNTHP_CTL_RESET_VAL U(0x0) + +/* VTTBR_EL2 definitions */ +#define VTTBR_RESET_VAL ULL(0x0) +#define VTTBR_VMID_MASK ULL(0xff) +#define VTTBR_VMID_SHIFT U(48) +#define VTTBR_BADDR_MASK ULL(0xffffffffffff) +#define VTTBR_BADDR_SHIFT U(0) /* HCR definitions */ #define HCR_RW_SHIFT U(31) @@ -199,6 +236,7 @@ #define ISR_F_SHIFT U(6) /* CNTHCTL_EL2 definitions */ +#define CNTHCTL_RESET_VAL U(0x0) #define EVNTEN_BIT (U(1) << 2) #define EL1PCEN_BIT (U(1) << 1) #define EL1PCTEN_BIT (U(1) << 0) @@ -217,6 +255,14 @@ #define TCPAC_BIT (U(1) << 31) #define TTA_BIT (U(1) << 20) #define TFP_BIT (U(1) << 10) +#define CPTR_EL3_RESET_VAL U(0x0) + +/* CPTR_EL2 definitions */ +#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) +#define CPTR_EL2_TCPAC_BIT (U(1) << 31) +#define CPTR_EL2_TTA_BIT (U(1) << 20) +#define CPTR_EL2_TFP_BIT (U(1) << 10) +#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 /* CPSR/SPSR definitions */ #define DAIF_FIQ_BIT (U(1) << 0) |