diff options
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch32/arch.h | 5 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 5 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a53.h | 20 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a57.h | 63 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a72.h | 47 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a53.h | 63 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 51 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a72.h | 47 | ||||
| -rw-r--r-- | include/lib/utils_def.h | 8 |
9 files changed, 210 insertions, 99 deletions
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 661dbf81..56163c8b 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -323,6 +323,11 @@ ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) /* + * TTBR definitions + */ +#define TTBR_CNP_BIT 0x1 + +/* * CTR definitions */ #define CTR_CWG_SHIFT 24 diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 7bceea77..2adf7699 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -396,6 +396,11 @@ (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) /* + * TTBR Definitions + */ +#define TTBR_CNP_BIT 0x1 + +/* * CTR_EL0 definitions */ #define CTR_CWG_SHIFT U(24) diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h index 24a9c6cd..8e86df46 100644 --- a/include/lib/cpus/aarch32/cortex_a53.h +++ b/include/lib/cpus/aarch32/cortex_a53.h @@ -40,11 +40,11 @@ /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A53_ACTLR p15, 0, c15 +#define CORTEX_A53_CPUACTLR p15, 0, c15 -#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT 44 -#define CORTEX_A53_ACTLR_ENDCCASCI (1 << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT) -#define CORTEX_A53_ACTLR_DTAH (1 << 24) +#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT 44 +#define CORTEX_A53_CPUACTLR_ENDCCASCI (1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT) +#define CORTEX_A53_CPUACTLR_DTAH (1 << 24) /******************************************************************************* * L2 Auxiliary Control register specific definitions. @@ -67,4 +67,16 @@ ******************************************************************************/ #define CORTEX_A53_L2MERRSR p15, 3, c15 +#if !ERROR_DEPRECATED +/* + * These registers were previously wrongly named. Provide previous definitions so + * as not to break platforms that continue using them. + */ +#define CORTEX_A53_ACTLR CORTEX_A53_CPUACTLR + +#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT +#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_ENDCCASCI +#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_DTAH +#endif /* !ERROR_DEPRECATED */ + #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index 1486b980..d3ae5b92 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -6,6 +6,7 @@ #ifndef __CORTEX_A57_H__ #define __CORTEX_A57_H__ +#include <utils_def.h> /* Cortex-A57 midr for revision 0 */ #define CORTEX_A57_MIDR 0x410FD070 @@ -24,13 +25,13 @@ ******************************************************************************/ #define CORTEX_A57_ECTLR p15, 1, c15 -#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6) -#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0 -#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. @@ -40,28 +41,28 @@ /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A57_ACTLR p15, 0, c15 - -#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59) -#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54) -#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52) -#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49) -#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44) -#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38) -#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27) -#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25) -#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) +#define CORTEX_A57_CPUACTLR p15, 0, c15 + +#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) +#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52) +#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27) +#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25) +#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2 +#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2 -#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Extended Control register specific definitions. @@ -69,11 +70,29 @@ #define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3 #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0 -#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ #define CORTEX_A57_L2MERRSR p15, 3, c15 +#if !ERROR_DEPRECATED +/* + * These registers were previously wrongly named. Provide previous definitions so + * as not to break platforms that continue using them. + */ +#define CORTEX_A57_ACTLR CORTEX_A57_CPUACTLR + +#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB +#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE +#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_DIS_OVERREAD +#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA +#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_DCC_AS_DCCI +#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH +#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_DIS_STREAMING +#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_DIS_L1_STREAMING +#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR +#endif /* !ERROR_DEPRECATED */ + #endif /* __CORTEX_A57_H__ */ diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index 59057bc5..306253d5 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -6,6 +6,7 @@ #ifndef __CORTEX_A72_H__ #define __CORTEX_A72_H__ +#include <utils_def.h> /* Cortex-A72 midr for revision 0 */ #define CORTEX_A72_MIDR 0x410FD080 @@ -13,42 +14,54 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_ECTLR p15, 1, c15 +#define CORTEX_A72_ECTLR p15, 1, c15 -#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6) -#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A72_MERRSR p15, 2, c15 +#define CORTEX_A72_MERRSR p15, 2, c15 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_ACTLR p15, 0, c15 +#define CORTEX_A72_CPUACTLR p15, 0, c15 -#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) -#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49) -#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) +#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 +#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 -#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A72_L2MERRSR p15, 3, c15 +#define CORTEX_A72_L2MERRSR p15, 3, c15 + +#if !ERROR_DEPRECATED +/* + * These registers were previously wrongly named. Provide previous definitions so + * as not to break platforms that continue using them. + */ +#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR + +#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH +#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA +#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_DCC_AS_DCCI +#endif /* !ERROR_DEPRECATED */ #endif /* __CORTEX_A72_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 6627dcfa..22c68006 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -22,53 +22,70 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 +#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 -#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6) +#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6) -#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) -#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) -#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) -#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2 +#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A53_ACTLR_EL1 S3_1_C15_C2_0 +#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0 -#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT U(44) -#define CORTEX_A53_ACTLR_ENDCCASCI (U(1) << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT) -#define CORTEX_A53_ACTLR_RADIS_SHIFT U(27) -#define CORTEX_A53_ACTLR_RADIS (U(3) << CORTEX_A53_ACTLR_RADIS_SHIFT) -#define CORTEX_A53_ACTLR_L1RADIS_SHIFT U(25) -#define CORTEX_A53_ACTLR_L1RADIS (U(3) << CORTEX_A53_ACTLR_L1RADIS_SHIFT) -#define CORTEX_A53_ACTLR_DTAH_SHIFT U(24) -#define CORTEX_A53_ACTLR_DTAH (U(1) << CORTEX_A53_ACTLR_DTAH_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44) +#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27) +#define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25) +#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24) +#define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) /******************************************************************************* * L2 Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0 +#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0 -#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) -#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) +#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) +#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3 +#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3 -#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) -#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 +#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 + +#if !ERROR_DEPRECATED +/* + * These registers were previously wrongly named. Provide previous definitions + * so as not to break platforms that continue using them. + */ +#define CORTEX_A53_ACTLR_EL1 CORTEX_A53_CPUACTLR_EL1 + +#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT +#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_EL1_ENDCCASCI +#define CORTEX_A53_ACTLR_RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT +#define CORTEX_A53_ACTLR_RADIS CORTEX_A53_CPUACTLR_EL1_RADIS +#define CORTEX_A53_ACTLR_L1RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT +#define CORTEX_A53_ACTLR_L1RADIS CORTEX_A53_CPUACTLR_EL1_L1RADIS +#define CORTEX_A53_ACTLR_DTAH_SHIFT CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT +#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_EL1_DTAH +#endif /* !ERROR_DEPRECATED */ #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 20d11e14..070108d5 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -6,6 +6,7 @@ #ifndef __CORTEX_A57_H__ #define __CORTEX_A57_H__ +#include <utils_def.h> /* Cortex-A57 midr for revision 0 */ #define CORTEX_A57_MIDR U(0x410FD070) @@ -40,30 +41,30 @@ /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A57_ACTLR_EL1 S3_1_C15_C2_0 - -#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) -#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) -#define CORTEX_A57_ACTLR_DIS_OVERREAD (ULL(1) << 52) -#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49) -#define CORTEX_A57_ACTLR_DCC_AS_DCCI (ULL(1) << 44) -#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) -#define CORTEX_A57_ACTLR_DIS_STREAMING (ULL(3) << 27) -#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (ULL(3) << 25) -#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) +#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 + +#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) +#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) +#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) +#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) +#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 +#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) -#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) -#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) -#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) -#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) +#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) /******************************************************************************* * L2 Extended Control register specific definitions. @@ -78,4 +79,22 @@ ******************************************************************************/ #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 +#if !ERROR_DEPRECATED +/* + * These registers were previously wrongly named. Provide previous definitions so + * as not to break platforms that continue using them. + */ +#define CORTEX_A57_ACTLR_EL1 CORTEX_A57_CPUACTLR_EL1 + +#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB +#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE +#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD +#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA +#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI +#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH +#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING +#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING +#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR +#endif /* !ERROR_DEPRECATED */ + #endif /* __CORTEX_A57_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 90f0abd9..aed714c6 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -6,49 +6,62 @@ #ifndef __CORTEX_A72_H__ #define __CORTEX_A72_H__ +#include <utils_def.h> /* Cortex-A72 midr for revision 0 */ -#define CORTEX_A72_MIDR 0x410FD080 +#define CORTEX_A72_MIDR 0x410FD080 /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 +#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 -#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6) -#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 +#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0 +#define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0 -#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) -#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49) -#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) +#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 +#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 +#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 + +#if !ERROR_DEPRECATED +/* + * These registers were previously wrongly named. Provide previous definitions so + * as not to break platforms that continue using them. + */ +#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR_EL1 + +#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH +#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA +#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI +#endif /* !ERROR_DEPRECATED */ #endif /* __CORTEX_A72_H__ */ diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 52496000..26ac4409 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -73,4 +73,12 @@ # define ULL(_x) (_x##ull) #endif +/* + * Test for the current architecture version to be at least the version + * expected. + */ +#define ARM_ARCH_AT_LEAST(_maj, _min) \ + ((ARM_ARCH_MAJOR > _maj) || \ + ((ARM_ARCH_MAJOR == _maj) && (ARM_ARCH_MINOR >= _min))) + #endif /* __UTILS_DEF_H__ */ |