diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/common/aarch32/el3_common_macros.S | 8 | ||||
-rw-r--r-- | include/common/aarch64/el3_common_macros.S | 7 | ||||
-rw-r--r-- | include/lib/aarch32/arch.h | 10 | ||||
-rw-r--r-- | include/lib/aarch32/arch_helpers.h | 3 | ||||
-rw-r--r-- | include/lib/aarch64/arch.h | 5 | ||||
-rw-r--r-- | include/lib/aarch64/arch_helpers.h | 3 |
6 files changed, 36 insertions, 0 deletions
diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S index 50ce952f..0018ea4b 100644 --- a/include/common/aarch32/el3_common_macros.S +++ b/include/common/aarch32/el3_common_macros.S @@ -67,6 +67,14 @@ orr r0, r0, #SCR_SIF_BIT stcopr r0, SCR + /* ----------------------------------------------------------------- + * Reset those registers that may have architecturally unknown reset + * values + * ----------------------------------------------------------------- + */ + mov r0, #0 + stcopr r0, SDCR + /* ----------------------------------------------------- * Enable the Asynchronous data abort now that the * exception vectors have been setup. diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S index 9b22a734..a4189116 100644 --- a/include/common/aarch64/el3_common_macros.S +++ b/include/common/aarch64/el3_common_macros.S @@ -77,6 +77,13 @@ */ mov x0, #(SCR_RES1_BITS | SCR_EA_BIT | SCR_SIF_BIT) msr scr_el3, x0 + + /* --------------------------------------------------------------------- + * Reset registers that may have architecturally unknown reset values + * --------------------------------------------------------------------- + */ + msr mdcr_el3, xzr + /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception * vectors have been setup. diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 4968e245..3c5ab26e 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -318,6 +318,11 @@ #define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ +/* PMCR definitions */ +#define PMCR_N_SHIFT 11 +#define PMCR_N_MASK 0x1f +#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) + /******************************************************************************* * Definitions of register offsets and fields in the CNTCTLBase Frame of the * system level implementation of the Generic Timer. @@ -375,6 +380,11 @@ #define CSSELR p15, 2, c0, c0, 0 #define CCSIDR p15, 1, c0, c0, 0 +/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ +#define HDCR p15, 4, c1, c1, 1 +#define SDCR p15, 0, c1, c3, 1 +#define PMCR p15, 0, c9, c12, 0 + /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ #define ICC_IAR1 p15, 0, c12, c12, 0 #define ICC_IAR0 p15, 0, c12, c8, 0 diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index 3b4349c3..0633bca2 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -249,6 +249,9 @@ DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1) DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0) DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1) +DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR) +DEFINE_COPROCR_READ_FUNC(pmcr, PMCR) + /* * TLBI operation prototypes */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index bef60323..a034ae20 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -411,4 +411,9 @@ #define CNTACR_RWVT_SHIFT 0x4 #define CNTACR_RWPT_SHIFT 0x5 +/* PMCR_EL0 definitions */ +#define PMCR_EL0_N_SHIFT 11 +#define PMCR_EL0_N_MASK 0x1f +#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) + #endif /* __ARCH_H__ */ diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index 4d936ad5..37db0313 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -279,6 +279,9 @@ DEFINE_SYSREG_READ_FUNC(isr_el1) DEFINE_SYSREG_READ_FUNC(ctr_el0) +DEFINE_SYSREG_RW_FUNCS(mdcr_el2) +DEFINE_SYSREG_READ_FUNC(pmcr_el0) + DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) |