diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76.S | 32 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_deimos.S | 51 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_helios.S | 34 | ||||
| -rw-r--r-- | lib/cpus/aarch64/denver.S | 32 | ||||
| -rw-r--r-- | lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S | 64 | ||||
| -rw-r--r-- | lib/cpus/aarch64/wa_cve_2017_5715_mmu.S | 32 | ||||
| -rw-r--r-- | lib/utils/mem_region.c | 2 |
7 files changed, 166 insertions, 81 deletions
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 14705d7b..51d0b15e 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -107,19 +107,19 @@ vector_base cortex_a76_wa_cve_2018_3639_a76_vbar */ vector_entry cortex_a76_sync_exception_sp_el0 b sync_exception_sp_el0 - check_vector_size cortex_a76_sync_exception_sp_el0 +end_vector_entry cortex_a76_sync_exception_sp_el0 vector_entry cortex_a76_irq_sp_el0 b irq_sp_el0 - check_vector_size cortex_a76_irq_sp_el0 +end_vector_entry cortex_a76_irq_sp_el0 vector_entry cortex_a76_fiq_sp_el0 b fiq_sp_el0 - check_vector_size cortex_a76_fiq_sp_el0 +end_vector_entry cortex_a76_fiq_sp_el0 vector_entry cortex_a76_serror_sp_el0 b serror_sp_el0 - check_vector_size cortex_a76_serror_sp_el0 +end_vector_entry cortex_a76_serror_sp_el0 /* --------------------------------------------------------------------- * Current EL with SP_ELx: 0x200 - 0x400 @@ -127,19 +127,19 @@ vector_entry cortex_a76_serror_sp_el0 */ vector_entry cortex_a76_sync_exception_sp_elx b sync_exception_sp_elx - check_vector_size cortex_a76_sync_exception_sp_elx +end_vector_entry cortex_a76_sync_exception_sp_elx vector_entry cortex_a76_irq_sp_elx b irq_sp_elx - check_vector_size cortex_a76_irq_sp_elx +end_vector_entry cortex_a76_irq_sp_elx vector_entry cortex_a76_fiq_sp_elx b fiq_sp_elx - check_vector_size cortex_a76_fiq_sp_elx +end_vector_entry cortex_a76_fiq_sp_elx vector_entry cortex_a76_serror_sp_elx b serror_sp_elx - check_vector_size cortex_a76_serror_sp_elx +end_vector_entry cortex_a76_serror_sp_elx /* --------------------------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x600 @@ -148,22 +148,22 @@ vector_entry cortex_a76_serror_sp_elx vector_entry cortex_a76_sync_exception_aarch64 apply_cve_2018_3639_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A64_SMC0 b sync_exception_aarch64 - check_vector_size cortex_a76_sync_exception_aarch64 +end_vector_entry cortex_a76_sync_exception_aarch64 vector_entry cortex_a76_irq_aarch64 apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0 b irq_aarch64 - check_vector_size cortex_a76_irq_aarch64 +end_vector_entry cortex_a76_irq_aarch64 vector_entry cortex_a76_fiq_aarch64 apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0 b fiq_aarch64 - check_vector_size cortex_a76_fiq_aarch64 +end_vector_entry cortex_a76_fiq_aarch64 vector_entry cortex_a76_serror_aarch64 apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0 b serror_aarch64 - check_vector_size cortex_a76_serror_aarch64 +end_vector_entry cortex_a76_serror_aarch64 /* --------------------------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x800 @@ -172,22 +172,22 @@ vector_entry cortex_a76_serror_aarch64 vector_entry cortex_a76_sync_exception_aarch32 apply_cve_2018_3639_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A32_SMC0 b sync_exception_aarch32 - check_vector_size cortex_a76_sync_exception_aarch32 +end_vector_entry cortex_a76_sync_exception_aarch32 vector_entry cortex_a76_irq_aarch32 apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0 b irq_aarch32 - check_vector_size cortex_a76_irq_aarch32 +end_vector_entry cortex_a76_irq_aarch32 vector_entry cortex_a76_fiq_aarch32 apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0 b fiq_aarch32 - check_vector_size cortex_a76_fiq_aarch32 +end_vector_entry cortex_a76_fiq_aarch32 vector_entry cortex_a76_serror_aarch32 apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0 b serror_aarch32 - check_vector_size cortex_a76_serror_aarch32 +end_vector_entry cortex_a76_serror_aarch32 func check_errata_cve_2018_3639 #if WORKAROUND_CVE_2018_3639 diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_deimos.S new file mode 100644 index 00000000..aec62a28 --- /dev/null +++ b/lib/cpus/aarch64/cortex_deimos.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <bl_common.h> +#include <cortex_deimos.h> +#include <cpu_macros.S> +#include <plat_macros.S> + + /* --------------------------------------------- + * HW will do the cache maintenance while powering down + * --------------------------------------------- + */ +func cortex_deimos_core_pwr_dwn + /* --------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------- + */ + mrs x0, CORTEX_DEIMOS_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_DEIMOS_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_deimos_core_pwr_dwn + + /* --------------------------------------------- + * This function provides Cortex-Deimos specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_deimos_regs, "aS" +cortex_deimos_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_deimos_cpu_reg_dump + adr x6, cortex_deimos_regs + mrs x8, CORTEX_DEIMOS_CPUECTLR_EL1 + ret +endfunc cortex_deimos_cpu_reg_dump + +declare_cpu_ops cortex_deimos, CORTEX_DEIMOS_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_deimos_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_helios.S b/lib/cpus/aarch64/cortex_helios.S new file mode 100644 index 00000000..bcda7411 --- /dev/null +++ b/lib/cpus/aarch64/cortex_helios.S @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch.h> +#include <asm_macros.S> +#include <bl_common.h> +#include <cortex_helios.h> +#include <cpu_macros.S> +#include <debug.h> +#include <plat_macros.S> + +func cortex_helios_cpu_pwr_dwn + mrs x0, CORTEX_HELIOS_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_HELIOS_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_helios_cpu_pwr_dwn + +.section .rodata.cortex_helios_regs, "aS" +cortex_helios_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_helios_cpu_reg_dump + adr x6, cortex_helios_regs + mrs x8, CORTEX_HELIOS_ECTLR_EL1 + ret +endfunc cortex_helios_cpu_reg_dump + +declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_helios_cpu_pwr_dwn diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index aee4feee..f04dbd6c 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -55,19 +55,19 @@ vector_base workaround_bpflush_runtime_exceptions */ vector_entry workaround_bpflush_sync_exception_sp_el0 b sync_exception_sp_el0 - check_vector_size workaround_bpflush_sync_exception_sp_el0 +end_vector_entry workaround_bpflush_sync_exception_sp_el0 vector_entry workaround_bpflush_irq_sp_el0 b irq_sp_el0 - check_vector_size workaround_bpflush_irq_sp_el0 +end_vector_entry workaround_bpflush_irq_sp_el0 vector_entry workaround_bpflush_fiq_sp_el0 b fiq_sp_el0 - check_vector_size workaround_bpflush_fiq_sp_el0 +end_vector_entry workaround_bpflush_fiq_sp_el0 vector_entry workaround_bpflush_serror_sp_el0 b serror_sp_el0 - check_vector_size workaround_bpflush_serror_sp_el0 +end_vector_entry workaround_bpflush_serror_sp_el0 /* --------------------------------------------------------------------- * Current EL with SP_ELx: 0x200 - 0x400 @@ -75,19 +75,19 @@ vector_entry workaround_bpflush_serror_sp_el0 */ vector_entry workaround_bpflush_sync_exception_sp_elx b sync_exception_sp_elx - check_vector_size workaround_bpflush_sync_exception_sp_elx +end_vector_entry workaround_bpflush_sync_exception_sp_elx vector_entry workaround_bpflush_irq_sp_elx b irq_sp_elx - check_vector_size workaround_bpflush_irq_sp_elx +end_vector_entry workaround_bpflush_irq_sp_elx vector_entry workaround_bpflush_fiq_sp_elx b fiq_sp_elx - check_vector_size workaround_bpflush_fiq_sp_elx +end_vector_entry workaround_bpflush_fiq_sp_elx vector_entry workaround_bpflush_serror_sp_elx b serror_sp_elx - check_vector_size workaround_bpflush_serror_sp_elx +end_vector_entry workaround_bpflush_serror_sp_elx /* --------------------------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x600 @@ -96,22 +96,22 @@ vector_entry workaround_bpflush_serror_sp_elx vector_entry workaround_bpflush_sync_exception_aarch64 apply_workaround b sync_exception_aarch64 - check_vector_size workaround_bpflush_sync_exception_aarch64 +end_vector_entry workaround_bpflush_sync_exception_aarch64 vector_entry workaround_bpflush_irq_aarch64 apply_workaround b irq_aarch64 - check_vector_size workaround_bpflush_irq_aarch64 +end_vector_entry workaround_bpflush_irq_aarch64 vector_entry workaround_bpflush_fiq_aarch64 apply_workaround b fiq_aarch64 - check_vector_size workaround_bpflush_fiq_aarch64 +end_vector_entry workaround_bpflush_fiq_aarch64 vector_entry workaround_bpflush_serror_aarch64 apply_workaround b serror_aarch64 - check_vector_size workaround_bpflush_serror_aarch64 +end_vector_entry workaround_bpflush_serror_aarch64 /* --------------------------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x800 @@ -120,22 +120,22 @@ vector_entry workaround_bpflush_serror_aarch64 vector_entry workaround_bpflush_sync_exception_aarch32 apply_workaround b sync_exception_aarch32 - check_vector_size workaround_bpflush_sync_exception_aarch32 +end_vector_entry workaround_bpflush_sync_exception_aarch32 vector_entry workaround_bpflush_irq_aarch32 apply_workaround b irq_aarch32 - check_vector_size workaround_bpflush_irq_aarch32 +end_vector_entry workaround_bpflush_irq_aarch32 vector_entry workaround_bpflush_fiq_aarch32 apply_workaround b fiq_aarch32 - check_vector_size workaround_bpflush_fiq_aarch32 +end_vector_entry workaround_bpflush_fiq_aarch32 vector_entry workaround_bpflush_serror_aarch32 apply_workaround b serror_aarch32 - check_vector_size workaround_bpflush_serror_aarch32 +end_vector_entry workaround_bpflush_serror_aarch32 .global denver_disable_dco diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S index 84371551..c613ebdf 100644 --- a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S +++ b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S @@ -114,19 +114,19 @@ aarch32_stub: .word EMIT_BPIALL .word EMIT_SMC - check_vector_size bpiall_sync_exception_sp_el0 +end_vector_entry bpiall_sync_exception_sp_el0 vector_entry bpiall_irq_sp_el0 b irq_sp_el0 - check_vector_size bpiall_irq_sp_el0 +end_vector_entry bpiall_irq_sp_el0 vector_entry bpiall_fiq_sp_el0 b fiq_sp_el0 - check_vector_size bpiall_fiq_sp_el0 +end_vector_entry bpiall_fiq_sp_el0 vector_entry bpiall_serror_sp_el0 b serror_sp_el0 - check_vector_size bpiall_serror_sp_el0 +end_vector_entry bpiall_serror_sp_el0 /* --------------------------------------------------------------------- * Current EL with SP_ELx: 0x200 - 0x400 @@ -134,19 +134,19 @@ vector_entry bpiall_serror_sp_el0 */ vector_entry bpiall_sync_exception_sp_elx b sync_exception_sp_elx - check_vector_size bpiall_sync_exception_sp_elx +end_vector_entry bpiall_sync_exception_sp_elx vector_entry bpiall_irq_sp_elx b irq_sp_elx - check_vector_size bpiall_irq_sp_elx +end_vector_entry bpiall_irq_sp_elx vector_entry bpiall_fiq_sp_elx b fiq_sp_elx - check_vector_size bpiall_fiq_sp_elx +end_vector_entry bpiall_fiq_sp_elx vector_entry bpiall_serror_sp_elx b serror_sp_elx - check_vector_size bpiall_serror_sp_elx +end_vector_entry bpiall_serror_sp_elx /* --------------------------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x600 @@ -154,19 +154,19 @@ vector_entry bpiall_serror_sp_elx */ vector_entry bpiall_sync_exception_aarch64 apply_cve_2017_5715_wa 1 - check_vector_size bpiall_sync_exception_aarch64 +end_vector_entry bpiall_sync_exception_aarch64 vector_entry bpiall_irq_aarch64 apply_cve_2017_5715_wa 2 - check_vector_size bpiall_irq_aarch64 +end_vector_entry bpiall_irq_aarch64 vector_entry bpiall_fiq_aarch64 apply_cve_2017_5715_wa 4 - check_vector_size bpiall_fiq_aarch64 +end_vector_entry bpiall_fiq_aarch64 vector_entry bpiall_serror_aarch64 apply_cve_2017_5715_wa 8 - check_vector_size bpiall_serror_aarch64 +end_vector_entry bpiall_serror_aarch64 /* --------------------------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x800 @@ -174,19 +174,19 @@ vector_entry bpiall_serror_aarch64 */ vector_entry bpiall_sync_exception_aarch32 apply_cve_2017_5715_wa 1 - check_vector_size bpiall_sync_exception_aarch32 +end_vector_entry bpiall_sync_exception_aarch32 vector_entry bpiall_irq_aarch32 apply_cve_2017_5715_wa 2 - check_vector_size bpiall_irq_aarch32 +end_vector_entry bpiall_irq_aarch32 vector_entry bpiall_fiq_aarch32 apply_cve_2017_5715_wa 4 - check_vector_size bpiall_fiq_aarch32 +end_vector_entry bpiall_fiq_aarch32 vector_entry bpiall_serror_aarch32 apply_cve_2017_5715_wa 8 - check_vector_size bpiall_serror_aarch32 +end_vector_entry bpiall_serror_aarch32 /* --------------------------------------------------------------------- * This vector table is used while the workaround is executing. It @@ -203,19 +203,19 @@ vector_base wa_cve_2017_5715_bpiall_ret_vbar */ vector_entry bpiall_ret_sync_exception_sp_el0 b report_unhandled_exception - check_vector_size bpiall_ret_sync_exception_sp_el0 +end_vector_entry bpiall_ret_sync_exception_sp_el0 vector_entry bpiall_ret_irq_sp_el0 b report_unhandled_interrupt - check_vector_size bpiall_ret_irq_sp_el0 +end_vector_entry bpiall_ret_irq_sp_el0 vector_entry bpiall_ret_fiq_sp_el0 b report_unhandled_interrupt - check_vector_size bpiall_ret_fiq_sp_el0 +end_vector_entry bpiall_ret_fiq_sp_el0 vector_entry bpiall_ret_serror_sp_el0 b report_unhandled_exception - check_vector_size bpiall_ret_serror_sp_el0 +end_vector_entry bpiall_ret_serror_sp_el0 /* --------------------------------------------------------------------- * Current EL with SP_ELx: 0x200 - 0x400 (UNUSED) @@ -223,19 +223,19 @@ vector_entry bpiall_ret_serror_sp_el0 */ vector_entry bpiall_ret_sync_exception_sp_elx b report_unhandled_exception - check_vector_size bpiall_ret_sync_exception_sp_elx +end_vector_entry bpiall_ret_sync_exception_sp_elx vector_entry bpiall_ret_irq_sp_elx b report_unhandled_interrupt - check_vector_size bpiall_ret_irq_sp_elx +end_vector_entry bpiall_ret_irq_sp_elx vector_entry bpiall_ret_fiq_sp_elx b report_unhandled_interrupt - check_vector_size bpiall_ret_fiq_sp_elx +end_vector_entry bpiall_ret_fiq_sp_elx vector_entry bpiall_ret_serror_sp_elx b report_unhandled_exception - check_vector_size bpiall_ret_serror_sp_elx +end_vector_entry bpiall_ret_serror_sp_elx /* --------------------------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x600 (UNUSED) @@ -243,19 +243,19 @@ vector_entry bpiall_ret_serror_sp_elx */ vector_entry bpiall_ret_sync_exception_aarch64 b report_unhandled_exception - check_vector_size bpiall_ret_sync_exception_aarch64 +end_vector_entry bpiall_ret_sync_exception_aarch64 vector_entry bpiall_ret_irq_aarch64 b report_unhandled_interrupt - check_vector_size bpiall_ret_irq_aarch64 +end_vector_entry bpiall_ret_irq_aarch64 vector_entry bpiall_ret_fiq_aarch64 b report_unhandled_interrupt - check_vector_size bpiall_ret_fiq_aarch64 +end_vector_entry bpiall_ret_fiq_aarch64 vector_entry bpiall_ret_serror_aarch64 b report_unhandled_exception - check_vector_size bpiall_ret_serror_aarch64 +end_vector_entry bpiall_ret_serror_aarch64 /* --------------------------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x800 @@ -324,7 +324,7 @@ vector_entry bpiall_ret_sync_exception_aarch32 1: ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] b sync_exception_aarch64 - check_vector_size bpiall_ret_sync_exception_aarch32 +end_vector_entry bpiall_ret_sync_exception_aarch32 vector_entry bpiall_ret_irq_aarch32 b report_unhandled_interrupt @@ -346,12 +346,12 @@ bpiall_ret_fiq: bpiall_ret_serror: ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] b serror_aarch64 - check_vector_size bpiall_ret_irq_aarch32 +end_vector_entry bpiall_ret_irq_aarch32 vector_entry bpiall_ret_fiq_aarch32 b report_unhandled_interrupt - check_vector_size bpiall_ret_fiq_aarch32 +end_vector_entry bpiall_ret_fiq_aarch32 vector_entry bpiall_ret_serror_aarch32 b report_unhandled_exception - check_vector_size bpiall_ret_serror_aarch32 +end_vector_entry bpiall_ret_serror_aarch32 diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S index a556d1fe..d7b6e26e 100644 --- a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S +++ b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S @@ -66,19 +66,19 @@ vector_base wa_cve_2017_5715_mmu_vbar */ vector_entry mmu_sync_exception_sp_el0 b sync_exception_sp_el0 - check_vector_size mmu_sync_exception_sp_el0 +end_vector_entry mmu_sync_exception_sp_el0 vector_entry mmu_irq_sp_el0 b irq_sp_el0 - check_vector_size mmu_irq_sp_el0 +end_vector_entry mmu_irq_sp_el0 vector_entry mmu_fiq_sp_el0 b fiq_sp_el0 - check_vector_size mmu_fiq_sp_el0 +end_vector_entry mmu_fiq_sp_el0 vector_entry mmu_serror_sp_el0 b serror_sp_el0 - check_vector_size mmu_serror_sp_el0 +end_vector_entry mmu_serror_sp_el0 /* --------------------------------------------------------------------- * Current EL with SP_ELx: 0x200 - 0x400 @@ -86,19 +86,19 @@ vector_entry mmu_serror_sp_el0 */ vector_entry mmu_sync_exception_sp_elx b sync_exception_sp_elx - check_vector_size mmu_sync_exception_sp_elx +end_vector_entry mmu_sync_exception_sp_elx vector_entry mmu_irq_sp_elx b irq_sp_elx - check_vector_size mmu_irq_sp_elx +end_vector_entry mmu_irq_sp_elx vector_entry mmu_fiq_sp_elx b fiq_sp_elx - check_vector_size mmu_fiq_sp_elx +end_vector_entry mmu_fiq_sp_elx vector_entry mmu_serror_sp_elx b serror_sp_elx - check_vector_size mmu_serror_sp_elx +end_vector_entry mmu_serror_sp_elx /* --------------------------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x600 @@ -107,22 +107,22 @@ vector_entry mmu_serror_sp_elx vector_entry mmu_sync_exception_aarch64 apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A64_SMC0 b sync_exception_aarch64 - check_vector_size mmu_sync_exception_aarch64 +end_vector_entry mmu_sync_exception_aarch64 vector_entry mmu_irq_aarch64 apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0 b irq_aarch64 - check_vector_size mmu_irq_aarch64 +end_vector_entry mmu_irq_aarch64 vector_entry mmu_fiq_aarch64 apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0 b fiq_aarch64 - check_vector_size mmu_fiq_aarch64 +end_vector_entry mmu_fiq_aarch64 vector_entry mmu_serror_aarch64 apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0 b serror_aarch64 - check_vector_size mmu_serror_aarch64 +end_vector_entry mmu_serror_aarch64 /* --------------------------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x800 @@ -131,19 +131,19 @@ vector_entry mmu_serror_aarch64 vector_entry mmu_sync_exception_aarch32 apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A32_SMC0 b sync_exception_aarch32 - check_vector_size mmu_sync_exception_aarch32 +end_vector_entry mmu_sync_exception_aarch32 vector_entry mmu_irq_aarch32 apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0 b irq_aarch32 - check_vector_size mmu_irq_aarch32 +end_vector_entry mmu_irq_aarch32 vector_entry mmu_fiq_aarch32 apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0 b fiq_aarch32 - check_vector_size mmu_fiq_aarch32 +end_vector_entry mmu_fiq_aarch32 vector_entry mmu_serror_aarch32 apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0 b serror_aarch32 - check_vector_size mmu_serror_aarch32 +end_vector_entry mmu_serror_aarch32 diff --git a/lib/utils/mem_region.c b/lib/utils/mem_region.c index e9541ba3..a5c3c617 100644 --- a/lib/utils/mem_region.c +++ b/lib/utils/mem_region.c @@ -50,7 +50,7 @@ void clear_mem_regions(mem_region_t *tbl, size_t nregions) * be cleared, and chunk is the amount of memory mapped and * cleared in every iteration. */ -void clear_map_dyn_mem_regions(mem_region_t *regions, +void clear_map_dyn_mem_regions(struct mem_region *regions, size_t nregions, uintptr_t va, size_t chunk) |