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-rw-r--r--plat/fvp/aarch64/plat_common.c4
-rw-r--r--plat/fvp/bl1_plat_setup.c4
-rw-r--r--plat/fvp/bl2_plat_setup.c14
-rw-r--r--plat/fvp/bl31_plat_setup.c12
-rw-r--r--plat/fvp/bl32_plat_setup.c6
-rw-r--r--plat/fvp/drivers/pwrc/fvp_pwrc.c2
-rw-r--r--plat/fvp/plat_io_storage.c22
-rw-r--r--plat/fvp/plat_pm.c16
-rw-r--r--plat/fvp/plat_security.c2
-rw-r--r--plat/fvp/plat_topology.c8
-rw-r--r--plat/fvp/platform.h8
11 files changed, 49 insertions, 49 deletions
diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/plat_common.c
index 338141c9..40e6b324 100644
--- a/plat/fvp/aarch64/plat_common.c
+++ b/plat/fvp/aarch64/plat_common.c
@@ -122,7 +122,7 @@ void disable_mmu(void)
* This doesn't include TZRAM as the 'mem_layout' argument passed to to
* configure_mmu() will give the available subset of that,
*/
-const mmap_region fvp_mmap[] = {
+const mmap_region_t fvp_mmap[] = {
{ TZROM_BASE, TZROM_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
{ TZDRAM_BASE, TZDRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
{ FLASH0_BASE, FLASH0_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
@@ -140,7 +140,7 @@ const mmap_region fvp_mmap[] = {
/*******************************************************************************
* Setup the pagetables as per the platform memory map & initialize the mmu
*******************************************************************************/
-void configure_mmu(meminfo *mem_layout,
+void configure_mmu(meminfo_t *mem_layout,
unsigned long ro_start,
unsigned long ro_limit,
unsigned long coh_start,
diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_plat_setup.c
index 67694f42..818c4e3f 100644
--- a/plat/fvp/bl1_plat_setup.c
+++ b/plat/fvp/bl1_plat_setup.c
@@ -60,9 +60,9 @@ extern unsigned long __BL1_RAM_END__;
/* Data structure which holds the extents of the trusted SRAM for BL1*/
-static meminfo bl1_tzram_layout;
+static meminfo_t bl1_tzram_layout;
-meminfo *bl1_plat_sec_mem_layout(void)
+meminfo_t *bl1_plat_sec_mem_layout(void)
{
return &bl1_tzram_layout;
}
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c
index da6a4858..8517497e 100644
--- a/plat/fvp/bl2_plat_setup.c
+++ b/plat/fvp/bl2_plat_setup.c
@@ -68,7 +68,7 @@ extern unsigned long __COHERENT_RAM_END__;
extern unsigned char **bl2_el_change_mem_ptr;
/* Data structure which holds the extents of the trusted SRAM for BL2 */
-static meminfo bl2_tzram_layout
+static meminfo_t bl2_tzram_layout
__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
section("tzfw_coherent_mem")));
@@ -76,9 +76,9 @@ __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
* Reference to structure which holds the arguments which need to be passed
* to BL31
******************************************************************************/
-static bl31_args *bl2_to_bl31_args;
+static bl31_args_t *bl2_to_bl31_args;
-meminfo *bl2_plat_sec_mem_layout(void)
+meminfo_t *bl2_plat_sec_mem_layout(void)
{
return &bl2_tzram_layout;
}
@@ -87,7 +87,7 @@ meminfo *bl2_plat_sec_mem_layout(void)
* This function returns a pointer to the memory that the platform has kept
* aside to pass all the information that BL31 could need.
******************************************************************************/
-bl31_args *bl2_get_bl31_args_ptr(void)
+bl31_args_t *bl2_get_bl31_args_ptr(void)
{
return bl2_to_bl31_args;
}
@@ -97,7 +97,7 @@ bl31_args *bl2_get_bl31_args_ptr(void)
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
* Copy it to a safe loaction before its reclaimed by later BL2 functionality.
******************************************************************************/
-void bl2_early_platform_setup(meminfo *mem_layout,
+void bl2_early_platform_setup(meminfo_t *mem_layout,
void *data)
{
/* Setup the BL2 memory layout */
@@ -137,10 +137,10 @@ void bl2_platform_setup()
* Ensure that the secure DRAM memory used for passing BL31 arguments
* does not overlap with the BL32_BASE.
*/
- assert (BL32_BASE > TZDRAM_BASE + sizeof(bl31_args));
+ assert (BL32_BASE > TZDRAM_BASE + sizeof(bl31_args_t));
/* Use the Trusted DRAM for passing args to BL31 */
- bl2_to_bl31_args = (bl31_args *) TZDRAM_BASE;
+ bl2_to_bl31_args = (bl31_args_t *) TZDRAM_BASE;
/* Populate the extents of memory available for loading BL33 */
bl2_to_bl31_args->bl33_meminfo.total_base = DRAM_BASE;
diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c
index bd167df0..5abe2368 100644
--- a/plat/fvp/bl31_plat_setup.c
+++ b/plat/fvp/bl31_plat_setup.c
@@ -66,14 +66,14 @@ extern unsigned long __COHERENT_RAM_END__;
* Reference to structure which holds the arguments that have been passed to
* BL31 from BL2.
******************************************************************************/
-static bl31_args *bl2_to_bl31_args;
+static bl31_args_t *bl2_to_bl31_args;
-meminfo *bl31_plat_sec_mem_layout(void)
+meminfo_t *bl31_plat_sec_mem_layout(void)
{
return &bl2_to_bl31_args->bl31_meminfo;
}
-meminfo *bl31_plat_get_bl32_mem_layout(void)
+meminfo_t *bl31_plat_get_bl32_mem_layout(void)
{
return &bl2_to_bl31_args->bl32_meminfo;
}
@@ -84,9 +84,9 @@ meminfo *bl31_plat_get_bl32_mem_layout(void)
* while BL32 corresponds to the secure image type. A NULL pointer is returned
* if the image does not exist.
******************************************************************************/
-el_change_info *bl31_get_next_image_info(uint32_t type)
+el_change_info_t *bl31_get_next_image_info(uint32_t type)
{
- el_change_info *next_image_info;
+ el_change_info_t *next_image_info;
next_image_info = (type == NON_SECURE) ?
&bl2_to_bl31_args->bl33_image_info :
@@ -110,7 +110,7 @@ el_change_info *bl31_get_next_image_info(uint32_t type)
* has flushed this information to memory, so we are guaranteed to pick up good
* data
******************************************************************************/
-void bl31_early_platform_setup(bl31_args *from_bl2,
+void bl31_early_platform_setup(bl31_args_t *from_bl2,
void *data)
{
bl2_to_bl31_args = from_bl2;
diff --git a/plat/fvp/bl32_plat_setup.c b/plat/fvp/bl32_plat_setup.c
index ba418fdd..3226ea23 100644
--- a/plat/fvp/bl32_plat_setup.c
+++ b/plat/fvp/bl32_plat_setup.c
@@ -66,11 +66,11 @@ extern unsigned long __COHERENT_RAM_END__;
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/* Data structure which holds the extents of the trusted SRAM for BL32 */
-static meminfo bl32_tzdram_layout
+static meminfo_t bl32_tzdram_layout
__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
section("tzfw_coherent_mem")));
-meminfo *bl32_plat_sec_mem_layout(void)
+meminfo_t *bl32_plat_sec_mem_layout(void)
{
return &bl32_tzdram_layout;
}
@@ -79,7 +79,7 @@ meminfo *bl32_plat_sec_mem_layout(void)
* BL1 has passed the extents of the trusted SRAM that's at BL32's disposal.
* Initialize the BL32 data structure with the memory extends
******************************************************************************/
-void bl32_early_platform_setup(meminfo *mem_layout,
+void bl32_early_platform_setup(meminfo_t *mem_layout,
void *data)
{
/* Setup the BL32 memory layout */
diff --git a/plat/fvp/drivers/pwrc/fvp_pwrc.c b/plat/fvp/drivers/pwrc/fvp_pwrc.c
index 164a7343..175d41c0 100644
--- a/plat/fvp/drivers/pwrc/fvp_pwrc.c
+++ b/plat/fvp/drivers/pwrc/fvp_pwrc.c
@@ -41,7 +41,7 @@
* TODO: Someday there will be a generic power controller api. At the moment
* each platform has its own pwrc so just exporting functions is fine.
*/
-static bakery_lock pwrc_lock __attribute__ ((section("tzfw_coherent_mem")));
+static bakery_lock_t pwrc_lock __attribute__ ((section("tzfw_coherent_mem")));
unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr)
{
diff --git a/plat/fvp/plat_io_storage.c b/plat/fvp/plat_io_storage.c
index d44a71d6..371f5671 100644
--- a/plat/fvp/plat_io_storage.c
+++ b/plat/fvp/plat_io_storage.c
@@ -40,40 +40,40 @@
#include <debug.h>
/* IO devices */
-static struct io_plat_data io_data;
-static struct io_dev_connector *sh_dev_con;
+static io_plat_data_t io_data;
+static io_dev_connector_t *sh_dev_con;
static void *const sh_dev_spec;
static void *const sh_init_params;
static io_dev_handle sh_dev_handle;
-static struct io_dev_connector *fip_dev_con;
+static io_dev_connector_t *fip_dev_con;
static void *const fip_dev_spec;
static io_dev_handle fip_dev_handle;
-static struct io_dev_connector *memmap_dev_con;
+static io_dev_connector_t *memmap_dev_con;
static void *const memmap_dev_spec;
static void *const memmap_init_params;
static io_dev_handle memmap_dev_handle;
-static io_block_spec fip_block_spec = {
+static io_block_spec_t fip_block_spec = {
.offset = FLASH0_BASE,
.length = FLASH0_SIZE
};
-static io_file_spec bl2_file_spec = {
+static io_file_spec_t bl2_file_spec = {
.path = BL2_IMAGE_NAME,
.mode = FOPEN_MODE_RB
};
-static io_file_spec bl31_file_spec = {
+static io_file_spec_t bl31_file_spec = {
.path = BL31_IMAGE_NAME,
.mode = FOPEN_MODE_RB
};
-static io_file_spec bl32_file_spec = {
+static io_file_spec_t bl32_file_spec = {
.path = BL32_IMAGE_NAME,
.mode = FOPEN_MODE_RB
};
-static io_file_spec bl33_file_spec = {
+static io_file_spec_t bl33_file_spec = {
.path = BL33_IMAGE_NAME,
.mode = FOPEN_MODE_RB
};
@@ -194,7 +194,7 @@ int plat_get_image_source(const char *image_name, io_dev_handle *dev_handle,
if (strcmp(policy->image_name, image_name) == 0) {
result = policy->check(policy->image_spec);
if (result == IO_SUCCESS) {
- *(io_file_spec **)image_spec =
+ *(io_file_spec_t **)image_spec =
policy->image_spec;
*dev_handle = *(policy->dev_handle);
break;
@@ -203,7 +203,7 @@ int plat_get_image_source(const char *image_name, io_dev_handle *dev_handle,
policy->image_spec);
if (result == IO_SUCCESS) {
*dev_handle = sh_dev_handle;
- *(io_file_spec **)image_spec =
+ *(io_file_spec_t **)image_spec =
policy->image_spec;
}
}
diff --git a/plat/fvp/plat_pm.c b/plat/fvp/plat_pm.c
index 4359638e..da940c1f 100644
--- a/plat/fvp/plat_pm.c
+++ b/plat/fvp/plat_pm.c
@@ -78,7 +78,7 @@ int fvp_affinst_on(unsigned long mpidr,
{
int rc = PSCI_E_SUCCESS;
unsigned long linear_id;
- mailbox *fvp_mboxes;
+ mailbox_t *fvp_mboxes;
unsigned int psysr;
/*
@@ -100,7 +100,7 @@ int fvp_affinst_on(unsigned long mpidr,
} while (psysr & PSYSR_AFF_L0);
linear_id = platform_get_core_pos(mpidr);
- fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
+ fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
fvp_mboxes[linear_id].value = sec_entrypoint;
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
sizeof(unsigned long));
@@ -209,7 +209,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
int rc = PSCI_E_SUCCESS;
unsigned int gicc_base, ectlr;
unsigned long cpu_setup, cci_setup, linear_id;
- mailbox *fvp_mboxes;
+ mailbox_t *fvp_mboxes;
switch (afflvl) {
case MPIDR_AFFLVL1:
@@ -247,7 +247,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
/* Program the jump address for the target cpu */
linear_id = platform_get_core_pos(mpidr);
- fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
+ fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
fvp_mboxes[linear_id].value = sec_entrypoint;
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
sizeof(unsigned long));
@@ -288,7 +288,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
{
int rc = PSCI_E_SUCCESS;
unsigned long linear_id, cpu_setup, cci_setup;
- mailbox *fvp_mboxes;
+ mailbox_t *fvp_mboxes;
unsigned int gicd_base, gicc_base, reg_val, ectlr;
switch (afflvl) {
@@ -341,7 +341,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
fvp_pwrc_clr_wen(mpidr);
/* Zero the jump address in the mailbox for this cpu */
- fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
+ fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
linear_id = platform_get_core_pos(mpidr);
fvp_mboxes[linear_id].value = 0;
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
@@ -394,7 +394,7 @@ int fvp_affinst_suspend_finish(unsigned long mpidr,
/*******************************************************************************
* Export the platform handlers to enable psci to invoke them
******************************************************************************/
-static plat_pm_ops fvp_plat_pm_ops = {
+static plat_pm_ops_t fvp_plat_pm_ops = {
fvp_affinst_standby,
fvp_affinst_on,
fvp_affinst_off,
@@ -406,7 +406,7 @@ static plat_pm_ops fvp_plat_pm_ops = {
/*******************************************************************************
* Export the platform specific power ops & initialize the fvp power controller
******************************************************************************/
-int platform_setup_pm(plat_pm_ops **plat_ops)
+int platform_setup_pm(plat_pm_ops_t **plat_ops)
{
*plat_ops = &fvp_plat_pm_ops;
return 0;
diff --git a/plat/fvp/plat_security.c b/plat/fvp/plat_security.c
index 042eb816..32306cd4 100644
--- a/plat/fvp/plat_security.c
+++ b/plat/fvp/plat_security.c
@@ -44,7 +44,7 @@
*/
void plat_security_setup(void)
{
- struct tzc_instance controller;
+ tzc_instance_t controller;
/*
* The Base FVP has a TrustZone address space controller, the Foundation
diff --git a/plat/fvp/plat_topology.c b/plat/fvp/plat_topology.c
index 765077e3..99f32594 100644
--- a/plat/fvp/plat_topology.c
+++ b/plat/fvp/plat_topology.c
@@ -46,20 +46,20 @@
* marks the absent affinity level instances as PSCI_AFF_ABSENT e.g. there is no
* cluster 1 on the Foundation FVP. The 'data' field is currently unused.
******************************************************************************/
-typedef struct {
+typedef struct affinity_info {
unsigned char sibling;
unsigned char child;
unsigned char state;
unsigned int data;
-} affinity_info;
+} affinity_info_t;
/*******************************************************************************
* The following two data structures store the topology tree for the fvp. There
* is a separate array for each affinity level i.e. cpus and clusters. The child
* and sibling references allow traversal inside and in between the two arrays.
******************************************************************************/
-static affinity_info fvp_aff1_topology_map[PLATFORM_CLUSTER_COUNT];
-static affinity_info fvp_aff0_topology_map[PLATFORM_CORE_COUNT];
+static affinity_info_t fvp_aff1_topology_map[PLATFORM_CLUSTER_COUNT];
+static affinity_info_t fvp_aff0_topology_map[PLATFORM_CORE_COUNT];
/* Simple global variable to safeguard us from stupidity */
static unsigned int topology_setup_done;
diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h
index 2024a9bc..098f499d 100644
--- a/plat/fvp/platform.h
+++ b/plat/fvp/platform.h
@@ -340,10 +340,10 @@
#ifndef __ASSEMBLY__
-typedef volatile struct {
+typedef volatile struct mailbox {
unsigned long value
__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
-} mailbox;
+} mailbox_t;
/*******************************************************************************
* Function and variable prototypes
@@ -364,11 +364,11 @@ extern unsigned long warm_boot_entrypoint;
extern void bl1_plat_arch_setup(void);
extern void bl2_plat_arch_setup(void);
extern void bl31_plat_arch_setup(void);
-extern int platform_setup_pm(plat_pm_ops **);
+extern int platform_setup_pm(plat_pm_ops_t **);
extern unsigned int platform_get_core_pos(unsigned long mpidr);
extern void disable_mmu(void);
extern void enable_mmu(void);
-extern void configure_mmu(meminfo *,
+extern void configure_mmu(meminfo_t *,
unsigned long,
unsigned long,
unsigned long,
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-30 09:37:47 +0000