diff options
Diffstat (limited to 'plat/hisilicon/hikey/hikey_bl2_setup.c')
| -rw-r--r-- | plat/hisilicon/hikey/hikey_bl2_setup.c | 246 |
1 files changed, 43 insertions, 203 deletions
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index 3f5e4860..20bb7527 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,13 +17,11 @@ #include <hisi_mcu.h> #include <hisi_sram_map.h> #include <mmio.h> -#if LOAD_IMAGE_V2 #ifdef SPD_opteed #include <optee_utils.h> #endif -#endif +#include <platform.h> #include <platform_def.h> -#include <sp804_delay_timer.h> #include <string.h> #include "hikey_def.h" @@ -38,6 +36,8 @@ #define BL2_RO_BASE (unsigned long)(&__RO_START__) #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL2_RW_BASE (BL2_RO_LIMIT) + /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be @@ -48,50 +48,19 @@ #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) -static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); +static meminfo_t bl2_el3_tzram_layout; -#if !LOAD_IMAGE_V2 - -/******************************************************************************* - * This structure represents the superset of information that is passed to - * BL31, e.g. while passing control to it from BL2, bl31_params - * and other platform specific params - ******************************************************************************/ -typedef struct bl2_to_bl31_params_mem { - bl31_params_t bl31_params; - image_info_t bl31_image_info; - image_info_t bl32_image_info; - image_info_t bl33_image_info; - entry_point_info_t bl33_ep_info; - entry_point_info_t bl32_ep_info; - entry_point_info_t bl31_ep_info; -} bl2_to_bl31_params_mem_t; - -static bl2_to_bl31_params_mem_t bl31_params_mem; - -meminfo_t *bl2_plat_sec_mem_layout(void) -{ - return &bl2_tzram_layout; -} - -void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) -{ - scp_bl2_meminfo->total_base = SCP_BL2_BASE; - scp_bl2_meminfo->total_size = SCP_BL2_SIZE; - scp_bl2_meminfo->free_base = SCP_BL2_BASE; - scp_bl2_meminfo->free_size = SCP_BL2_SIZE; -} -#endif /* LOAD_IMAGE_V2 */ +enum { + BOOT_MODE_RECOVERY = 0, + BOOT_MODE_NORMAL, + BOOT_MODE_MASK = 1, +}; /******************************************************************************* * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. * Return 0 on success, -1 otherwise. ******************************************************************************/ -#if LOAD_IMAGE_V2 int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) -#else -int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info) -#endif { /* Enable MCU SRAM */ hisi_mcu_enable_sram(); @@ -161,7 +130,6 @@ uint32_t hikey_get_spsr_for_bl33_entry(void) } #endif /* AARCH32 */ -#if LOAD_IMAGE_V2 int hikey_bl2_handle_post_image_load(unsigned int image_id) { int err = 0; @@ -222,144 +190,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) return hikey_bl2_handle_post_image_load(image_id); } -#else /* LOAD_IMAGE_V2 */ - -bl31_params_t *bl2_plat_get_bl31_params(void) -{ - bl31_params_t *bl2_to_bl31_params = NULL; - - /* - * Initialise the memory for all the arguments that needs to - * be passed to BL3-1 - */ - memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); - - /* Assign memory for TF related information */ - bl2_to_bl31_params = &bl31_params_mem.bl31_params; - SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); - - /* Fill BL3-1 related information */ - bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, - VERSION_1, 0); - - /* Fill BL3-2 related information if it exists */ -#ifdef BL32_BASE - bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, - VERSION_1, 0); - bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, - VERSION_1, 0); -#endif - - /* Fill BL3-3 related information */ - bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, - PARAM_EP, VERSION_1, 0); - - /* BL3-3 expects to receive the primary CPU MPID (through x0) */ - bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); - - bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; - SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, - VERSION_1, 0); - - return bl2_to_bl31_params; -} - -struct entry_point_info *bl2_plat_get_bl31_ep_info(void) -{ -#if DEBUG - bl31_params_mem.bl31_ep_info.args.arg1 = HIKEY_BL31_PLAT_PARAM_VAL; -#endif - - return &bl31_params_mem.bl31_ep_info; -} - -void bl2_plat_set_bl31_ep_info(image_info_t *image, - entry_point_info_t *bl31_ep_info) -{ - SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); - bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); -} - -/******************************************************************************* - * Before calling this function BL32 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL32 and set SPSR and security state. - * On Hikey we only set the security state of the entrypoint - ******************************************************************************/ -#ifdef BL32_BASE -void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, - entry_point_info_t *bl32_ep_info) -{ - SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL32 image. - */ - bl32_ep_info->spsr = 0; -} - -/******************************************************************************* - * Populate the extents of memory available for loading BL32 - ******************************************************************************/ -void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) -{ - /* - * Populate the extents of memory available for loading BL32. - */ - bl32_meminfo->total_base = BL32_BASE; - bl32_meminfo->free_base = BL32_BASE; - bl32_meminfo->total_size = - (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; - bl32_meminfo->free_size = - (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; -} -#endif /* BL32_BASE */ - -void bl2_plat_set_bl33_ep_info(image_info_t *image, - entry_point_info_t *bl33_ep_info) -{ - unsigned long el_status; - unsigned int mode; - - /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - if (el_status) - mode = MODE_EL2; - else - mode = MODE_EL1; - - /* - * TODO: Consider the possibility of specifying the SPSR in - * the FIP ToC and allowing the platform to have a say as - * well. - */ - bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); - SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); -} - -void bl2_plat_flush_bl31_params(void) -{ - flush_dcache_range((unsigned long)&bl31_params_mem, - sizeof(bl2_to_bl31_params_mem_t)); -} - -void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) -{ - bl33_meminfo->total_base = DDR_BASE; - bl33_meminfo->total_size = DDR_SIZE; - bl33_meminfo->free_base = DDR_BASE; - bl33_meminfo->free_size = DDR_SIZE; -} -#endif /* LOAD_IMAGE_V2 */ - static void reset_dwmmc_clk(void) { unsigned int data; @@ -442,28 +272,53 @@ static void hikey_jumper_init(void) mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0); } -void bl2_early_platform_setup(meminfo_t *mem_layout) +void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4) { - dw_mmc_params_t params; - /* Initialize the console to provide early debug support */ console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); + /* + * Allow BL2 to see the whole Trusted RAM. + */ + bl2_el3_tzram_layout.total_base = BL2_RW_BASE; + bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; +} + +void bl2_el3_plat_arch_setup(void) +{ + hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base, + bl2_el3_tzram_layout.total_size, + BL2_RO_BASE, + BL2_RO_LIMIT, + BL2_COHERENT_RAM_BASE, + BL2_COHERENT_RAM_LIMIT); +} - /* Setup the BL2 memory layout */ - bl2_tzram_layout = *mem_layout; +void bl2_platform_setup(void) +{ + dw_mmc_params_t params; - /* Clear SRAM since it'll be used by MCU right now. */ - memset((void *)SRAM_BASE, 0, SRAM_SIZE); + hikey_sp804_init(); + hikey_gpio_init(); + hikey_pmussi_init(); + hikey_hi6553_init(); - sp804_timer_init(SP804_TIMER0_BASE, 10, 192); dsb(); hikey_ddr_init(); + hikey_security_setup(); + + /* Clear SRAM since it'll be used by MCU right now. */ + memset((void *)SRAM_BASE, 0, SRAM_SIZE); + clean_dcache_range(SRAM_BASE, SRAM_SIZE); hikey_boardid_init(); init_acpu_dvfs(); + hikey_rtc_init(); hikey_sd_init(); hikey_jumper_init(); + hikey_mmc_pll_init(); + reset_dwmmc_clk(); memset(¶ms, 0, sizeof(dw_mmc_params_t)); params.reg_base = DWMMC0_BASE; @@ -476,18 +331,3 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) hikey_io_setup(); } - -void bl2_plat_arch_setup(void) -{ - hikey_init_mmu_el1(bl2_tzram_layout.total_base, - bl2_tzram_layout.total_size, - BL2_RO_BASE, - BL2_RO_LIMIT, - BL2_COHERENT_RAM_BASE, - BL2_COHERENT_RAM_LIMIT); -} - -void bl2_platform_setup(void) -{ - hikey_security_setup(); -} |