diff options
Diffstat (limited to 'plat/imx/imx8mq')
-rw-r--r-- | plat/imx/imx8mq/ddr/lpddr4_dvfs.c | 3 | ||||
-rw-r--r-- | plat/imx/imx8mq/gpc.c | 5 | ||||
-rw-r--r-- | plat/imx/imx8mq/imx8mq_bl31_setup.c | 6 | ||||
-rw-r--r-- | plat/imx/imx8mq/include/ddrc.h | 27 | ||||
-rw-r--r-- | plat/imx/imx8mq/include/platform_def.h | 6 | ||||
-rw-r--r-- | plat/imx/imx8mq/platform.mk | 14 |
6 files changed, 48 insertions, 13 deletions
diff --git a/plat/imx/imx8mq/ddr/lpddr4_dvfs.c b/plat/imx/imx8mq/ddr/lpddr4_dvfs.c index 7adbf924..c7702290 100644 --- a/plat/imx/imx8mq/ddr/lpddr4_dvfs.c +++ b/plat/imx/imx8mq/ddr/lpddr4_dvfs.c @@ -109,6 +109,3 @@ int lpddr4_dvfs_handler(uint32_t smc_fid, return 0; } - - - diff --git a/plat/imx/imx8mq/gpc.c b/plat/imx/imx8mq/gpc.c index a094bd65..40d303c1 100644 --- a/plat/imx/imx8mq/gpc.c +++ b/plat/imx/imx8mq/gpc.c @@ -6,6 +6,7 @@ #include <debug.h> #include <delay_timer.h> +#include <dram.h> #include <stdlib.h> #include <stdint.h> #include <stdbool.h> @@ -391,10 +392,10 @@ void imx_set_sys_lpm(bool retention) SLPCR_BYPASS_PMIC_READY | SLPCR_RBC_EN); /* DDR enter retention */ - ddrc_enter_retention(); + dram_enter_retention(); } else { /* DDR exit retention */ - ddrc_exit_retention(); + dram_exit_retention(); } mmio_write_32(IMX_GPC_BASE + 0x14, val); diff --git a/plat/imx/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8mq/imx8mq_bl31_setup.c index 5fc21a56..46a4d76d 100644 --- a/plat/imx/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8mq/imx8mq_bl31_setup.c @@ -12,6 +12,7 @@ #include <context.h> #include <context_mgmt.h> #include <debug.h> +#include <dram.h> #include <generic_delay_timer.h> #include <stdbool.h> #include <mmio.h> @@ -20,6 +21,7 @@ #include <plat_imx8.h> #include <xlat_tables.h> #include <soc.h> +#include <string.h> #include <tzc380.h> #include <imx_csu.h> #include <imx_rdc.h> @@ -59,6 +61,7 @@ static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; + /* get SPSR for BL33 entry */ static uint32_t get_spsr_for_bl33_entry(void) { @@ -291,8 +294,7 @@ void bl31_platform_setup(void) /* gpc init */ imx_gpc_init(); - /* switch DDR frequency to 3200 mts */ - lpddr4_switch_to_3200(); + dram_info_init(SAVED_DRAM_TIMING_BASE); } entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) diff --git a/plat/imx/imx8mq/include/ddrc.h b/plat/imx/imx8mq/include/ddrc.h index 8eb42fd8..ed6ebfa1 100644 --- a/plat/imx/imx8mq/include/ddrc.h +++ b/plat/imx/imx8mq/include/ddrc.h @@ -297,6 +297,33 @@ #define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) #define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) +#define DRC_PERF_MON_BASE_ADDR(X) 0x3d800000 + (X * 0x2000000) +#define DRC_PERF_MON_CNT0_CTL(X) DRC_PERF_MON_BASE_ADDR(X) + 0x0 +#define DRC_PERF_MON_CNT1_CTL(X) DRC_PERF_MON_BASE_ADDR(X) + 0x4 +#define DRC_PERF_MON_CNT2_CTL(X) DRC_PERF_MON_BASE_ADDR(X) + 0x8 +#define DRC_PERF_MON_CNT3_CTL(X) DRC_PERF_MON_BASE_ADDR(X) + 0xC +#define DRC_PERF_MON_CNT0_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x20 +#define DRC_PERF_MON_CNT1_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x24 +#define DRC_PERF_MON_CNT2_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x28 +#define DRC_PERF_MON_CNT3_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x2C +#define DRC_PERF_MON_DPCR_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x30 +#define DRC_PERF_MON_MRR0_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x40 +#define DRC_PERF_MON_MRR1_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x44 +#define DRC_PERF_MON_MRR2_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x48 +#define DRC_PERF_MON_MRR3_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x4C +#define DRC_PERF_MON_MRR4_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x50 +#define DRC_PERF_MON_MRR5_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x54 +#define DRC_PERF_MON_MRR6_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x58 +#define DRC_PERF_MON_MRR7_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x5C +#define DRC_PERF_MON_MRR8_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x60 +#define DRC_PERF_MON_MRR9_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x64 +#define DRC_PERF_MON_MRR10_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x68 +#define DRC_PERF_MON_MRR11_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x6C +#define DRC_PERF_MON_MRR12_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x70 +#define DRC_PERF_MON_MRR13_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x74 +#define DRC_PERF_MON_MRR14_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x78 +#define DRC_PERF_MON_MRR15_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x7C + #define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) #define dwc_ddrphy_apb_rd(addr) mmio_read_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) #define dwc_ddrphy_apb_wr(addr, val) mmio_write_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), val) diff --git a/plat/imx/imx8mq/include/platform_def.h b/plat/imx/imx8mq/include/platform_def.h index f2c3d112..488175be 100644 --- a/plat/imx/imx8mq/include/platform_def.h +++ b/plat/imx/imx8mq/include/platform_def.h @@ -69,6 +69,12 @@ #define IMX_DDR_IPS_BASE 0x3d000000 #define IMX_ROM_BASE 0x0 +#define SAVED_DRAM_TIMING_BASE 0x40000000 + +#define HW_DRAM_PLL_CFG0 (IMX_ANAMIX_BASE + 0x60) +#define HW_DRAM_PLL_CFG1 (IMX_ANAMIX_BASE + 0x64) +#define HW_DRAM_PLL_CFG2 (IMX_ANAMIX_BASE + 0x68) + #define OCRAM_S_BASE 0x00180000 #define OCRAM_S_SIZE 0x8000 #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) diff --git a/plat/imx/imx8mq/platform.mk b/plat/imx/imx8mq/platform.mk index 93d61c41..456d7ced 100644 --- a/plat/imx/imx8mq/platform.mk +++ b/plat/imx/imx8mq/platform.mk @@ -7,11 +7,13 @@ PLAT_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ plat/common/plat_gicv3.c \ plat/imx/common/plat_imx8_gic.c -PLAT_DDR_SOURCES := plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c \ - plat/imx/imx8mq/ddr/lpddr4_phy_cfg.c \ - plat/imx/imx8mq/ddr/lpddr4_dvfs.c \ - plat/imx/imx8mq/ddr/lpddr4_swffc.c \ - plat/imx/imx8mq/ddr/lpddr4_retention.c +PLAT_DRAM_SOURCES := plat/imx/common/imx8m/dram.c \ + plat/imx/common/imx8m/clock.c \ + plat/imx/common/imx8m/lpddr4_retention.c \ + plat/imx/common/imx8m/ddr4_retention.c \ + plat/imx/common/imx8m/lpddr4_helper.c \ + plat/imx/common/imx8m/lpddr4_dvfs.c \ + plat/imx/common/imx8m/ddr4_dvfs.c BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/common/mxcuart_console.S \ @@ -32,7 +34,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ ${PLAT_GIC_SOURCES} \ - ${PLAT_DDR_SOURCES} \ + ${PLAT_DRAM_SOURCES} \ drivers/arm/tzc/tzc380.c ENABLE_PLAT_COMPAT := 0 |