diff options
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/xilinx/zynqmp/bl31_zynqmp_setup.c | 20 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/zynqmp_def.h | 4 |
2 files changed, 24 insertions, 0 deletions
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index d878b86b..c05b094e 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -118,11 +118,31 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); } +/* Enable the test setup */ +#ifndef ZYNQMP_TESTING +static void zynqmp_testing_setup(void) { } +#else +static void zynqmp_testing_setup(void) +{ + uint32_t actlr_el3, actlr_el2; + + /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ + actlr_el3 = read_actlr_el3(); + actlr_el2 = read_actlr_el2(); + + actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; + actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; + write_actlr_el3(actlr_el3); + write_actlr_el2(actlr_el2); +} +#endif + void bl31_platform_setup(void) { /* Initialize the gic cpu and distributor interfaces */ plat_arm_gic_driver_init(); plat_arm_gic_init(); + zynqmp_testing_setup(); } void bl31_plat_runtime_setup(void) diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/zynqmp_def.h index 4bb332e0..65bc25f8 100644 --- a/plat/xilinx/zynqmp/zynqmp_def.h +++ b/plat/xilinx/zynqmp/zynqmp_def.h @@ -201,4 +201,8 @@ #define ZYNQMP_CSU_VERSION_OFFSET 0x44 +/* Access control register defines */ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) + #endif /* __ZYNQMP_DEF_H__ */ |