diff options
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/arm/common/aarch32/arm_helpers.S | 6 | ||||
| -rw-r--r-- | plat/arm/common/aarch64/arm_helpers.S | 6 | ||||
| -rw-r--r-- | plat/hisilicon/hikey/platform.mk | 4 | ||||
| -rw-r--r-- | plat/hisilicon/hikey960/platform.mk | 4 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/aarch64/platform_common.c | 14 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/bl1_plat_setup.c | 36 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/bl2_plat_mem_params_desc.c | 166 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/bl2_plat_setup.c | 199 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/bl31_plat_setup.c | 55 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/include/plat_private.h | 1 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/include/platform_def.h | 26 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/include/poplar_layout.h | 2 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/plat_storage.c | 18 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/platform.mk | 42 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/poplar_image_load.c | 34 |
15 files changed, 561 insertions, 52 deletions
diff --git a/plat/arm/common/aarch32/arm_helpers.S b/plat/arm/common/aarch32/arm_helpers.S index f56b2153..c4cfa8a6 100644 --- a/plat/arm/common/aarch32/arm_helpers.S +++ b/plat/arm/common/aarch32/arm_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -68,10 +68,10 @@ endfunc plat_crash_console_putc * Function to force a write of all buffered * data that hasn't been output. * Out : return -1 on error else return 0. - * Clobber list : r0 - r1 + * Clobber list : r0 * --------------------------------------------- */ func plat_crash_console_flush - ldr r1, =PLAT_ARM_CRASH_UART_BASE + ldr r0, =PLAT_ARM_CRASH_UART_BASE b console_core_flush endfunc plat_crash_console_flush diff --git a/plat/arm/common/aarch64/arm_helpers.S b/plat/arm/common/aarch64/arm_helpers.S index 9d3a1081..760a53af 100644 --- a/plat/arm/common/aarch64/arm_helpers.S +++ b/plat/arm/common/aarch64/arm_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -70,11 +70,11 @@ endfunc plat_crash_console_putc * Function to force a write of all buffered * data that hasn't been output. * Out : return -1 on error else return 0. - * Clobber list : r0 - r1 + * Clobber list : r0 * --------------------------------------------- */ func plat_crash_console_flush - mov_imm x1, PLAT_ARM_CRASH_UART_BASE + mov_imm x0, PLAT_ARM_CRASH_UART_BASE b console_core_flush endfunc plat_crash_console_flush diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk index d43b20b3..36629140 100644 --- a/plat/hisilicon/hikey/platform.mk +++ b/plat/hisilicon/hikey/platform.mk @@ -9,11 +9,11 @@ LOAD_IMAGE_V2 := 1 # On Hikey, the TSP can execute from TZC secure area in DRAM (default) # or SRAM. -HIKEY_TSP_RAM_LOCATION := dram +HIKEY_TSP_RAM_LOCATION ?= dram ifeq (${HIKEY_TSP_RAM_LOCATION}, dram) HIKEY_TSP_RAM_LOCATION_ID = HIKEY_DRAM_ID else ifeq (${HIKEY_TSP_RAM_LOCATION}, sram) - HIKEY_TSP_RAM_LOCATION_ID := HIKEY_SRAM_ID + HIKEY_TSP_RAM_LOCATION_ID = HIKEY_SRAM_ID else $(error "Currently unsupported HIKEY_TSP_RAM_LOCATION value") endif diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk index cd063058..ffe10738 100644 --- a/plat/hisilicon/hikey960/platform.mk +++ b/plat/hisilicon/hikey960/platform.mk @@ -8,11 +8,11 @@ LOAD_IMAGE_V2 := 1 # On Hikey960, the TSP can execute from TZC secure area in DRAM. -HIKEY960_TSP_RAM_LOCATION := dram +HIKEY960_TSP_RAM_LOCATION ?= dram ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram) HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_DRAM_ID else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram) - HIKEY960_TSP_RAM_LOCATION_ID := HIKEY960_SRAM_ID + HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_SRAM_ID else $(error "Currently unsupported HIKEY960_TSP_RAM_LOCATION value") endif diff --git a/plat/hisilicon/poplar/aarch64/platform_common.c b/plat/hisilicon/poplar/aarch64/platform_common.c index 762bd846..54980650 100644 --- a/plat/hisilicon/poplar/aarch64/platform_common.c +++ b/plat/hisilicon/poplar/aarch64/platform_common.c @@ -29,10 +29,24 @@ TSP_SEC_MEM_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) +#if LOAD_IMAGE_V2 +#ifdef SPD_opteed +#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \ + POPLAR_OPTEE_PAGEABLE_LOAD_BASE, \ + POPLAR_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif +#endif + static const mmap_region_t poplar_mmap[] = { MAP_DDR, MAP_DEVICE, MAP_TSP_MEM, +#if LOAD_IMAGE_V2 +#ifdef SPD_opteed + MAP_OPTEE_PAGEABLE, +#endif +#endif {0} }; diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c index 7d6f10c2..39551135 100644 --- a/plat/hisilicon/poplar/bl1_plat_setup.c +++ b/plat/hisilicon/poplar/bl1_plat_setup.c @@ -38,23 +38,49 @@ meminfo_t *bl1_plat_sec_mem_layout(void) return &bl1_tzram_layout; } +#if LOAD_IMAGE_V2 +/******************************************************************************* + * Function that takes a memory layout into which BL2 has been loaded and + * populates a new memory layout for BL2 that ensures that BL1's data sections + * resident in secure RAM are not visible to BL2. + ******************************************************************************/ +void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, + meminfo_t *bl2_mem_layout) +{ + + assert(bl1_mem_layout != NULL); + assert(bl2_mem_layout != NULL); + + /* + * Cannot use default weak implementation in bl1main.c because + * BL1 RW data is not at the top of bl1_mem_layout + */ + bl2_mem_layout->total_base = BL2_BASE; + bl2_mem_layout->total_size = BL32_LIMIT - BL2_BASE; + + flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); +} +#endif /* LOAD_IMAGE_V2 */ + void bl1_early_platform_setup(void) { /* Initialize the console to provide early debug support */ console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); /* Allow BL1 to see the whole Trusted RAM */ - bl1_tzram_layout.total_base = BL_MEM_BASE; - bl1_tzram_layout.total_size = BL_MEM_SIZE; + bl1_tzram_layout.total_base = BL1_RW_BASE; + bl1_tzram_layout.total_size = BL1_RW_SIZE; +#if !LOAD_IMAGE_V2 /* Calculate how much RAM BL1 is using and how much remains free */ - bl1_tzram_layout.free_base = BL_MEM_BASE; - bl1_tzram_layout.free_size = BL_MEM_SIZE; + bl1_tzram_layout.free_base = BL1_RW_BASE; + bl1_tzram_layout.free_size = BL1_RW_SIZE; reserve_mem(&bl1_tzram_layout.free_base, &bl1_tzram_layout.free_size, BL1_RAM_BASE, BL1_RAM_LIMIT - BL1_RAM_BASE); +#endif INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, BL1_RAM_LIMIT - BL1_RAM_BASE); @@ -64,7 +90,7 @@ void bl1_plat_arch_setup(void) { plat_configure_mmu_el3(bl1_tzram_layout.total_base, bl1_tzram_layout.total_size, - BL_MEM_BASE, /* l-loader and BL1 ROM */ + BL1_RO_BASE, /* l-loader and BL1 ROM */ BL1_RO_LIMIT, BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT); diff --git a/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c b/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c new file mode 100644 index 00000000..c73ead8d --- /dev/null +++ b/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <bl_common.h> +#include <desc_image_load.h> +#include <platform.h> +#include <platform_def.h> + + +/******************************************************************************* + * Following descriptor provides BL image/ep information that gets used + * by BL2 to load the images and also subset of this information is + * passed to next BL image. The image loading sequence is managed by + * populating the images in required loading order. The image execution + * sequence is managed by populating the `next_handoff_image_id` with + * the next executable image id. + ******************************************************************************/ +static bl_mem_params_node_t bl2_mem_params_descs[] = { +#ifdef SCP_BL2_BASE + /* Fill SCP_BL2 related information if it exists */ + { + .image_id = SCP_BL2_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = SCP_BL2_SIZE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +#endif /* SCP_BL2_BASE */ + +#ifdef EL3_PAYLOAD_BASE + /* Fill EL3 payload related information (BL31 is EL3 payload)*/ + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + +#else /* EL3_PAYLOAD_BASE */ + + /* Fill BL31 related information */ + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), +#if DEBUG + .ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL, +#endif + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + +# ifdef BL32_BASE + .next_handoff_image_id = BL32_IMAGE_ID, +# else + .next_handoff_image_id = BL33_IMAGE_ID, +# endif + }, + +# ifdef BL32_BASE + /* Fill BL32 related information */ + { + .image_id = BL32_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + + .next_handoff_image_id = BL33_IMAGE_ID, + }, + + /* + * Fill BL32 external 1 related information. + * A typical use for extra1 image is with OP-TEE where it is the pager image. + */ + { + .image_id = BL32_EXTRA1_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + + /* + * Fill BL32 external 2 related information. + * A typical use for extra2 image is with OP-TEE where it is the paged image. + */ + { + .image_id = BL32_EXTRA2_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), +#ifdef SPD_opteed + .image_info.image_base = POPLAR_OPTEE_PAGEABLE_LOAD_BASE, + .image_info.image_max_size = POPLAR_OPTEE_PAGEABLE_LOAD_SIZE, +#endif + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +# endif /* BL32_BASE */ + + /* Fill BL33 related information */ + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), +# ifdef PRELOADED_BL33_BASE + .ep_info.pc = PRELOADED_BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), +# else + .ep_info.pc = PLAT_POPLAR_NS_IMAGE_OFFSET, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_POPLAR_NS_IMAGE_OFFSET, + .image_info.image_max_size = DDR_BASE + DDR_SIZE - + PLAT_POPLAR_NS_IMAGE_OFFSET, +# endif /* PRELOADED_BL33_BASE */ + + .next_handoff_image_id = INVALID_IMAGE_ID, + } +#endif /* EL3_PAYLOAD_BASE */ +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c index 7edfab7f..177630b0 100644 --- a/plat/hisilicon/poplar/bl2_plat_setup.c +++ b/plat/hisilicon/poplar/bl2_plat_setup.c @@ -9,11 +9,13 @@ #include <bl_common.h> #include <console.h> #include <debug.h> +#include <desc_image_load.h> #include <dw_mmc.h> #include <emmc.h> #include <errno.h> #include <generic_delay_timer.h> #include <mmio.h> +#include <optee_utils.h> #include <partition/partition.h> #include <platform.h> #include <string.h> @@ -28,6 +30,15 @@ #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); + +#if !LOAD_IMAGE_V2 + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL31, e.g. while passing control to it from BL2, bl31_params + * and other platform specific params + ******************************************************************************/ typedef struct bl2_to_bl31_params_mem { bl31_params_t bl31_params; image_info_t bl31_image_info; @@ -38,7 +49,6 @@ typedef struct bl2_to_bl31_params_mem { entry_point_info_t bl31_ep_info; } bl2_to_bl31_params_mem_t; -static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); static bl2_to_bl31_params_mem_t bl31_params_mem; meminfo_t *bl2_plat_sec_mem_layout(void) @@ -46,6 +56,159 @@ meminfo_t *bl2_plat_sec_mem_layout(void) return &bl2_tzram_layout; } +#ifdef SCP_BL2_BASE +void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) +{ + /* + * This platform has no SCP_BL2 yet + */ +} +#endif +#endif /* LOAD_IMAGE_V2 */ + +/******************************************************************************* + * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. + * Return 0 on success, -1 otherwise. + ******************************************************************************/ +#if LOAD_IMAGE_V2 +int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) +#else +int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info) +#endif +{ + /* + * This platform has no SCP_BL2 yet + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +uint32_t poplar_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL3-2 image. + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +#ifndef AARCH32 +uint32_t poplar_get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned int mode; + uint32_t spsr; + + /* Figure out what mode we enter the non-secure world in */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} +#else +uint32_t poplar_get_spsr_for_bl33_entry(void) +{ + unsigned int hyp_status, mode, spsr; + + hyp_status = GET_VIRT_EXT(read_id_pfr1()); + + mode = (hyp_status) ? MODE32_hyp : MODE32_svc; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); + return spsr; +} +#endif /* AARCH32 */ + +#if LOAD_IMAGE_V2 +int poplar_bl2_handle_post_image_load(unsigned int image_id) +{ + int err = 0; + bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); +#ifdef SPD_opteed + bl_mem_params_node_t *pager_mem_params = NULL; + bl_mem_params_node_t *paged_mem_params = NULL; +#endif + + assert(bl_mem_params); + + switch (image_id) { +#ifdef AARCH64 + case BL32_IMAGE_ID: +#ifdef SPD_opteed + pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); + assert(pager_mem_params); + + paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); + assert(paged_mem_params); + + err = parse_optee_header(&bl_mem_params->ep_info, + &pager_mem_params->image_info, + &paged_mem_params->image_info); + if (err != 0) { + WARN("OPTEE header parse error.\n"); + } + + /* + * OP-TEE expect to receive DTB address in x2. + * This will be copied into x2 by dispatcher. + * Set this (arg3) if necessary + */ + /* bl_mem_params->ep_info.args.arg3 = PLAT_HIKEY_DT_BASE; */ +#endif + bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl32_entry(); + break; +#endif + + case BL33_IMAGE_ID: + /* BL33 expects to receive the primary CPU MPID (through r0) */ + bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); + bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl33_entry(); + break; + +#ifdef SCP_BL2_BASE + case SCP_BL2_IMAGE_ID: + /* The subsequent handling of SCP_BL2 is platform specific */ + err = plat_poplar_bl2_handle_scp_bl2(&bl_mem_params->image_info); + if (err) { + WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); + } + break; +#endif + } + + return err; +} + +/******************************************************************************* + * This function can be used by the platforms to update/use image + * information for given `image_id`. + ******************************************************************************/ +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + return poplar_bl2_handle_post_image_load(image_id); +} + +#else /* LOAD_IMAGE_V2 */ + bl31_params_t *bl2_plat_get_bl31_params(void) { bl31_params_t *bl2_to_bl31_params = NULL; @@ -92,6 +255,10 @@ bl31_params_t *bl2_plat_get_bl31_params(void) struct entry_point_info *bl2_plat_get_bl31_ep_info(void) { +#if DEBUG + bl31_params_mem.bl31_ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL; +#endif + return &bl31_params_mem.bl31_ep_info; } @@ -138,32 +305,11 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) } #endif /* BL32_BASE */ -static uint32_t hisi_get_spsr_for_bl33_entry(void) -{ - unsigned long el_status; - unsigned int mode; - uint32_t spsr; - - /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - mode = (el_status) ? MODE_EL2 : MODE_EL1; - - /* - * TODO: Consider the possibility of specifying the SPSR in - * the FIP ToC and allowing the platform to have a say as - * well. - */ - spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); - return spsr; -} - void bl2_plat_set_bl33_ep_info(image_info_t *image, entry_point_info_t *bl33_ep_info) { SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); - bl33_ep_info->spsr = hisi_get_spsr_for_bl33_entry(); + bl33_ep_info->spsr = poplar_get_spsr_for_bl33_entry(); bl33_ep_info->args.arg2 = image->image_size; } @@ -180,6 +326,7 @@ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) bl33_meminfo->free_base = DDR_BASE; bl33_meminfo->free_size = DDR_SIZE; } +#endif /* LOAD_IMAGE_V2 */ void bl2_early_platform_setup(meminfo_t *mem_layout) { @@ -217,7 +364,11 @@ void bl2_platform_setup(void) { } -unsigned long plat_get_ns_image_entrypoint(void) +uintptr_t plat_get_ns_image_entrypoint(void) { +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else return PLAT_POPLAR_NS_IMAGE_OFFSET; +#endif } diff --git a/plat/hisilicon/poplar/bl31_plat_setup.c b/plat/hisilicon/poplar/bl31_plat_setup.c index e3a5c50f..ec72acdb 100644 --- a/plat/hisilicon/poplar/bl31_plat_setup.c +++ b/plat/hisilicon/poplar/bl31_plat_setup.c @@ -59,14 +59,64 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) return NULL; } +/******************************************************************************* + * Perform any BL31 early platform setup common to ARM standard platforms. + * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 + * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be + * done before the MMU is initialized so that the memory layout can be used + * while creating page tables. BL2 has flushed this information to memory, so + * we are guaranteed to pick up good data. + ******************************************************************************/ +#if LOAD_IMAGE_V2 +void bl31_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2) +#else void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) +#endif { console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); /* Init console for crash report */ plat_crash_console_init(); +#if LOAD_IMAGE_V2 + /* + * Check params passed from BL2 should not be NULL, + */ + bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; + + assert(params_from_bl2 != NULL); + assert(params_from_bl2->h.type == PARAM_BL_PARAMS); + assert(params_from_bl2->h.version >= VERSION_2); + + bl_params_node_t *bl_params = params_from_bl2->head; + + /* + * Copy BL33 and BL32 (if present), entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + while (bl_params) { + if (bl_params->image_id == BL32_IMAGE_ID) + bl32_image_ep_info = *bl_params->ep_info; + + if (bl_params->image_id == BL33_IMAGE_ID) + bl33_image_ep_info = *bl_params->ep_info; + + bl_params = bl_params->next_params_info; + } + + if (bl33_image_ep_info.pc == 0) + panic(); + +#else /* LOAD_IMAGE_V2 */ + + /* + * Check params passed from BL2 should not be NULL, + */ + assert(params_from_bl2 != NULL); + assert(params_from_bl2->h.type == PARAM_BL31); + assert(params_from_bl2->h.version >= VERSION_1); /* * Copy BL32 (if populated by BL2) and BL33 entry point information. @@ -75,6 +125,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, if (from_bl2->bl32_ep_info) bl32_image_ep_info = *from_bl2->bl32_ep_info; bl33_image_ep_info = *from_bl2->bl33_ep_info; +#endif /* LOAD_IMAGE_V2 */ } void bl31_platform_setup(void) @@ -97,8 +148,8 @@ void bl31_plat_runtime_setup(void) void bl31_plat_arch_setup(void) { - plat_configure_mmu_el3(BL31_RO_BASE, - (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), + plat_configure_mmu_el3(BL31_BASE, + (BL31_LIMIT - BL31_BASE), BL31_RO_BASE, BL31_RO_LIMIT, BL31_COHERENT_RAM_BASE, diff --git a/plat/hisilicon/poplar/include/plat_private.h b/plat/hisilicon/poplar/include/plat_private.h index e2272cc6..845b1bd7 100644 --- a/plat/hisilicon/poplar/include/plat_private.h +++ b/plat/hisilicon/poplar/include/plat_private.h @@ -24,7 +24,6 @@ void plat_configure_mmu_el1(unsigned long total_base, unsigned long coh_start, unsigned long coh_limit); -void plat_delay_timer_init(void); void plat_io_setup(void); #endif /* __PLAT_PRIVATE_H__ */ diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h index c0f83711..805c152a 100644 --- a/plat/hisilicon/poplar/include/platform_def.h +++ b/plat/hisilicon/poplar/include/platform_def.h @@ -16,6 +16,9 @@ #include "hi3798cv200.h" #include "poplar_layout.h" /* BL memory region sizes, etc */ +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define POPLAR_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 @@ -39,9 +42,20 @@ #define MAX_IO_HANDLES (4) #define MAX_IO_BLOCK_DEVICES (2) +/* Memory size options */ +#define POPLAR_DRAM_SIZE_1G 0 +#define POPLAR_DRAM_SIZE_2G 1 + /* Memory map related constants */ #define DDR_BASE (0x00000000) + +#if (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_2G) +#define DDR_SIZE (0x80000000) +#elif (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_1G) #define DDR_SIZE (0x40000000) +#else +#error "Currently unsupported POPLAR_DRAM_SIZE_ID value" +#endif #define DEVICE_BASE (0xF0000000) #define DEVICE_SIZE (0x0F000000) @@ -64,10 +78,6 @@ #define DDR_SEC_SIZE 0x01000000 #define DDR_SEC_BASE 0x03000000 -#define BL_MEM_BASE (BL1_RO_BASE) -#define BL_MEM_LIMIT (BL31_LIMIT) -#define BL_MEM_SIZE (BL_MEM_LIMIT - BL_MEM_BASE) - /* * BL3-2 specific defines. */ @@ -78,6 +88,14 @@ #define BL32_DRAM_BASE 0x03000000 #define BL32_DRAM_LIMIT 0x04000000 +#if LOAD_IMAGE_V2 +#ifdef SPD_opteed +/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ +#define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ +#define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */ +#endif +#endif + #if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID) #define TSP_SEC_MEM_BASE BL32_DRAM_BASE #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) diff --git a/plat/hisilicon/poplar/include/poplar_layout.h b/plat/hisilicon/poplar/include/poplar_layout.h index 9ce04342..9fb5a94c 100644 --- a/plat/hisilicon/poplar/include/poplar_layout.h +++ b/plat/hisilicon/poplar/include/poplar_layout.h @@ -88,7 +88,7 @@ #define BL1_RO_SIZE 0x00008000 /* page multiple */ #define BL1_RW_SIZE 0x00008000 /* page multiple */ #define BL1_SIZE (BL1_RO_SIZE + BL1_RW_SIZE) -#define BL2_SIZE 0x0000c000 /* page multiple */ +#define BL2_SIZE 0x0000d000 /* page multiple */ #define BL31_SIZE 0x00014000 #if !POPLAR_RECOVERY /* diff --git a/plat/hisilicon/poplar/plat_storage.c b/plat/hisilicon/poplar/plat_storage.c index 468e2292..db52c676 100644 --- a/plat/hisilicon/poplar/plat_storage.c +++ b/plat/hisilicon/poplar/plat_storage.c @@ -70,6 +70,14 @@ static const io_uuid_spec_t bl32_uuid_spec = { .uuid = UUID_SECURE_PAYLOAD_BL32, }; +static const io_uuid_spec_t bl32_extra1_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, +}; + +static const io_uuid_spec_t bl32_extra2_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, +}; + static const io_uuid_spec_t bl33_uuid_spec = { .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, }; @@ -109,6 +117,16 @@ static const struct plat_io_policy policies[] = { (uintptr_t)&bl32_uuid_spec, open_fip }, + [BL32_EXTRA1_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra1_uuid_spec, + open_fip + }, + [BL32_EXTRA2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra2_uuid_spec, + open_fip + }, [BL33_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl33_uuid_spec, diff --git a/plat/hisilicon/poplar/platform.mk b/plat/hisilicon/poplar/platform.mk index d53e0627..7c8027ea 100644 --- a/plat/hisilicon/poplar/platform.mk +++ b/plat/hisilicon/poplar/platform.mk @@ -4,20 +4,42 @@ # SPDX-License-Identifier: BSD-3-Clause # +# Enable version2 of image loading +LOAD_IMAGE_V2 := 1 + # On Poplar, the TSP can execute from TZC secure area in DRAM. -POPLAR_TSP_RAM_LOCATION := dram +POPLAR_TSP_RAM_LOCATION ?= dram ifeq (${POPLAR_TSP_RAM_LOCATION}, dram) POPLAR_TSP_RAM_LOCATION_ID = POPLAR_DRAM_ID -else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram) - POPLAR_TSP_RAM_LOCATION_ID := POPLAR_SRAM_ID +else ifeq (${POPLAR_TSP_RAM_LOCATION}, sram) + POPLAR_TSP_RAM_LOCATION_ID = POPLAR_SRAM_ID else $(error "Currently unsupported POPLAR_TSP_RAM_LOCATION value") endif $(eval $(call add_define,POPLAR_TSP_RAM_LOCATION_ID)) +POPLAR_DRAM_SIZE ?= two_gig +ifeq (${POPLAR_DRAM_SIZE}, two_gig) + POPLAR_DRAM_SIZE_ID = POPLAR_DRAM_SIZE_2G +else ifeq (${POPLAR_DRAM_SIZE}, one_gig) + POPLAR_DRAM_SIZE_ID = POPLAR_DRAM_SIZE_1G +else + $(error "Currently unsupported POPLAR_DRAM_SIZE value") +endif +$(eval $(call add_define,POPLAR_DRAM_SIZE_ID)) + POPLAR_RECOVERY := 0 $(eval $(call add_define,POPLAR_RECOVERY)) +# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images +# in the FIP if the platform requires. +ifneq ($(BL32_EXTRA1),) +$(eval $(call FIP_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1)) +endif +ifneq ($(BL32_EXTRA2),) +$(eval $(call FIP_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2)) +endif + NEED_BL33 := yes COLD_BOOT_SINGLE_CPU := 1 @@ -68,8 +90,7 @@ BL1_SOURCES += \ drivers/io/io_fip.c \ drivers/io/io_memmap.c \ plat/hisilicon/poplar/bl1_plat_setup.c \ - plat/hisilicon/poplar/plat_storage.c \ - + plat/hisilicon/poplar/plat_storage.c BL2_SOURCES += \ drivers/arm/pl061/pl061_gpio.c \ @@ -83,6 +104,17 @@ BL2_SOURCES += \ plat/hisilicon/poplar/bl2_plat_setup.c \ plat/hisilicon/poplar/plat_storage.c +ifeq (${LOAD_IMAGE_V2},1) +BL2_SOURCES += \ + plat/hisilicon/poplar/bl2_plat_mem_params_desc.c \ + plat/hisilicon/poplar/poplar_image_load.c \ + common/desc_image_load.c + +ifeq (${SPD},opteed) +BL2_SOURCES += \ + lib/optee/optee_utils.c +endif +endif BL31_SOURCES += \ lib/cpus/aarch64/aem_generic.S \ diff --git a/plat/hisilicon/poplar/poplar_image_load.c b/plat/hisilicon/poplar/poplar_image_load.c new file mode 100644 index 00000000..32ca36db --- /dev/null +++ b/plat/hisilicon/poplar/poplar_image_load.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <bl_common.h> +#include <desc_image_load.h> +#include <platform.h> + +/******************************************************************************* + * This function flushes the data structures so that they are visible + * in memory for the next BL image. + ******************************************************************************/ +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +/******************************************************************************* + * This function returns the list of loadable images. + ******************************************************************************/ +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +/******************************************************************************* + * This function returns the list of executable images. + ******************************************************************************/ +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} |