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2018-01-20Merge pull request #1229 from ↵davidcunado-arm
manojkumar-arm/manojkumar-arm/ca72-aarch32-reset-fix lib/cpus: fix branching in reset function for cortex-a72 AARCH32 mode
2018-01-19Merge pull request #1227 from geesun/qx/emmc_macrosdavidcunado-arm
emmc: add macros CMD21, BUS_WIDTH_DDR_4 and BUS_WIDTH_DDR_8
2018-01-19Merge pull request #1200 from robertovargas-arm/bl2-el3davidcunado-arm
Add BL2_AT_EL3 build option
2018-01-19lib/cpus: fix branching in reset function for cortex-a72 AARCH32 modeManoj Kumar
In AARCH32 mode, cortex_a72_reset_func branches to address in lr register instead of r5 register. This leads to linux boot failure of Cortex-A72 cores in AARCH32 mode on Juno-R2 board. This patch fixes the branching of cortex_a72_reset_func to r5 register as in cortex_a57_reset_func implementation. Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
2018-01-18bl2-el3: Don't compile BL1 when BL2_AT_EL3 is defined in FVPRoberto Vargas
This patch modifies the makefiles to avoid the definition of BL1_SOURCES and BL2_SOURCES in the tbbr makefiles, and it lets to the platform makefiles to define them if they actually need these images. In the case of BL2_AT_EL3 BL1 will not be needed usually because the Boot ROM will jump directly to BL2. Change-Id: Ib6845a260633a22a646088629bcd7387fe35dcf9 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-18bl2-el3: Don't include BL2 in fip for BL2 at EL3Roberto Vargas
It is better to not include BL2 in FIP when using `BL2 at EL3` as platforms using this config would not have the capability to parse the FIP format in Boot ROM and BL2 needs to be loaded independently. This patch does the required changes for the same. Change-Id: Iad285c247b3440e2d827fef97c3dd81f5c09cabc Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-18bl2-el3: Add documentation for BL2 at EL3Roberto Vargas
Update firmware-design.rst, porting-guide.rst and user-guide.rst with the information about BL2 at EL3. Firmware-design.rst is also update to explain how to test this feauture with FVP. Change-Id: I86d64bc64594e13eb041cea9cefa3f7f3fa745bd Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-18bl2-el3: Mark all the assembly functions in bl2 at el3Roberto Vargas
When BL2_AT_EL3 option is enabled some platforms are going to need a resident part in BL2 because the boot rom may jump to it after a reset. This patch introduces __TEXT_RESIDENT_START__ and __TEXT_RESIDENT_END__ linker symbols that mark the resident region. Change-Id: Ib20c1b8ee257831bcc0ca7d3df98d0cb617a04f8 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-18Mark functions defined in assembly filesRoberto Vargas
This patch change the name of the section containing the functions defined in assembly files from text.* to text.asm.*. This change makes possible to select in the linker script the functions defined in those files. Change-Id: If35e44ef1b43ffd951dfac5e052db75d7198e2e0 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-18bl2-el3: Add BL2 at EL3 support in FVPRoberto Vargas
This patch add supports for the new API added for BL2 at EL3 for FVP. We don't have a non-TF Boot ROM for FVP, but this option can be tested setting specific parameters in the model. The bl2 image is loaded directly in memory instead of being loaded by a non-TF Boot ROM and the reset address is changed: --data cluster0.cpu0=bl2.bin@0x4001000 -C cluster0.cpu0.RVBAR=0x4001000 These parameters mean that in the cold boot path the processor will jump to BL2 again. For this reason, BL2 is loaded in dram in this case, to avoid other images reclaiming BL2 memory. Change-Id: Ieb2ff8535a9e67ccebcd8c2212cad366e7776422 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-18bl2-el3: Add BL2_EL3 imageRoberto Vargas
This patch enables BL2 to execute at the highest exception level without any dependancy on TF BL1. This enables platforms which already have a non-TF Boot ROM to directly load and execute BL2 and subsequent BL stages without need for BL1. This is not currently possible because BL2 executes at S-EL1 and cannot jump straight to EL3. Change-Id: Ief1efca4598560b1b8c8e61fbe26d1f44e929d69 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-17Merge pull request #1226 from masahir0y/utilsdavidcunado-arm
utils: rename struct mem_region_t to struct mem_region
2018-01-17Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_statedavidcunado-arm
Hikey960: Remove ca73 cpu nap state
2018-01-17emmc: add macros CMD21, BUS_WIDTH_DDR_4 and BUS_WIDTH_DDR_8Qixiang Xu
Add some macros according to JEDEC Standard Embedded Multi-Media Card (eMMC) Electrical Standard (5.1)": Table 145 - Bus Mode Selection. Change-Id: Iaa45e0582653ef4290efd60d039f0bdc420eeb47 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
2018-01-16utils: rename struct mem_region_t to struct mem_regionMasahiro Yamada
typedef mem_region_t mem_region_t; ... seems to work because they belong to different name-spaces, but humans are confused even if compilers are not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-16Hikey960: Change CPU standby state for WFILeo Yan
At early time, the CPU CA73 retention state has been supported on Hikey960. Later we found the system has the hang issue and for resolving this issue Hisilicon released new MCU firmware, but unfortunately the new MCU firmware has side effect and results in the CA73 CPU cannot really enter retention state and roll back to WFI state. After discussion we cannot see the possibility to enable CA73 retention state anymore on Hikey960, based on this conclusion we should remove this state supporting from ARM-TF and roll back to WFI state only. We will commit one patch to remove CA73 CPU retention state in kernel DT binding as well. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Kevin Wang <jean.wangtao@linaro.org> Cc: Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org>
2018-01-16Revert "Hikey960: Change to use recommended power state id format"Leo Yan
This reverts commit fdae60b6ba27c216fd86d13b7432a1ff4f57dd84. The commit fdae60b6ba27c216fd86d13b7432a1ff4f57dd84 changed the parameter encoding for the hikey960. However that implies a DT change in the kernel side. After submitting the DT change for upstreaming, the backward compatibility issue and the interface change raise some concerns from the Linux community about the issues related to kernel <-> ATF alignment. There is no way to detect a mis-alignment of those without a deep knowledge of the ATF and the kernel. Furthermore, the failing calls to PSCI in the idle path (because of bad parameters), will lead to busy looping, implying: thermal issues and extra energy consumption. In regard of the Linux community concerns, the potential issues when the ATF and the kernel are not aligned, it is preferable to revert the commit. Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Kevin Wang <jean.wangtao@linaro.org> Co-authored-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org>
2018-01-16Merge pull request #1221 from hzhuang1/fix_HLEdavidcunado-arm
emmc/dw_mmc: fix the assert on HLE bit
2018-01-16Merge pull request #1219 from antonio-nino-diaz-arm/an/mm-versiondavidcunado-arm
SPM: Fix version header definitions
2018-01-16Merge pull request #1218 from antonio-nino-diaz-arm/an/xlat-fixdavidcunado-arm
xlat v2: Correctly unmap regions on map error
2018-01-16Merge pull request #1216 from hzhuang1/fix_pscidavidcunado-arm
Hikey960: Fix hikey960 pcie mount fail
2018-01-16Merge pull request #1215 from vwadekar/tlkd-ns-dram-rangesdavidcunado-arm
spd: tlkd: support for "NS memory ranges" function ID
2018-01-15Merge pull request #1217 from robertovargas-arm/doc-plat_try_next_boot_sourcedavidcunado-arm
Add documentation about plat_try_next_boot_source to bl1_platform_setup
2018-01-15Merge pull request #1213 from masahir0y/uniphierdavidcunado-arm
uniphier: clean-up platform makefile
2018-01-15Merge pull request #1225 from dp-arm/dp/amu-remove-warndavidcunado-arm
AMU: Remove unnecessary WARN()
2018-01-15AMU: Remove unnecessary WARN()Dimitris Papastamos
If AMU is not supported by the hardware but it is enabled in Trusted Firmware, the console will be spammed with warnings every time a CPU is brought up with a CPU ON call. Remove the warning message as this is more in line with how other extensions like SPE and SVE are handled. Change-Id: Iba6d367e4d1375ab554d23d2eaceab3ae1362c5a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-12Merge pull request #1197 from dp-arm/dp/amudavidcunado-arm
AMUv1 support
2018-01-11Merge pull request #1214 from dp-arm/dp/cve_2017_5715davidcunado-arm
Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75
2018-01-11Merge pull request #1222 from davidcunado-arm/dp/bl31_memdavidcunado-arm
Increase BL31 memory space by 2 pages
2018-01-11Increase BL31 memory space by 2 pagesDimitris Papastamos
On some build configurations BL31 is running out of space. Now that TSP is moved to secure dram, we have a bit of additional space to use in BL31. Change-Id: Ib89fcd8bae99c85c9c5e5d9228bb42fb7048dcb6 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Signed-off-by: David Cunado <david.cunado@arm.com>
2018-01-11Add hooks to save/restore AMU context for Cortex A75Dimitris Papastamos
Change-Id: I504d3f65ca5829bc1f4ebadb764931f8379ee81f Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11AMU: Add hooks to save/restore AMU contextDimitris Papastamos
On some systems, the AMU counters might reset to 0 when a CPU powerdown happens. This behaviour conflicts with the intended use-case of AMU as lower ELs are only expected to see non-decreasing counter values. Change-Id: If25519965d4e6e47e09225d0e732947986cbb5ec Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11AMU: Add configuration helpers for aarch64Dimitris Papastamos
Add some AMU helper functions to allow configuring, reading and writing of the Group 0 and Group 1 counters. Documentation for these helpers will come in a separate patch. Change-Id: I656e070d2dae830c22414f694aa655341d4e2c40 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11AMU: Add plat interface to select which group 1 counters to enableDimitris Papastamos
A new platform macro `PLAT_AMU_GROUP1_COUNTERS_MASK` controls which group 1 counters should be enabled. The maximum number of group 1 counters supported by AMUv1 is 16 so the mask can be at most 0xffff. If the platform does not define this mask, no group 1 counters are enabled. A related platform macro `PLAT_AMU_GROUP1_NR_COUNTERS` is used by generic code to allocate an array to save and restore the counters on CPU suspend. Change-Id: I6d135badf4846292de931a43bb563077f42bb47b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11Add PubSub events for CPU powerdown/powerupDimitris Papastamos
The suspend hook is published at the start of a CPU powerdown operation. The resume hook is published at the end of a CPU powerup operation. Change-Id: I50c05e2dde0d33834095ac41b4fcea4c161bb434 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11Use PFR0 to identify need for mitigation of CVE-2017-5915Dimitris Papastamos
If the CSV2 field reads as 1 then branch targets trained in one context cannot affect speculative execution in a different context. In that case skip the workaround on Cortex A75. Change-Id: I4d5504cba516a67311fb5f0657b08f72909cbd38 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11Workaround for CVE-2017-5715 on Cortex A73 and A75Dimitris Papastamos
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by temporarily dropping into AArch32 Secure-EL1 and executing the `BPIALL` instruction. This is achieved by using 3 vector tables. There is the runtime vector table which is used to handle exceptions and 2 additional tables which are required to implement this workaround. The additional tables are `vbar0` and `vbar1`. The sequence of events for handling a single exception is as follows: 1) Install vector table `vbar0` which saves the CPU context on entry to EL3 and sets up the Secure-EL1 context to execute in AArch32 mode with the MMU disabled and I$ enabled. This is the default vector table. 2) Before doing an ERET into Secure-EL1, switch vbar to point to another vector table `vbar1`. This is required to restore EL3 state when returning from the workaround, before proceeding with normal EL3 exception handling. 3) While in Secure-EL1, the `BPIALL` instruction is executed and an SMC call back to EL3 is performed. 4) On entry to EL3 from Secure-EL1, the saved context from step 1) is restored. The vbar is switched to point to `vbar0` in preparation to handle further exceptions. Finally a branch to the runtime vector table entry is taken to complete the handling of the original exception. This workaround is enabled by default on the affected CPUs. NOTE ==== There are 4 different stubs in Secure-EL1. Each stub corresponds to an exception type such as Sync/IRQ/FIQ/SError. Each stub will move a different value in `R0` before doing an SMC call back into EL3. Without this piece of information it would not be possible to know what the original exception type was as we cannot use `ESR_EL3` to distinguish between IRQs and FIQs. Change-Id: I90b32d14a3735290b48685d43c70c99daaa4b434 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11Workaround for CVE-2017-5715 on Cortex A57 and A72Dimitris Papastamos
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling and enabling the MMU. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. This workaround is enabled by default on the affected CPUs. Change-Id: I97788d38463a5840a410e3cea85ed297a1678265 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11emmc/dw_mmc: fix the assert on HLE bitHaojian Zhuang
When check HLE bit in interrupt register, it should check whether HLE bit is set, not clear. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2018-01-10xlat v2: Correctly unmap regions on map errorAntonio Nino Diaz
`mm_cursor` doesn't have the needed data because the `memmove()` that is called right before it overwrites that information. In order to get the information of the region that was being mapped, `mm` has to be used instead (like it is done to fill the fields of `unmap_mm`). If the incorrect information is read, this check isn't reliable and `xlat_tables_unmap_region` may be requested to unmap memory that isn't mapped at all, triggering assertions. Change-Id: I602d4ac83095d4e5dac9deb34aa5d00d00e6c289 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-01-10SPM: Fix version header definitionsAntonio Nino Diaz
Rename SP_VERSION macros to MM_VERSION, which is the name used in the MM specification [1]. Also, a few more helper macros have been added. MM-specific definitions have been moved to their own header file. [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0060a/DEN0060A_ARM_MM_Interface_Specification.pdf Change-Id: Ia10e48c7e81a7a1f5eeca29a5270cae740a4a88a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-01-10Merge pull request #1176 from wjliang/zynqmp-ipi-mb-svcdavidcunado-arm
plat: xilinx: Add ZynqMP IPI mailbox service [v4]
2018-01-10Add documentation about plat_try_next_boot_source to bl1_platform_setupRoberto Vargas
If boot redundancy is required in BL1 then the initialization of the boot sequence must be done in bl1_platform_setup. In BL2, we had to add a new function, bl2_preload_setup, because bl2_platform_setup is called after the images are loaded, making it invalid for the boot sequence initialization. Change-Id: I5c177ff142608ed38b4192288b06614343b2b83b Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-10Merge pull request #1208 from masahir0y/builddavidcunado-arm
Build: trivial fixes
2018-01-10Merge pull request #1207 from hzhuang1/isp_clkdavidcunado-arm
hikey960: set isp clks as unsecure mode
2018-01-09Hikey960: Fix hikey960 pcie mount failKaihua Zhong
Set IOC_AO_IOMG_033 function from GPIO213 to PCIE_CLKREQ_N bit[0-2]: 000: GPIO_213; 001: PCIE_CLKREQ_N; 010: GPIO_018_SH; 100: GPIO_014_SE; 110: FAC_TEST24; 111: FAC_TEST24; bit[3-31]: reserved Signed-off-by: Guangtao Zhang <zhangguangtao@hisilicon.com> Tested-by: Yao Chen <chenyao11@huawei.com> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2018-01-09Merge pull request #1167 from Leo-Yan/hikey-fix-alignmentdavidcunado-arm
Set alignment size to 512B for Hikey/Hikey960
2018-01-08zynqmp: pm_service: use zynqmp_ipi APIsWendy Liang
Use zynqmp_ipi APIs to access IPI registers in pm_service. As the zynqmp_ipi APIs doesn't cover IPI buffers, the pm_ipi in pm_service will still directly access the IPI buffers. Signed-off-by: Wendy Liang <jliang@xilinx.com>
2018-01-08Add Xilinx ZynqMP IPI mailbox serviceWendy Liang
Add IPI mailbox service to manage Xilinx ZynqMP IPI(Inter Processors Interrupt) access. Signed-off-by: Wendy Liang <jliang@xilinx.com>
2018-01-08Introduce ZynqMP IPI implementationWendy Liang
Previously, ZynqMP IPI in ATF is only for ZynqMP PM, This patch is to have a ZynqMP IPI implementation to handle both ZynqMP PM IPI requirement and IPI mailbox service requirement which will be introduced next. We control IPI agents registers access but not IPI buffers access in this implementation. Each IPI mailbox user will directly access the IPI buffers. Signed-off-by: Wendy Liang <jliang@xilinx.com>
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