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The array of affinity nodes is currently allocated for 32 entries
with the PSCI_NUM_AFFS value defined in psci.h. This is not enough
for large systems, and will substantially over allocate the array
for small systems.
This patch introduces an optional platform definition
PLATFORM_NUM_AFFS to platform_def.h. If defined this value is
used for PSCI_NUM_AFFS, otherwise a value of two times the number
of CPU cores is used.
The FVP port defines PLATFORM_NUM_AFFS to be 10 which saves
nearly 1.5KB of memory.
Fixes ARM-software/tf-issues#192
Change-Id: I68e30ac950de88cfbd02982ba882a18fb69c1445
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psci_suspend_context is an array of cache-line aligned structures
containing the single power_state integer per cpu. This array is
the only structure indexed by the aff_map_node.data integer.
This patch saves 2KB of BL3-1 memory by placing the CPU
power_state value directly in the aff_map_node structure. As a
result, this value is now never cached and the cache clean when
writing the value is no longer required.
Fixes ARM-software/tf-issues#195
Change-Id: Ib4c70c8f79eed295ea541e7827977a588a19ef9b
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Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
* The first uses entry_point_info to initialize the relevant
cpu_context for first entry into a lower exception level on a CPU
* The second populates the EL1 and EL2 system registers as needed
from the cpu_context to ensure correct entry into the lower EL
This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).
In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.
Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
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Move CPU context pointers into cpu_data
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Remove early_exceptions from BL3-1
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Per-cpu data cache restructuring
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Remove broken assertion in console_putc()
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The assertion in console_putc() would trigger a recursion that
exhausts the stack and eventually aborts.
This patch replaces the assertion with an error return if the
console has not been initialized yet.
Fixes ARM-software/tf-issues#208
Change-Id: I95f736ff215d69655eb5ba7ceac70dc1409d986a
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Remove re-initialisation of system timers after warm boot for FVP
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This patch removes the reinitialisation of memory mapped system timer
registers after a warm boot for the FVP. The system timers in FVP are
in the 'Always ON' power domain which meant the reinitialisation was
redundant and it could have conflicted with the setup the normal
world has done.
The programming of CNTACR(x) and CNTNSAR, the system timer registers,
are removed from the warm boot path with this patch.
Fixes ARM-software/tf-issues#169
Change-Id: Ie982eb03d1836b15ef3cf1568de2ea68a08b443e
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Set correct value for SYS_ID_REV_SHIFT in FVP
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The crash reporting support and early initialisation of the
cpu_data allow the runtime_exception vectors to be used from
the start in BL3-1, removing the need for the additional
early_exception vectors and 2KB of code from BL3-1.
Change-Id: I5f8997dabbaafd8935a7455910b7db174a25d871
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Moving the context pointers for each CPU into the per-cpu data
allows for much more efficient access to the contexts for the
current CPU.
Change-Id: Id784e210d63cbdcddb44ac1591617ce668dbc29f
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This patch prepares the per-cpu pointer cache for wider use by:
* renaming the structure to cpu_data and placing in new header
* providing accessors for this CPU, or other CPUs
* splitting the initialization of the TPIDR pointer from the
initialization of the cpu_data content
* moving the crash stack initialization to a crash stack function
* setting the TPIDR pointer very early during boot
Change-Id: Icef9004ff88f8eb241d48c14be3158087d7e49a3
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According to documentation, the Rev field is located at bit 28 in
the V2M sysid register.
Fixes ARM-software/tf-issues#179
Change-Id: I2abb7bdc092ccd3f41f8962dc8d8d8e44e8dfdc3
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Make the BL3-1 crash reporting optional
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Provide cm_get/set_context() for current CPU
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Make system register functions inline assembly v2
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Make the entry point argument optional in load_image()
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PL011: Fix a bug in the UART FIFO polling
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Include 'platform_def.h' header file in 'crash_reporting.S'
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fvp: Remove unused 'bl2_el_change_mem_ptr' variable
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This patch makes the console crash dump of processor register
state optional based on the CRASH_REPORTING make variable.
This defaults to only being enabled for DEBUG builds. This can
be overridden by setting a different value in the platform
makefile or on the make command line.
Change-Id: Icfa1b2d7ff0145cf0a85e8ad732f9cee7e7e993f
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All callers of cm_get_context() pass the calling CPU MPIDR to the
function. Providing a specialised version for the current
CPU results in a reduction in code size and better readability.
The current function has been renamed to cm_get_context_by_mpidr()
and the existing name is now used for the current-CPU version.
The same treatment has been done to cm_set_context(), although
only both forms are used at present in the PSCI and TSPD code.
Change-Id: I91cb0c2f7bfcb950a045dbd9ff7595751c0c0ffb
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Replace the current out-of-line assembler implementations of
the system register and system instruction operations with
inline assembler.
This enables better compiler optimisation and code generation
when accessing system registers.
Fixes ARM-software/tf-issues#91
Change-Id: I149af3a94e1e5e5140a3e44b9abfc37ba2324476
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'bl2_el_change_mem_ptr' variable is a left over from the former
BL2/BL3-1 interface.
Change-Id: Ib0979c8e2809e103a41f9c5cc4afec7dd21ac9ab
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There are cases where the entry point information is useless to the
caller, e.g. when an image just needs to be loaded in memory but won't
ever be executed.
This patch allows load_image() function to take a NULL pointer as the
entry point argument. In this case, it won't be populated.
Change-Id: Ie9394b054457706c6699926c5e0206e0c3851c56
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Before attempting to write a character, the PL011 driver polls
the PL011_UARTFR_TXFF bit to know whether the UART FIFO is full.
However, the comparison with 1 was incorrect because
PL011_UARTFR_TXFF is not at bit 0. This patch fixes it.
Change-Id: If78892345bbdc8a5e4ae4a1b7159753c609681b0
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'crash_reporting.S' needs to include 'platform_def.h' to get the
definition of PLATFORM_CORE_COUNT.
Note: On FVP it was compiling because 'platform_def.h' gets included
through 'plat/fvp/include/plat_macros.S' but we don't want to rely on
that for other platforms.
Change-Id: I51e974776dd0f3bda10ad9849f5ef7b30c629833
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This patch adds documentation that describes the design of the Interrupt
management framework in the ARM Trusted Firmware. The porting-guide.md has also
been updated to describe the interface that should be implemented by each
platform to support this framework.
Change-Id: I3eda48e5c9456e6a9516956bee16a29e366633b7
Co-Authored-By: Soby Mathew <soby.mathew@arm.com>
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Update documentation with BL3-1 hardening interface
changes and for using BL3-1 as a reset vector feature
Change-Id: Iafdd05e7a8e66503409f2acc934372efef5bc51b
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Updates to readme.md and change-log.md to describe the features and changes in
the v0.4 release.
Change-Id: Ice0a7cf7abae349f552e662eac638a46acc5db3f
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Update the Linux kernel, Linaro file system, FVP and DS-5 versions used for the
v0.4 release in user-guide.md.
Change-Id: I2265fc17c229d4b8cc52165d6583a4a579cdcee3
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Current ATF uses a direct physical-to-virtual mapping, that is, a physical
address is mapped to the same address in the virtual space. For example,
physical address 0x8000_0000 is mapped to 0x8000_0000 virtual. This
approach works fine for FVP as all its physical addresses fall into 0 to
4GB range. But for other platform where all I/O addresses are 48-bit long,
If we follow the same direct mapping, we would need virtual address range
from 0 to 0x8fff_ffff_ffff, which is about 144TB. This requires a
significant amount of memory for MMU tables and it is not necessary to use
that much virtual space in ATF.
The patch is to enable mapping a physical address range to an arbitrary
virtual address range (instead of flat mapping)
Changed "base" to "base_va" and added "base_pa" in mmap_region_t and
modified functions such as mmap_add_region and init_xlation_table etc.
Fixes ARM-software/tf-issues#158
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This patch modifies and adds to the existing documentation
for the crash reporting implementation in BL3-1.
Change-Id: I2cfbfeeeb64996ec7d19a9ddf95295482899b4bd
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Following recent refactoring changes to platform.h, this commit updates
porting-guide.md to correctly refer to platform.h and platform_def.h where
appropriate.
Change-Id: Idf1e77503c24358696f8f3c14caa0cc1d579deb4
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This patch fixes the compilation issue for trusted firmware when the
IMF_READ_INTERRUPT_ID is enabled.
Change-Id: I94ab613b9bc96a7c1935796c674dc42246aaafee
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The interrupt handling routine in BL3-1 expects a cookie as its last
parameter which was not being passed when invoking the interrupt
handler in BL3-1. This patch fixes that by passing a dummy cookie
parameter in the x3 register.
Fixes ARM-software/tf-issues#171
Change-Id: Ic98abbbd9f849e6f1c55343e865b5e0a4904a1c5
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bl2_main() was overwriting any platform set X1 parameter for BL3-1
with the value zero.
This patch ensure that any platform set value is correctly passed
to BL3-1. The FVP port adds a check to verify this parameter is
being passed correctly.
Fixes ARM-software/tf-issues#173
Change-Id: Ifbcda73d3d41d2b04a4baf5614e9d2d21f1717c8
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At present the arguments for BL3-3 in the entry_point_info
structure are not being transferred to X0-X7 before starting
execution of this image
This patch saves the args for BL3-3 into cpu context used
for its entry
Fixes ARM-software/tf-issues#172
Change-Id: I001b4b9bff6a264336f0d01d377619ae719f928b
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