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path: root/docs/cpu-specific-build-macros.md
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2017-06-29Remove Markdown documentationDouglas Raillard
Removed Markdown documents as they have been converted to reStructuredText. Change-Id: I3148222eb31258f158f64de4ddcdda4b232ce483 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-03-20Add workaround for ARM Cortex-A53 erratum 855873Andre Przywara
ARM erratum 855873 applies to all Cortex-A53 CPUs. The recommended workaround is to promote "data cache clean" instructions to "data cache clean and invalidate" instructions. For core revisions of r0p3 and later this can be done by setting a bit in the CPUACTLR_EL1 register, so that hardware takes care of the promotion. As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3, we set the bit in firmware. Also we dump this register upon crashing to provide more debug information. Enable the workaround for the Juno boards. Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2017-03-16Merge pull request #856 from antonio-nino-diaz-arm/an/dynamic-xlatdavidcunado-arm
Introduce version 2 of the translation tables library
2017-03-08Apply workaround for errata 813419 of Cortex-A57Antonio Nino Diaz
TLBI instructions for EL3 won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. This errata has been enabled for Juno. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-02-23Clarify errata ERRATA_A53_836870 documentationDouglas Raillard
The errata is enabled by default on r0p4, which is confusing given that we state we do not enable errata by default. This patch clarifies this sentence by saying it is enabled in hardware by default. Change-Id: I70a062d93e1da2416d5f6d5776a77a659da737aa Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-01-30Report errata workaround status to consoleJeenu Viswambharan
The errata reporting policy is as follows: - If an errata workaround is enabled: - If it applies (i.e. the CPU is affected by the errata), an INFO message is printed, confirming that the errata workaround has been applied. - If it does not apply, a VERBOSE message is printed, confirming that the errata workaround has been skipped. - If an errata workaround is not enabled, but would have applied had it been, a WARN message is printed, alerting that errata workaround is missing. The CPU errata messages are printed by both BL1 (primary CPU only) and runtime firmware on debug builds, once for each CPU/errata combination. Relevant output from Juno r1 console when ARM Trusted Firmware is built with PLAT=juno LOG_LEVEL=50 DEBUG=1: VERBOSE: BL1: cortex_a57: errata workaround for 806969 was not applied VERBOSE: BL1: cortex_a57: errata workaround for 813420 was not applied INFO: BL1: cortex_a57: errata workaround for disable_ldnp_overread was applied WARNING: BL1: cortex_a57: errata workaround for 826974 was missing! WARNING: BL1: cortex_a57: errata workaround for 826977 was missing! WARNING: BL1: cortex_a57: errata workaround for 828024 was missing! WARNING: BL1: cortex_a57: errata workaround for 829520 was missing! WARNING: BL1: cortex_a57: errata workaround for 833471 was missing! ... VERBOSE: BL31: cortex_a57: errata workaround for 806969 was not applied VERBOSE: BL31: cortex_a57: errata workaround for 813420 was not applied INFO: BL31: cortex_a57: errata workaround for disable_ldnp_overread was applied WARNING: BL31: cortex_a57: errata workaround for 826974 was missing! WARNING: BL31: cortex_a57: errata workaround for 826977 was missing! WARNING: BL31: cortex_a57: errata workaround for 828024 was missing! WARNING: BL31: cortex_a57: errata workaround for 829520 was missing! WARNING: BL31: cortex_a57: errata workaround for 833471 was missing! ... VERBOSE: BL31: cortex_a53: errata workaround for 826319 was not applied INFO: BL31: cortex_a53: errata workaround for disable_non_temporal_hint was applied Also update documentation. Change-Id: Iccf059d3348adb876ca121cdf5207bdbbacf2aba Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2016-04-21Doc: Add links to the A53/A57 Errata Notice documentsSandrine Bailleux
This patch adds links to the Cortex-A53 and Cortex-A57 MPCores Software Developers Errata Notice documents in the ARM CPU Specific Build Macros document. Change-Id: I0aa26d7f373026097ed012a02bc61ee2c5b9d6fc
2016-04-21Add support for Cortex-A57 erratum 833471 workaroundSandrine Bailleux
Change-Id: I86ac81ffd7cd094ce68c4cceb01c16563671a063
2016-04-21Add support for Cortex-A57 erratum 826977 workaroundSandrine Bailleux
Change-Id: Icaacd19c4cef9c10d02adcc2f84a4d7c97d4bcfa
2016-04-21Add support for Cortex-A57 erratum 829520 workaroundSandrine Bailleux
Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439
2016-04-21Add support for Cortex-A57 erratum 828024 workaroundSandrine Bailleux
Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d
2016-04-21Add support for Cortex-A57 erratum 826974 workaroundSandrine Bailleux
Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4
2016-02-18Cortex-A57: Add link to software optimization guideSandrine Bailleux
This patch adds a link to the Cortex-A57 Software Optimization Guide in the ARM CPU Specific Build Macros document to justify the default value of the A57_DISABLE_NON_TEMPORAL_HINT build flag. Change-Id: I9779e42a4bb118442b2b64717ce143314ec9dd16
2016-02-08Disable non-temporal hint on Cortex-A53/57Sandrine Bailleux
The LDNP/STNP instructions as implemented on Cortex-A53 and Cortex-A57 do not behave in a way most programmers expect, and will most probably result in a significant speed degradation to any code that employs them. The ARMv8-A architecture (see Document ARM DDI 0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint and treat LDNP/STNP as LDP/STP instead. This patch introduces 2 new build flags: A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT to enforce this behaviour on Cortex-A53 and Cortex-A57. They are enabled by default. The string printed in debug builds when a specific CPU errata workaround is compiled in but skipped at runtime has been generalised, so that it can be reused for the non-temporal hint use case as well. Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
2015-08-05cortex_a53: Add A53 errata #826319, #836870Jimmy Huang
- Apply a53 errata #826319 to revision <= r0p2 - Apply a53 errata #836870 to revision <= r0p3 - Update docs/cpu-specific-build-macros.md for newly added errata build flags Change-Id: I44918e36b47dca1fa29695b68700ff9bf888865e Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
2015-02-02Miscellaneous doc fixes for v1.1Sandrine Bailleux
Change-Id: Iaf9d6305edc478d39cf1b37c8a70ccdf723e8ef9
2015-01-07Create Table of Content links in markdown filesJoakim Bech
Fixes arm-software/tf-issues#276
2014-10-29Optimize Cortex-A57 cluster power down sequence on JunoSoby Mathew
This patch optimizes the Cortex-A57 cluster power down sequence by not flushing the Level1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. This optimization can be enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build flag. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This patch also renames the cpu-errata-workarounds.md to cpu-specific-build-macros.md as this facilitates documentation of both CPU Specific errata and CPU Specific Optimization build macros. Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
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