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2018-10-25MLK-20044 plat: imx8m: fix ddr4 dvfs hang after retentionBai Ping
The RFSHCTL3.refresh_mode should be set normal mode if we want to disable auto refresh mode. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-10-23imx8qxp: add support for cpuidleAnson Huang
This patch adds support for cpuidle with CPU powerdown, there will be 3 idle states in Linux kernel: 1: wfi; 2: cpu power down; 3: cluster power down. As Linux kernel needs a broadcast timer for waking up CPU when whole CLUSTER is powerdown, GPT is adopted as broadcast timer, and to make the clock & power management easy for Linux kernel to avoid many workaround/hake in Linux kernel, TF-A will handle GPT's power & clock management as well as registers save/restore when suspend/resume. Also, psci power states are used to determine CORE/CLUSTER/SYSTEM power state to distinguish CPU idle and SYSTEM suspend which share same domain_suspend callback. The SoC IPs register mmap regions are merged into 1 large section to cover all the SoC IPs register ranges TF-A needs, this is to save mmap regions and make it simple. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-10-12plat: imx8m: update the DVFS flow for DDR4Bai Ping
Update the DDR4 DVFS flow Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-10-12imx8m: Add DDR4 DVFS supportBai Ping
Add DDR4 DVFS support for i.MX8M. Currently, only tested on i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-10-12imx8qm: keep A53 cluster power on for cache coherency issueAnson Huang
A53 cluster cannot be power gated unless the entire multi-cluster (A53 + A72 + CCI) is gated off. Root cause still TBD, this patch adds temporary workaround to ONLY allow A53 power off when system suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-10-01imx8mm: Add ddr4 retention support for imx8mBai Ping
Add ddr4 retention flow for imx8m. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-28imx8qm/imx8qxp: enable output debug message to SC consoleAnson Huang
Add support for enabling output debug message to SC console, SC_CONSOLE is used to enable/disable it. Example log output on SC console as below: *** Debug Monitor *** >$ NOTICE: smc_fid is c2000003 imx_pwr_domain_on cluster_id 0, cpu_id 1 cluster:0 core:1 is on imx_pwr_domain_on cluster_id 0, cpu_id 2 cluster:0 core:2 is on imx_pwr_domain_on cluster_id 0, cpu_id 3 cluster:0 core:3 is on imx_pwr_domain_on cluster_id 1, cpu_id 0 cluster:1 core:0 is on imx_pwr_domain_on cluster_id 1, cpu_id 1 cluster:1 core:1 is on Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-26imx8qm/imx8qxp: add misc set temp SIP supportAnson Huang
Add FSL_SIP_MISC_SET_TEMP support for setting thermal alarm function. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-17plat: imx8mq: add 100us delay after USB OTG SRC bit 0 clearBai Ping
After the SRC bit clear, we must wait for a while to make sure the operation is finished. for USB OTG, the limitations are: 1. before system clock configuration. ipg clock runs at 12.5MHz. delay time should longer than 82us. 2. after system clock configuration. ipg clock runs at 66.5MHz. delay time should longer than 15.3us. so add udelay 100 to safely clear the SRC bit 0. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-15plat: imx8mm: Add support for imx8mm lpaAnson Huang
For i.MX8MM low power audio playback, when Linux suspend, M4 still needs to be active for audio playback, so system can NOT enter DSM mode but only force A core platform into STOP mode, PLLs/NoC/DRAM need to be active as well and MU interrupt wakeup needs to be enabled for waking up Linux by MU message sent by M4. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-13imx8mq: fix soc_id issueAnson Huang
The chip revision should ONLY overwrite the lower 16 bits of soc_id, otherwise, the cpu_is_imx8mq() API in Linux kernel will be incorrect. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-12MA-11015 Support Trusty OS on imx8qm/qxpHaoran.Wang
The Trusty OS binary will be installed into container.img and loaded into 0x84000000. Due Trusty OS addresss is in 0xfe000000 which ROM cannot reach, so use ATF to copy it into the target address. Mapped the BL32 code into MMU due the Trusty SPD need to check the code status and decide the CPU executing mode. To reserve and protect the memory for secure world, modify the partition code to keep BL32 spaces in secure_part. Signed-off-by: Haoran.Wang <elven.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2018-09-11plat: imx8mm: fix the gpumix vpumix power downBai Ping
the GPU/VPU mix power off is skip in previous code, so correct to make sure GPU/VPU mix is actually power off. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-08imx8qm/imx8qxp: support random CPU resume when system suspendAnson Huang
Using sc_pm_set_cpu_resume API instead of sc_pm_set_cpu_resume_addr to support random CPU resume for system suspend, as Linux kernel now supports non CPU0 suspend, we have to specify the CPU ID for SCFW to wake up when system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-07plat: imx8mm: Read mode register setting from ddrcOliver Chen
Read the mode register setting from the DDRC, then we can make the DVFS flow more indepent from the actual DDR config. Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-06MLK-19465 imx8mq: Fix cpu rev issue on B0.1 chipYe Li
On B0.1 chip, the value is 0x1020 not 0x20, due to minor version updated. So if reading the word and comparing with 0x20, the result is wrong. Fix the issue by only reading low major version byte for ROM version Signed-off-by: Ye Li <ye.li@nxp.com>
2018-09-03imx8mq: update chip revision method for B1Anson Huang
i.MX8MQ B1's chip revision is identified by reading OCOTP offset 0x40, the magic number 0xff0055aa is for B1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-31plat: imx8mq: update the ddr controller perf QoS settingBai Ping
update the ddr controller perf QoS setting on i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-27MLK-18619: [MX8MM-EVK]CSU_RDC: enable csu_rdc test in ATF make the board crashFranck LENORMAND
csu_rdc test in ATF makes use of GPIO 4 and 5. Unfortunatly GPIO5 is being used by u-boot. This is why u-boot crashes. Changing the peripherals to protect, instead of gpio4 and 5, use csu and rdc registers instead. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
2018-08-27imx8qm: put IRQ_STEER/DRC/DBLOGIC into OFF when suspendAnson Huang
To support KS1, need to put all resources into OFF mode instead of STBY when Linux kernel suspend. Here, DRC, IRQ_STEER and DBLOGIC can be OFF for KS1 mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-22imx8mq:plat: add noc priority configuration entryZhang Bo
Add NOC configuration entry for all the module. Kernel can configure the noc priority through this entry. Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
2018-08-21MLK-19263 imx8m: hab: Add check target and failsafe sip callYe Li
imx_v2018.03 u-boot uses ROM's APIs: check_target and failsafe. So for iMX8M platforms, we have to implement the sip calls and use ATF to call them when u-boot running at non-secure world. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-08-21plat: imx8mm: fix system resume hang when tz380 is enabledBai Ping
If NOC is power down in DSM mode, the tz380 register config will be lost, so we must re-init the tz380 after system resume. the tz380 initialization must be done after DRAM has been out of retention. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-20MLK-19256 plat: imx8mm: correct dram apb clock rate dvfsBai Ping
The DRAM APB bus clock rate is wrong before and after DVFS. The register offset for APB bus clock is wrong, so fix it. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-15imx8qxp: put DRC into OFF mode when Linux suspendAnson Huang
SCFW has supported DDR retention, so now DRC can be into OFF mode instead of STBY when Linux suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-02plat: imx8mm: enable noc power down supportBai Ping
enable NOC power down in DSM mode. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-26imx8: postpone moving resources to non-secure partitionPeng Fan
With flash_uboot_cm4ddr in imx-mkimage, the m4 code will access ddr. However after m4 core moved to non-secure partition, the ddr memory is still in secure partition. Then m4 core will fault. So postpone moving resources including m4 core, until other resources, such as memory/pin moved to non-secure partition. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1c8ce0ad5f583ec41026d4ab5bef622f1b45aecd)
2018-07-26plat: imx8mm: enable power domain supportBai Ping
Enable the power domain support on imx8mm. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-20plat: imx8mm: Add lpddr4 dvfs supportBai Ping
add LPDDR4 DVFS support on imx8mm. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-20plat: imx: refact the dram retention flow on imx8mmBai Ping
All the DRAM timing related config is saved by SPL in OCRAM_S, so no need to do save for these configs in ATF anymore. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-20PLAT: imx: Change the bl31 base address to 0x920000 for imx8mmBai Ping
On i.MX8MM, the OCRAM's last 128K is dedicated for ATF, so move bl31 to this memory region. BuildInfo: - IMX-MKIMAGE: ee5ad91b Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-05imx8mq/imx8mm: make sure no overlap during memory mapAnson Huang
The debug version of TF-A has below assert, fix it by making sure no memory map overlap. ASSERT: lib/xlat_tables/xlat_tables_common.c:129 Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-05imx8mq/imx8mm: switch to MULTI_CONSOLE_API for debug uart supportAnson Huang
Switch to MULTI_CONSOLE_API to make debug UART work. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-05imx8qm/imx8qxp: switch to MULTI_CONSOLE_API for debug uart supportAnson Huang
Switch to MULTI_CONSOLE_API to make debug UART work. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-04plat: imx: fix boot hang on imx8mm ddr4 boardBai Ping
skip init the dram info if the ddr type is DDR4, support for it will be added later. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-03MLK-18732-2: Add OTP SIP service for QM/QXTeo Hall
Add SIP service for OTP reading/writing for use in u-boot Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-07-03MLK-18732-1: Update to the latest SCFW APITeo Hall
Update API based on following commit: commit 24fa33d2f95707e739f01cc04d38a62bec707ceb Author: Chuck Cannon <chuck.cannon@nxp.com> Date: Thu Jun 28 15:00:03 2018 -0500 SCF-105: Add disclaimer to docs. Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com> For use of the misc otp service Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-06-21imx: enable necessary erratas for A53 r0p4Anson Huang
This patch enables necessary erratas for A53 r0p4 according to docs/cpu-specific-build-macros.rst. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-21Merge pull request #1397 from dp-arm/dp/cortex-a76Dimitris Papastamos
Add support for Cortex-A76 and Cortex-Ares
2018-06-20imx8qxp: support SC_R_IRQSTR_SCU2 OFF in system suspendAnson Huang
SC_R_IRQSTR_SCU2 can be OFF in system suspend if there is no wakeup irq enabled from non-secure OS partion. Add wakeup source check to decide if turning off SC_R_IRQSTR_SCU2 or NOT when suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-20plat: imx: fix smp boot hang issue when GIC is power downBai Ping
When GIC is power down, all the GIC state will be lost. All the redistributor's state need save/resotre. Additionally, the redistributor's restore need to be done after distributor Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-20imx8qxp: turn off DB when linux suspendAnson Huang
DB is NOT necessary for irqsteer on i.MX8QXP, it can be OFF when linux suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-20imx8qm: support MU power off during suspendAnson Huang
Add MU power off support for suspend, it needs to be re-initialized after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-20imx8qxp: support MU power off during suspendAnson Huang
Add MU power off support for suspend, it needs to be re-initialized after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11plat: imx8mm: mask the non-wakeup irq in low power modeBai Ping
Only enable the wakeup irq when system enter DSM mode. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mm: use ARRAY_SIZE instead of magic numberBai Ping
use ARRAY_SIZE to get the array size. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mm: enable DSM mode support on imx8mmBai Ping
enable DSM mode on i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8m: add a common dram PM code for imx8m socBai Ping
re-design the dram power management code to make it more common for all i.MX8M SOCs. code need to refact and optimize to make more better. Using this common code on i.MX8MM first, for i.MX8MQ, will move to this later. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mm: switch the CKIL clock source to 32K OSCBai Ping
Switch the CKIL clock source to 32K OSC. On i.MX8MM, after SOC PoR, the default clock source for CKIL is from divided 24MHz OSC, as 24MHz OSC will be power down when system enters DSM mdoe. So it is better to use 32K OSC as the default clock source after system bootup. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mm: enable PU domains' clocks before power upBai Ping
VPU, GPU and PCIE's clock need to be on before power on these power domains. Signed-off-by: Bai Ping <ping.bai@nxp.com>
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